From c7c52865252fc2106134cc50ce4823ef78d7e10e Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 25 Nov 2013 18:33:12 +0100 Subject: ahci-tegra: add avdd_plle regulator When enabling SATA clocks, the PCIE clocks are enabled as well since those are the parent clocks. In order to enable this parent clocks, the PCIE regulator avdd_plle needs to be enabled. The resume path used to freeze because the PCIE PLL did not lock. --- drivers/ata/ahci-tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ata/ahci-tegra.c b/drivers/ata/ahci-tegra.c index c90472827b9b..32bf46940b0f 100644 --- a/drivers/ata/ahci-tegra.c +++ b/drivers/ata/ahci-tegra.c @@ -217,6 +217,7 @@ enum sata_state { }; char *sata_power_rails[] = { + "avdd_plle", "avdd_sata", "vdd_sata", "hvdd_sata", -- cgit v1.2.3