From 716b9cbb91450161b36a4fe686c75449a1d355ad Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 24 Aug 2016 16:39:19 -0700 Subject: ARM: dts: imx7-colibri: select MCLK in SGTL5000 node The SGTL5000 requires a MCLK frequency in the range of 8 to 27MHz to work properly. Make sure the clocking requirements are met by setting the clock within the codecs node. Signed-off-by: Stefan Agner Acked-by: Max Krummenacher --- arch/arm/boot/dts/imx7-colibri.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 48b260a23127..f56fa805a8e4 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -76,10 +76,6 @@ "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT"; - assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, - <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <12288000>; }; m4_tcm: tcml@007f8000 { @@ -176,6 +172,10 @@ pinctrl-0 = <&pinctrl_sai1_mclk>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <12288000>; }; ad7879@2c { -- cgit v1.2.3