From 506577cc0e43d6e0e15a26ca1c521b7909036e05 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Mon, 27 Jun 2022 09:47:43 +0200 Subject: arm64: dts: apalis-imx8: add sd card sleep state This adds SD card sleep state and relevant pinmux configuration for Apalis iMX8 boards. Pins for sleep state are configured for pull-disable, except card detect pin which is always pull-up. Signed-off-by: Andrejs Cainikovs --- .../boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi | 30 ++------- .../boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi | 30 ++------- .../arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi | 76 ++++++++++++++++++---- 3 files changed, 72 insertions(+), 64 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi index db2832a4500f..c7ae93c55e7d 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -270,28 +270,6 @@ IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x21 >; }; - - /* Apalis MMC1_CD# */ - pinctrl_mmc1_cd: mmc1cdgrp { - fsl,pins = < - IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000061 - >; - }; - - /* Apalis MMC1 */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - - /* On-module PMIC use */ - IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; }; }; @@ -427,10 +405,10 @@ /* Apalis MMC1 */ &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; - pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; - pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>; bus-width = <4>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi index 2591656645e0..51fffcc6a791 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -308,28 +308,6 @@ >; }; - /* Apalis MMC1_CD# */ - pinctrl_mmc1_cd: mmc1cdgrp { - fsl,pins = < - IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000061 - >; - }; - - /* Apalis MMC1 */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - - /* On-module PMIC use */ - IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; - /* PMIC MMC1 power-switch */ pinctrl_enable_3v3_vmmc: enable_3v3_vmmc { fsl,pins = < @@ -478,10 +456,10 @@ /* Apalis MMC1 */ &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; - pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; - pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>; bus-width = <4>; cap-power-off-card; vmmc-supply = <®_3v3_vmmc>; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index 601fb7942478..0ece42889af8 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -713,8 +713,14 @@ >; }; + pinctrl_mmc1_cd_sleep: mmc1cdgrpsleep { + fsl,pins = < + IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x04000021 + >; + }; + /* Apalis MMC1 */ - pinctrl_usdhc2: usdhc2grp { + pinctrl_usdhc2_4bit: usdhc2grp4bit { fsl,pins = < IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 @@ -722,16 +728,21 @@ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + /* On-module PMIC use */ + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_8bit: usdhc2grp8bit { + fsl,pins = < IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021 IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021 IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021 IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021 - /* On-module PMIC use */ - IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_4bit_100mhz: usdhc2grp4bit100mhz { fsl,pins = < IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 @@ -739,16 +750,21 @@ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + /* On-module PMIC use */ + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp8bit100mhz { + fsl,pins = < IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020 IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020 IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020 IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020 - /* On-module PMIC use */ - IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_4bit_200mhz: usdhc2grp4bit200mhz { fsl,pins = < IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 @@ -756,12 +772,39 @@ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + /* On-module PMIC use */ + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp8bit200mhz { + fsl,pins = < IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020 IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020 IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020 IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020 + >; + }; + + pinctrl_usdhc2_4bit_sleep: usdhc2grp4bitsleep { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x04000061 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x04000061 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x04000061 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x04000061 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x04000061 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x04000061 /* On-module PMIC use */ - IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_8bit_sleep: usdhc2grp8bitsleep { + fsl,pins = < + IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x04000061 + IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x04000061 + IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x04000061 + IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x04000061 >; }; @@ -1764,10 +1807,19 @@ /* Apalis MMC1 */ &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_mmc1_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_mmc1_cd>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_4bit>, + <&pinctrl_usdhc2_8bit>, + <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, + <&pinctrl_usdhc2_8bit_100mhz>, + <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, + <&pinctrl_usdhc2_8bit_200mhz>, + <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, + <&pinctrl_usdhc2_8bit_sleep>, + <&pinctrl_mmc1_cd_sleep>; bus-width = <8>; cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ no-1-8-v; -- cgit v1.2.3