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-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp.dtsi563
1 files changed, 165 insertions, 398 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 1133b412182a..89f6f168cd4b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
@@ -9,7 +9,9 @@
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
@@ -17,6 +19,8 @@
#size-cells = <2>;
aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &fec2;
gpio0 = &lsio_gpio0;
gpio1 = &lsio_gpio1;
gpio2 = &lsio_gpio2;
@@ -25,17 +29,40 @@
gpio5 = &lsio_gpio5;
gpio6 = &lsio_gpio6;
gpio7 = &lsio_gpio7;
+ dpu0 = &dpu1;
+ ldb0 = &ldb1;
+ ldb1 = &ldb2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
mu1 = &lsio_mu1;
- serial0 = &adma_lpuart0;
- serial1 = &adma_lpuart1;
- serial2 = &adma_lpuart2;
- serial3 = &adma_lpuart3;
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ isi0 = &isi_0;
+ isi1 = &isi_1;
+ isi2 = &isi_2;
+ isi3 = &isi_3;
+ isi4 = &isi_4;
+ isi5 = &isi_5;
+ isi6 = &isi_6;
+ isi7 = &isi_7;
+ csi0 = &mipi_csi_0;
+ can0 = &flexcan1;
+ can1 = &flexcan2;
+ can2 = &flexcan3;
+ i2c1 = &i2c_rpbus_1;
+ i2c5 = &i2c_rpbus_5;
+ i2c12 = &i2c_rpbus_12;
+ i2c13 = &i2c_rpbus_13;
+ i2c14 = &i2c_rpbus_14;
+ i2c15 = &i2c_rpbus_15;
+ mipi_dsi0 = &mipi0_dsi_host;
+ mipi_dsi1 = &mipi1_dsi_host;
};
- cpus {
+ cpus: cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -46,7 +73,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -57,7 +84,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -68,7 +95,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -79,7 +106,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
- clocks = <&clk IMX_A35_CLK>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
@@ -152,9 +179,16 @@
&lsio_mu1 1 3
&lsio_mu1 3 3>;
+ pd: imx8qx-pd {
+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ wakeup-irq = <235 236 237 258 262 267 271
+ 345 346 347 348>;
+ };
+
clk: clock-controller {
- compatible = "fsl,imx8qxp-clk";
- #clock-cells = <1>;
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
+ #clock-cells = <2>;
clocks = <&xtal32k &xtal24m>;
clock-names = "xtal_32KHz", "xtal_24Mhz";
};
@@ -167,21 +201,40 @@
compatible = "fsl,imx8qxp-scu-ocotp";
#address-cells = <1>;
#size-cells = <1>;
- };
+ read-only;
- pd: imx8qx-pd {
- compatible = "fsl,imx8qxp-scu-pd";
- #power-domain-cells = <1>;
+ fec_mac0: mac@2c4 {
+ reg = <0x2c4 6>;
+ };
+
+ fec_mac1: mac@2c6 {
+ reg = <0x2c6 6>;
+ };
};
rtc: rtc {
compatible = "fsl,imx8qxp-sc-rtc";
};
+ secvio: secvio {
+ compatible = "fsl,imx-sc-secvio";
+ nvmem = <&ocotp>;
+ };
+
watchdog {
compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
timeout-sec = <60>;
};
+
+ tsens: thermal-sensor {
+ compatible = "fsl,imx8qxp-sc-thermal";
+ tsens-num = <2>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ soc {
+ compatible = "fsl,imx8qxp-soc";
};
timer {
@@ -192,6 +245,43 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
};
+ thermal_zones: thermal-zones {
+ cpu-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens 355>;
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit0: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ clk_dummy: clock-dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "clk_dummy";
+ };
+
xtal32k: clock-xtal32k {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -206,395 +296,72 @@
clock-output-names = "xtal_24MHz";
};
- adma_subsys: bus@59000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x59000000 0x0 0x59000000 0x2000000>;
-
- adma_lpcg: clock-controller@59000000 {
- compatible = "fsl,imx8qxp-lpcg-adma";
- reg = <0x59000000 0x2000000>;
- #clock-cells = <1>;
- };
-
- adma_dsp: dsp@596e8000 {
- compatible = "fsl,imx8qxp-dsp";
- reg = <0x596e8000 0x88000>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
- clock-names = "ipg", "ocram", "core";
- power-domains = <&pd IMX_SC_R_MU_13A>,
- <&pd IMX_SC_R_MU_13B>,
- <&pd IMX_SC_R_DSP>,
- <&pd IMX_SC_R_DSP_RAM>;
- mbox-names = "txdb0", "txdb1",
- "rxdb0", "rxdb1";
- mboxes = <&lsio_mu13 2 0>,
- <&lsio_mu13 2 1>,
- <&lsio_mu13 3 0>,
- <&lsio_mu13 3 1>;
- memory-region = <&dsp_reserved>;
- status = "disabled";
- };
-
- adma_lpuart0: serial@5a060000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x5a060000 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_0>;
- status = "disabled";
- };
-
- adma_lpuart1: serial@5a070000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x5a070000 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_1>;
- status = "disabled";
- };
-
- adma_lpuart2: serial@5a080000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x5a080000 0x1000>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_2>;
- status = "disabled";
- };
-
- adma_lpuart3: serial@5a090000 {
- compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x5a090000 0x1000>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
- <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
- clock-names = "ipg", "baud";
- power-domains = <&pd IMX_SC_R_UART_3>;
- status = "disabled";
- };
-
- adma_i2c0: i2c@5a800000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x5a800000 0x4000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_0>;
- status = "disabled";
- };
-
- adma_i2c1: i2c@5a810000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x5a810000 0x4000>;
- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_1>;
- status = "disabled";
- };
-
- adma_i2c2: i2c@5a820000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x5a820000 0x4000>;
- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_2>;
- status = "disabled";
- };
-
- adma_i2c3: i2c@5a830000 {
- compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x5a830000 0x4000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
- clock-names = "per";
- assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
- assigned-clock-rates = <24000000>;
- power-domains = <&pd IMX_SC_R_I2C_3>;
- status = "disabled";
- };
+ imx_ion {
+ compatible = "fsl,mxc-ion";
+ fsl,heap-id = <0>;
};
- conn_subsys: bus@5b000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
-
- conn_lpcg: clock-controller@5b200000 {
- compatible = "fsl,imx8qxp-lpcg-conn";
- reg = <0x5b200000 0xb0000>;
- #clock-cells = <1>;
- };
-
- usdhc1: mmc@5b010000 {
- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x5b010000 0x10000>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
- clock-names = "ipg", "per", "ahb";
- assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
- assigned-clock-rates = <200000000>;
- power-domains = <&pd IMX_SC_R_SDHC_0>;
- status = "disabled";
- };
-
- usdhc2: mmc@5b020000 {
- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x5b020000 0x10000>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
- clock-names = "ipg", "per", "ahb";
- assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
- assigned-clock-rates = <200000000>;
- power-domains = <&pd IMX_SC_R_SDHC_1>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
- status = "disabled";
- };
-
- usdhc3: mmc@5b030000 {
- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x5b030000 0x10000>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
- clock-names = "ipg", "per", "ahb";
- assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
- assigned-clock-rates = <200000000>;
- power-domains = <&pd IMX_SC_R_SDHC_2>;
- status = "disabled";
- };
-
- fec1: ethernet@5b040000 {
- compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
- reg = <0x5b040000 0x10000>;
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
- clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
- fsl,num-tx-queues=<3>;
- fsl,num-rx-queues=<3>;
- power-domains = <&pd IMX_SC_R_ENET_0>;
- status = "disabled";
- };
-
- fec2: ethernet@5b050000 {
- compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
- reg = <0x5b050000 0x10000>;
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
- clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
- fsl,num-tx-queues=<3>;
- fsl,num-rx-queues=<3>;
- power-domains = <&pd IMX_SC_R_ENET_1>;
- status = "disabled";
- };
+ rpmsg: rpmsg{
+ compatible = "fsl,imx8qxp-rpmsg";
+ /* up to now, the following channels are used in imx rpmsg
+ * - tx1/rx1: messages channel.
+ * - general interrupt1: remote proc finish re-init rpmsg stack
+ * when A core is partition reset.
+ */
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&lsio_mu5 0 1
+ &lsio_mu5 1 1
+ &lsio_mu5 3 1>;
+ mub-partition = <3>;
+ status = "disabled";
};
- ddr_subsyss: bus@5c000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
-
- ddr-pmu@5c020000 {
- compatible = "fsl,imx8-ddr-pmu";
- reg = <0x5c020000 0x10000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- };
+ sc_pwrkey: sc-powerkey {
+ compatible = "fsl,imx8-pwrkey";
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
};
- lsio_subsys: bus@5d000000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
-
- lsio_gpio0: gpio@5d080000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d080000 0x10000>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_0>;
- };
-
- lsio_gpio1: gpio@5d090000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d090000 0x10000>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_1>;
- };
-
- lsio_gpio2: gpio@5d0a0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0a0000 0x10000>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_2>;
- };
-
- lsio_gpio3: gpio@5d0b0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0b0000 0x10000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_3>;
- };
-
- lsio_gpio4: gpio@5d0c0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0c0000 0x10000>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_4>;
- };
-
- lsio_gpio5: gpio@5d0d0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0d0000 0x10000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_5>;
- };
-
- lsio_gpio6: gpio@5d0e0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0e0000 0x10000>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_6>;
- };
-
- lsio_gpio7: gpio@5d0f0000 {
- compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
- reg = <0x5d0f0000 0x10000>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- power-domains = <&pd IMX_SC_R_GPIO_7>;
- };
-
- lsio_mu0: mailbox@5d1b0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d1b0000 0x10000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- status = "disabled";
- };
-
- lsio_mu1: mailbox@5d1c0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d1c0000 0x10000>;
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- };
-
- lsio_mu2: mailbox@5d1d0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d1d0000 0x10000>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- status = "disabled";
- };
-
- lsio_mu3: mailbox@5d1e0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d1e0000 0x10000>;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- status = "disabled";
- };
+ /* sorted in register address */
+ #include "imx8-ss-security.dtsi"
+ #include "imx8-ss-cm40.dtsi"
+ #include "imx8-ss-vpu.dtsi"
+ #include "imx8-ss-dc0.dtsi"
+ #include "imx8-ss-adma.dtsi"
+ #include "imx8-ss-conn.dtsi"
+ #include "imx8-ss-ddr.dtsi"
+ #include "imx8-ss-lsio.dtsi"
+ #include "imx8-ss-hsio.dtsi"
+ #include "imx8-ss-img.dtsi"
+ #include "imx8-ss-gpu0.dtsi"
+ #include "imx8-ss-lcdif.dtsi"
+};
- lsio_mu4: mailbox@5d1f0000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d1f0000 0x10000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- status = "disabled";
- };
+#include "imx8qxp-ss-adma.dtsi"
+#include "imx8qxp-ss-conn.dtsi"
+#include "imx8qxp-ss-lsio.dtsi"
+#include "imx8qxp-ss-hsio.dtsi"
+#include "imx8qxp-ss-img.dtsi"
+#include "imx8qxp-ss-dc.dtsi"
+#include "imx8qxp-ss-lvds.dtsi"
+#include "imx8qxp-ss-gpu.dtsi"
+
+&edma2 {
+ status = "okay";
+};
- lsio_mu13: mailbox@5d280000 {
- compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
- reg = <0x5d280000 0x10000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- power-domains = <&pd IMX_SC_R_MU_13A>;
- };
+&A35_0 {
+ operating-points = <
+ /* kHz uV*/
+ /* voltage is maintained by SCFW, so no need here */
+ 1200000 0
+ 900000 0
+ >;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+ clock-latency = <61036>;
+ #cooling-cells = <2>;
+};
- lsio_lpcg: clock-controller@5d400000 {
- compatible = "fsl,imx8qxp-lpcg-lsio";
- reg = <0x5d400000 0x400000>;
- #clock-cells = <1>;
- };
- };
+&dsp {
+ memory-region = <&dsp_reserved>;
};
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-10 01:11:21 +0000