diff options
Diffstat (limited to 'arch/arm/mach-mx6/pads-apalis_imx6.h')
| -rw-r--r-- | arch/arm/mach-mx6/pads-apalis_imx6.h | 303 |
1 files changed, 194 insertions, 109 deletions
diff --git a/arch/arm/mach-mx6/pads-apalis_imx6.h b/arch/arm/mach-mx6/pads-apalis_imx6.h index 9eea5fa93ec2..3e28478c13d1 100644 --- a/arch/arm/mach-mx6/pads-apalis_imx6.h +++ b/arch/arm/mach-mx6/pads-apalis_imx6.h @@ -14,69 +14,34 @@ #define MX6NAME(a) mx6q_##a #endif -#define MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define MX6Q_USDHC_PAD_CTRL_50MHZ MX6Q_USDHC_PAD_CTRL -#define MX6Q_PAD_SD3_CLK__USDHC3_CLK MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ -#define MX6Q_PAD_SD3_CMD__USDHC3_CMD MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ -#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ -#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ -#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ -#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ -#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ -#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ -#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ -#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ -#define MX6Q_PAD_SD4_CLK__USDHC4_CLK MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ -#define MX6Q_PAD_SD4_CMD__USDHC4_CMD MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ -#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ -#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ -#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ -#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ - -#define MX6DL_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ -#define MX6DL_USDHC_PAD_CTRL_50MHZ MX6DL_USDHC_PAD_CTRL -#define MX6DL_PAD_SD3_CLK__USDHC3_CLK MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ -#define MX6DL_PAD_SD3_CMD__USDHC3_CMD MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ -#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ -#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ -#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ -#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ -#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4 MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ -#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5 MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ -#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6 MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ -#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7 MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ -#define MX6DL_PAD_SD4_CLK__USDHC4_CLK MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ -#define MX6DL_PAD_SD4_CMD__USDHC4_CMD MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ -#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ -#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ -#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ -#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ - -#define NP(id, pin, pad_ctl) \ - NEW_PAD_CTRL(MX6PAD(SD##id##_##pin##__USDHC##id##_##pin), MX6(pad_ctl)) - -#define SD_PINS(id, pad_ctl) \ - NP(id, CLK, pad_ctl), \ - NP(id, CMD, pad_ctl), \ - NP(id, DAT0, pad_ctl), \ - NP(id, DAT1, pad_ctl), \ - NP(id, DAT2, pad_ctl), \ - NP(id, DAT3, pad_ctl) - -static iomux_v3_cfg_t MX6NAME(nitrogen6x_pads)[] = { -#ifdef TODO - NEW_PAD_CTRL(MX6PAD(NANDF_CS1__GPIO_6_14), N6_IRQ_PADCFG), /* wl1271 wl_irq */ -#endif - static iomux_v3_cfg_t MX6NAME(common_pads)[] = { /* CCM */ - MX6PAD(GPIO_5__CCM_CLKO), /* local AC97 sys_mclk */ + MX6PAD(GPIO_5__CCM_CLKO), /* I2S sys_mclk */ MX6PAD(NANDF_CS2__CCM_CLKO2), /* MXM193 CAM1_MCLK */ + /* Apalis GPIO */ + MX6PAD(NANDF_D4__GPIO_2_4), /* 1 */ + MX6PAD(NANDF_D5__GPIO_2_5), /* 2 */ + MX6PAD(NANDF_D6__GPIO_2_6), /* 3 */ + MX6PAD(NANDF_D7__GPIO_2_7), /* 4 */ + MX6PAD(NANDF_RB0__GPIO_6_10), /* 5 */ + MX6PAD(NANDF_WP_B__GPIO_6_9), /* 6 */ + MX6PAD(GPIO_2__GPIO_1_2), /* 7 */ + MX6PAD(GPIO_6__GPIO_1_6), /* 8 */ + + /* Apalis SPI1, ECSPI1 */ + MX6PAD(CSI0_DAT6__ECSPI1_MISO), + MX6PAD(CSI0_DAT5__ECSPI1_MOSI), + MX6PAD(CSI0_DAT4__ECSPI1_SCLK), + MX6PAD(CSI0_DAT7__ECSPI1_SS0), + + /* Apalis SPI2, ECSPI2 */ + MX6PAD(EIM_CS1__ECSPI2_MOSI), + MX6PAD(EIM_CS0__ECSPI2_SCLK), + MX6PAD(EIM_OE__ECSPI2_MISO), + MX6PAD(EIM_RW__ECSPI2_SS0), + /* ENET */ MX6PAD(ENET_MDIO__ENET_MDIO), MX6PAD(ENET_MDC__ENET_MDC), @@ -136,8 +101,8 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = { MX6PAD(EIM_DA12__IPU1_CSI1_VSYNC), /* GPIO3[12] */ MX6PAD(EIM_A16__IPU1_CSI1_PIXCLK), /* GPIO2[22] */ #else - MX6PAD(EIM_EB2__IPU2_CSI1_D_19), /* GPIO2[30] */ #ifdef TODO + MX6PAD(EIM_EB2__IPU2_CSI1_D_19), /* GPIO2[30] */ MX6PAD(EIM_A23__IPU2_CSI1_D_18), /* GPIO6[6] */ MX6PAD(EIM_A22__IPU2_CSI1_D_17), /* GPIO2[16] */ MX6PAD(EIM_A21__IPU2_CSI1_D_16), /* GPIO2[17] */ @@ -163,33 +128,50 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = { MX6PAD(EIM_A16__IPU2_CSI1_PIXCLK), /* GPIO2[22] */ #endif #endif - MX6PAD(EIM_DA13__GPIO_3_13), /* Power */ - MX6PAD(EIM_DA14__GPIO_3_14), /* Reset */ - MX6PAD(EIM_WAIT__GPIO_5_0), /* Irq */ + MX6PAD(EIM_DA13__GPIO_3_13), /* BKL1_ON */ + MX6PAD(EIM_DA14__GPIO_3_14), /* BKL1_PWM */ + MX6PAD(EIM_A25__GPIO_5_2), /* BKL1_PWM_EN */ + MX6PAD(EIM_BCLK__GPIO_6_31), /* VGA_PSAVE# */ + + MX6PAD(KEY_ROW2__HDMI_TX_CEC_LINE), /* HDMI CEC */ + + MX6PAD(EIM_WAIT__GPIO_5_0), /* TS_6 */ #ifdef TODO MX6PAD(EIM_A24__GPIO_5_4), /* Field */ #endif - MX6PAD(EIM_RW__GPIO_2_26), /* GPIO2[26] - unused */ - MX6PAD(EIM_LBA__GPIO_2_27), /* GPIO2[27] - unused */ + MX6PAD(EIM_LBA__GPIO_2_27), /* DAP1_RESET */ #ifdef TODO MX6PAD(EIM_EB3__GPIO_2_31), /* GPIO2[31] - unused */ #endif - MX6PAD(EIM_DA15__GPIO_3_15), /* GPIO3[15] - unused */ + MX6PAD(EIM_DA15__GPIO_3_15), /* SATA1_ACT# */ /* NANDF_CS1/2/3 are unused for sabrelite */ - NEW_PAD_CTRL(MX6PAD(NANDF_CS1__GPIO_6_14), N6_IRQ_TEST_PADCFG), /* wl1271 wl_irq */ - NEW_PAD_CTRL(MX6PAD(NANDF_CS3__GPIO_6_16), N6_EN_PADCFG), /* wl1271 bt_en */ + MX6PAD(NANDF_CS1__GPIO_6_14), /* SD1_CD# */ + MX6PAD(NANDF_CS3__GPIO_6_16), /* TS_DIFF6- */ - /* GPIO7 */ - MX6PAD(GPIO_17__GPIO_7_12), /* USB Hub Reset */ - MX6PAD(GPIO_18__GPIO_7_13), /* J14 - Volume Up */ + MX6PAD(GPIO_16__SPDIF_IN1), /* SPDIF1_IN */ + MX6PAD(GPIO_17__SPDIF_OUT1), /* SPDIF1_OUT */ + MX6PAD(GPIO_18__GPIO_7_13), /* PWR_INT */ + MX6PAD(DI0_PIN4__GPIO_4_20), /* MMC1_CD# */ - /* DISPLAY */ - NEW_PAD_CTRL(MX6PAD(DI0_PIN4__GPIO_4_20), - WEAK_PULLUP), /* I2C Touch IRQ */ - MX6PAD(GPIO_7__GPIO_1_7), /* J7 - Display Connector GP */ - MX6PAD(GPIO_9__GPIO_1_9), /* J7 - Display Connector GP */ + /* Apalis CAN1 */ + MX6PAD(GPIO_7__CAN1_TXCAN), + MX6PAD(GPIO_8__CAN1_RXCAN), + /* Apalis CAN2 */ + MX6PAD(KEY_ROW4__CAN2_RXCAN), + MX6PAD(KEY_COL4__CAN2_TXCAN), +#ifdef TODO + MX6PAD(GPIO_2__GPIO_1_2), /* STNDBY */ + MX6PAD(GPIO_7__GPIO_1_7), /* NERR */ + NEW_PAD_CTRL(MX6PAD(GPIO_7__GPIO_1_7), CAN1_ERR_TEST_PADCFG), + MX6PAD(GPIO_4__GPIO_1_4), /* Enable */ +#endif + + MX6PAD(GPIO_9__PWM1_PWMO), /* PWM1 */ + MX6PAD(GPIO_1__PWM2_PWMO), /* PWM2 */ + MX6PAD(SD4_DAT1__PWM3_PWMO), /* PWM3 */ + MX6PAD(SD4_DAT2__PWM4_PWMO), /* PWM4 */ #ifdef TODO MX6PAD(NANDF_D0__GPIO_2_0), /* J6 - LVDS Display contrast */ #endif @@ -208,7 +190,7 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = { MX6PAD(SD1_CMD__PWM4_PWMO), /* GPIO1[18] */ #endif /* RTC ISL1208 irq*/ - MX6PAD(NANDF_CLE__GPIO_6_7), + MX6PAD(NANDF_CLE__GPIO_6_7), /* TS_DIFF5- */ /* Apalis UART1 */ MX6PAD(CSI0_DAT10__UART1_TXD), @@ -234,33 +216,62 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = { MX6PAD(KEY_COL1__UART5_TXD), MX6PAD(KEY_ROW1__UART5_RXD), - /* Apalis, AUDMUX, local AC97 */ - MX6PAD(DISP0_DAT23__AUDMUX_AUD4_RXD), + /* Apalis, AUDMUX, local I2S */ MX6PAD(DISP0_DAT20__AUDMUX_AUD4_TXC), MX6PAD(DISP0_DAT21__AUDMUX_AUD4_TXD), MX6PAD(DISP0_DAT22__AUDMUX_AUD4_TXFS), - /* Apalis MMC1 */ - SD_PINS(1, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ), - NEW_PAD_CTRL(MX6PAD(NANDF_D0__USDHC1_DAT4), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)), - NEW_PAD_CTRL(MX6PAD(NANDF_D1__USDHC1_DAT5), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)), - NEW_PAD_CTRL(MX6PAD(NANDF_D2__USDHC1_DAT6), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)), - NEW_PAD_CTRL(MX6PAD(NANDF_D3__USDHC1_DAT7), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)), - /* Apalis SD1 */ - SD_PINS(2, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ), - /* Apalis eMMC */ - SD_PINS(3, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ), - NEW_PAD_CTRL(MX6PAD(SD3_DAT4__USDHC3_DAT4), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)), - NEW_PAD_CTRL(MX6PAD(SD3_DAT5__USDHC3_DAT5), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)), - NEW_PAD_CTRL(MX6PAD(SD3_DAT6__USDHC3_DAT6), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)), - NEW_PAD_CTRL(MX6PAD(SD3_DAT7__USDHC3_DAT7), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)), - MX6PAD(SD3_RST__USDHC3_RST), + MX6PAD(DISP0_DAT23__AUDMUX_AUD4_RXD), /* USBOTG ID pin */ MX6PAD(ENET_RX_ER__ANATOP_USBOTG_ID), + /* USBOTG USB_VBUS_DET to internal HUB pin */ + MX6PAD(EIM_D28__GPIO_3_28), + /* USB OTG OC pin */ + MX6PAD(EIM_D21__USBOH3_USBOTG_OC), + /* USBOTG Power Enable */ + MX6PAD(EIM_D22__GPIO_3_22), + /* USBH Power Enable */ + MX6PAD(GPIO_0__GPIO_1_0), /*GPIO_0__USBOH3_USBH1_PWR*/ /* USB OC pin */ - MX6PAD(EIM_D21__USBOH3_USBOTG_OC), MX6PAD(GPIO_3__USBOH3_USBH1_OC), + + /* Apalis I2C1, i.MX I2C1*/ + MX6PAD(CSI0_DAT9__I2C1_SCL), + MX6PAD(CSI0_DAT8__I2C1_SDA), + + /* Apalis I2C3 (CAM), i.MX I2C3 */ + MX6PAD(EIM_D17__I2C3_SCL), + MX6PAD(EIM_D18__I2C3_SDA), + + /* Touch Int */ + MX6PAD(KEY_COL2__GPIO_4_10), + 0 +}; + +/* Apalis I2C2 (DDC) */ +#define DDC_USE_I2C2 +static iomux_v3_cfg_t MX6NAME(hdmi_ddc_pads)[] = { +#ifdef DDC_USE_I2C2 + MX6PAD(KEY_COL3__GPIO_4_12), /* I2C2 SCL */ + MX6PAD(KEY_ROW3__GPIO_4_13), /* I2C2 SDA */ + MX6PAD(EIM_EB2__I2C2_SCL), /* HDMI DDC SCL */ + MX6PAD(EIM_D16__I2C2_SDA), /* HDMI DDC SDA */ +#else + MX6PAD(EIM_EB2__HDMI_TX_DDC_SCL), /* HDMI DDC SCL */ + MX6PAD(EIM_D16__HDMI_TX_DDC_SDA), /* HDMI DDC SDA */ +#endif + 0 +}; + +/* Apalis power I2C, i.MX I2C2*/ +static iomux_v3_cfg_t MX6NAME(i2c2_pads)[] = { +#ifdef DDC_USE_I2C2 + MX6PAD(EIM_EB2__HDMI_TX_DDC_SCL), /* HDMI DDC SCL */ + MX6PAD(EIM_D16__HDMI_TX_DDC_SDA), /* HDMI DDC SDA */ +#endif + MX6PAD(KEY_COL3__I2C2_SCL), /* I2C2 SCL */ + MX6PAD(KEY_ROW3__I2C2_SDA), /* I2C2 SDA */ 0 }; @@ -335,6 +346,7 @@ static iomux_v3_cfg_t MX6NAME(vga_dac_enable)[] = { MX6PAD(DI0_DISP_CLK__IPU1_DI0_DISP_CLK), MX6PAD(DI0_PIN2__IPU1_DI0_PIN2), /* HSync */ MX6PAD(DI0_PIN3__IPU1_DI0_PIN3), /* VSync */ + MX6PAD(DI0_PIN15__IPU1_DI0_PIN15), /* DE */ MX6PAD(DISP0_DAT0__IPU1_DISP0_DAT_0), MX6PAD(DISP0_DAT1__IPU1_DISP0_DAT_1), MX6PAD(DISP0_DAT2__IPU1_DISP0_DAT_2), @@ -356,6 +368,7 @@ static iomux_v3_cfg_t MX6NAME(vga_dac_enable)[] = { MX6PAD(DI0_DISP_CLK__IPU2_DI0_DISP_CLK), MX6PAD(DI0_PIN2__IPU2_DI0_PIN2), /* HSync */ MX6PAD(DI0_PIN3__IPU2_DI0_PIN3), /* VSync */ + MX6PAD(DI0_PIN15__IPU2_DI0_PIN15), /* DE */ MX6PAD(DISP0_DAT0__IPU2_DISP0_DAT_0), MX6PAD(DISP0_DAT1__IPU2_DISP0_DAT_1), MX6PAD(DISP0_DAT2__IPU2_DISP0_DAT_2), @@ -380,6 +393,7 @@ static iomux_v3_cfg_t MX6NAME(vga_dac_disable)[] = { MX6PAD(DI0_DISP_CLK__GPIO_4_16), MX6PAD(DI0_PIN2__GPIO_4_18), /* HSync */ MX6PAD(DI0_PIN3__GPIO_4_19), /* VSync */ + MX6PAD(DI0_PIN15__GPIO_4_17), /* DE */ MX6PAD(DISP0_DAT0__GPIO_4_21), MX6PAD(DISP0_DAT1__GPIO_4_22), MX6PAD(DISP0_DAT2__GPIO_4_23), @@ -436,29 +450,97 @@ static iomux_v3_cfg_t MX6NAME(csi0_sensor_pads)[] = { }; #endif -static iomux_v3_cfg_t MX6NAME(hdmi_ddc_pads)[] = { - MX6PAD(KEY_COL3__HDMI_TX_DDC_SCL), /* HDMI DDC SCL */ - MX6PAD(KEY_ROW3__HDMI_TX_DDC_SDA), /* HDMI DDC SDA */ - 0 -}; -/* TODO fix that i2c mess */ -static iomux_v3_cfg_t MX6NAME(i2c2_pads)[] = { -#ifdef TODO - MX6PAD(KEY_COL3__I2C2_SCL), /* I2C2 SCL */ - MX6PAD(KEY_ROW3__I2C2_SDA), /* I2C2 SDA */ -#endif - 0 -}; - #ifdef TODO static iomux_v3_cfg_t MX6NAME(mc33902_flexcan_pads)[] = { NEW_PAD_CTRL(MX6PAD(GPIO_7__GPIO_1_7), CAN1_ERR_PADCFG), 0 }; #endif + +/* MMC / SD Cards */ +#define MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6Q_USDHC_PAD_CTRL_50MHZ MX6Q_USDHC_PAD_CTRL +#define MX6Q_PAD_SD3_CLK__USDHC3_CLK MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ +#define MX6Q_PAD_SD3_CMD__USDHC3_CMD MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ +#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ +#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ +#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ +#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ +#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ +#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ +#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ +#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ +#define MX6Q_PAD_SD4_CLK__USDHC4_CLK MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ +#define MX6Q_PAD_SD4_CMD__USDHC4_CMD MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ +#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ +#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ +#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ +#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ + +#define MX6DL_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ +#define MX6DL_USDHC_PAD_CTRL_50MHZ MX6DL_USDHC_PAD_CTRL +#define MX6DL_PAD_SD3_CLK__USDHC3_CLK MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ +#define MX6DL_PAD_SD3_CMD__USDHC3_CMD MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ +#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ +#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ +#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ +#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ +#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4 MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ +#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5 MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ +#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6 MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ +#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7 MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ +#define MX6DL_PAD_SD4_CLK__USDHC4_CLK MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ +#define MX6DL_PAD_SD4_CMD__USDHC4_CMD MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ +#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ +#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ +#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ +#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ + +#define NP(id, pin, pad_ctl) \ + NEW_PAD_CTRL(MX6PAD(SD##id##_##pin##__USDHC##id##_##pin), MX6(pad_ctl)) + +#define SD_PINS(id, pad_ctl) \ + NP(id, CLK, pad_ctl), \ + NP(id, CMD, pad_ctl), \ + NP(id, DAT0, pad_ctl), \ + NP(id, DAT1, pad_ctl), \ + NP(id, DAT2, pad_ctl), \ + NP(id, DAT3, pad_ctl) + +/* Apalis MMC1 */ +#define SD_PINS1(pad_ctl) \ + SD_PINS(1, pad_ctl), \ + NEW_PAD_CTRL(MX6PAD(NANDF_D0__USDHC1_DAT4), MX6(pad_ctl)), \ + NEW_PAD_CTRL(MX6PAD(NANDF_D1__USDHC1_DAT5), MX6(pad_ctl)), \ + NEW_PAD_CTRL(MX6PAD(NANDF_D2__USDHC1_DAT6), MX6(pad_ctl)), \ + NEW_PAD_CTRL(MX6PAD(NANDF_D3__USDHC1_DAT7), MX6(pad_ctl)) + +/* Apalis SD1 */ +#define SD_PINS2(pad_ctl) \ + SD_PINS(2, pad_ctl) + +/* Apalis eMMC */ +#define SD_PINS3(pad_ctl) \ + SD_PINS(3, pad_ctl), \ + NEW_PAD_CTRL(MX6PAD(SD3_DAT4__USDHC3_DAT4), MX6(pad_ctl)), \ + NEW_PAD_CTRL(MX6PAD(SD3_DAT5__USDHC3_DAT5), MX6(pad_ctl)), \ + NEW_PAD_CTRL(MX6PAD(SD3_DAT6__USDHC3_DAT6), MX6(pad_ctl)), \ + NEW_PAD_CTRL(MX6PAD(SD3_DAT7__USDHC3_DAT7), MX6(pad_ctl)), \ + MX6PAD(SD3_RST__USDHC3_RST) + +/* not in default pinmuxing, pins partly used for UART2 & PWM */ +#define SD_PINS4(pad_ctl) \ + SD_PINS(4, pad_ctl) + #define MX6_USDHC_PAD_SETTING(id, speed, pad_ctl) \ - MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS(id, pad_ctl), 0 } + MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS##id(pad_ctl), 0 } +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(1, 50, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ); +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(1, 100, USDHC_PAD_CTRL_100MHZ); +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(1, 200, USDHC_PAD_CTRL_200MHZ); static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 50, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ); static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 100, USDHC_PAD_CTRL_100MHZ); static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 200, USDHC_PAD_CTRL_200MHZ); @@ -475,6 +557,9 @@ static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 200, USDHC_PAD_CTRL_200MHZ); #define SD_SPEED_CNT 3 static iomux_v3_cfg_t * MX6NAME(sd_pads)[] = { + MX6NAME(sd1_50mhz), + MX6NAME(sd1_100mhz), + MX6NAME(sd1_200mhz), MX6NAME(sd2_50mhz), MX6NAME(sd2_100mhz), MX6NAME(sd2_200mhz), |