diff options
| author | Oleksandr Suvorov <oleksandr.suvorov@toradex.com> | 2020-07-06 20:17:30 +0300 |
|---|---|---|
| committer | Oleksandr Suvorov <oleksandr.suvorov@toradex.com> | 2020-07-06 20:24:05 +0300 |
| commit | d6e1cff14875d6ce338c1f27afe0639ef0f97b79 (patch) | |
| tree | 2449859b19a9e58abb0414700621a86f234d91d6 /arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts | |
| parent | 453fdfde79e13e27030a56c7ea787e98698b0dba (diff) | |
| parent | 0347fe7527d062e1762498cb5863bcd5bde0997b (diff) | |
Merge branch 'imx_4.14.98_2.3.0' into toradex_4.14-2.3.x-imx
Fix conflicts after merging changes from the latest NXP branch.
Conflicts:
arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
drivers/pci/dwc/pci-imx6.c
Related-to: ELB-1306
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts new file mode 100644 index 000000000000..6bac94c0b44c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP + */ + + +#include "fsl-imx8qm-mek.dts" + +/* + * Add the PCIeA x2 lanes and PCIeB x1 lane usecase + * hsio-cfg = <PCIEAX2PCIEBX1> + * NOTE: In this case, the HSIO nodes contained + * hsio-cfg = <PCIEAX1PCIEBX1SATA> would be re-configured. + */ +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + num-lanes = <2>; + clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", + "pcie_inbound_axi", "phy_per", "misc_per"; + hsio-cfg = <PCIEAX2PCIEBX1>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PCLK>, + <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pciex2_per", + "pcie_inbound_axi", "phy_per", "misc_per"; + power-domains = <&pd_pcie1>; + hsio-cfg = <PCIEAX2PCIEBX1>; + status = "okay"; +}; + +&sata { + status = "disabled"; +}; + |