diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-03-19 10:53:42 +0100 |
|---|---|---|
| committer | Philippe Schenker <philippe.schenker@toradex.com> | 2019-05-09 11:13:53 +0200 |
| commit | 1be6df67b7640612d21778d491426668953aad87 (patch) | |
| tree | 839fa76b81ef127fe76e6d31cb6a48ddd110d25e | |
| parent | f33f592f77af45f594804958777b068486e21683 (diff) | |
Revert "MLK-14498-2 ARM: imx7d: clk: select uart clock parent and rate"
This seems to limit possible baud rates due to lower input clock.
Since Toradex modules do not use UART5/6 as console, do not set
clock explicitly.
This reverts commit 4f447cb8bccb1d40973e46478d7b11aa61961c90.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| -rw-r--r-- | drivers/clk/imx/clk-imx7d.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 041d7b54f0e2..226289737ce2 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -921,11 +921,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) /* set parent of SIM1 root clock */ imx_clk_set_parent(clks[IMX7D_SIM1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_120M_CLK]); - imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_rate(clks[IMX7D_UART5_ROOT_DIV], 80000000); - imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_rate(clks[IMX7D_UART6_ROOT_DIV], 80000000); - imx_register_uart_clocks(uart_clks); } CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); |