diff options
| author | Bai Ping <b51503@freescale.com> | 2014-12-21 01:42:36 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2015-02-02 14:47:21 +0800 |
| commit | f083680940eb04fedb2ead47aa7547fcecf91e23 (patch) | |
| tree | 430b13863be925f9493c8f9d84dd50f6467a1201 | |
| parent | 245bf82e27c46db4f25e58634860f407b4c05309 (diff) | |
MLK-10044 arm: imx: Fix the pll2_bus clk tree mismatch for i.MX6SL
In busfreq code, when switching between different busfreq mode,
the PLL2_BUS clk rate will be changed in asm code. But the kernel clock
tree is NOT aware of this change, so the clk tree information is NOT
updated timely. We must explicitly call imx_clk_set_rate() to update the
PLL2_BUS clk tree infomation.
Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit a8cf0e4633ee897b7efff715f889026262f7a027)
| -rw-r--r-- | arch/arm/mach-imx/busfreq-imx6.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/busfreq-imx6.c b/arch/arm/mach-imx/busfreq-imx6.c index 9a8fcc53a5b2..6b695e60f561 100644 --- a/arch/arm/mach-imx/busfreq-imx6.c +++ b/arch/arm/mach-imx/busfreq-imx6.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -245,6 +245,7 @@ static void enter_lpm_imx6sl(void) update_lpddr2_freq(LPDDR2_AUDIO_CLK); /* Fix the clock tree in kernel */ + imx_clk_set_rate(pll2, pll2_org_rate); imx_clk_set_parent(periph2_pre_clk, pll2_200); imx_clk_set_parent(periph2_clk, periph2_pre_clk); @@ -326,6 +327,7 @@ static void enter_lpm_imx6sl(void) * Make sure PLL2 rate is updated as it gets * bypassed in the DDR freq change code. */ + imx_clk_set_rate(pll2, LPAPM_CLK); imx_clk_set_parent(periph2_clk2_sel, pll2); imx_clk_set_parent(periph2_clk, periph2_clk2); @@ -352,6 +354,7 @@ static void exit_lpm_imx6sl(void) * Make sure PLL2 rate is updated as it gets * un-bypassed in the DDR freq change code. */ + imx_clk_set_rate(pll2, pll2_org_rate); imx_clk_set_parent(periph2_pre_clk, pll2_400); imx_clk_set_parent(periph2_clk, periph2_pre_clk); |