diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-09-02 12:18:42 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-09-02 12:22:14 -0500 |
| commit | 0cefa4127a81cf1ba6ac867e49357e818635c2e6 (patch) | |
| tree | 1fd7528b32090b704d3573b9063189ef0540733d | |
| parent | ebd65cca09664befcc5bb462b0b566c27225abe3 (diff) | |
ENGR00155958: MX6: Fix bug in setting parent of periph_clk
periph_clk mux should be set only after the periph_clk2 mux is set.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index cfc5f1bb5fe3..5328e60824c0 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -937,7 +937,7 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent) reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; __raw_writel(reg, MXC_CCM_CBCMR); - /* Set the periph_clk_sel multiplexer. */ + /* Set the periph_clk_sel multiplexer. */ reg = __raw_readl(MXC_CCM_CBCDR); reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; __raw_writel(reg, MXC_CCM_CBCDR); @@ -945,9 +945,6 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent) reg = __raw_readl(MXC_CCM_CBCDR); /* Set the periph_clk2_podf divider to divide by 1. */ reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK; - /* Clear periph_clk_sel to select periph_clk2. */ - reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; - __raw_writel(reg, MXC_CCM_CBCDR); /* Set the periph_clk2_sel mux. */ @@ -955,11 +952,16 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent) reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK; reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET); __raw_writel(reg, MXC_CCM_CBCMR); + + reg = __raw_readl(MXC_CCM_CBCDR); + /* Set periph_clk_sel to select periph_clk2. */ + reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; + __raw_writel(reg, MXC_CCM_CBCDR); } if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY)) - panic("pll _clk_axi_a_set_rate failed\n"); + panic("_clk_periph_set_parent failed\n"); return 0; } |