diff options
| author | Anson Huang <b20788@freescale.com> | 2011-04-21 10:11:17 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2011-04-21 10:11:17 +0800 |
| commit | 3c07d833ef6a12dc81de5b878131b3ba862b946c (patch) | |
| tree | b6dba92137c2facdef9c38bcaaee5c277bb62d38 | |
| parent | b826b22de74538f06e2b23c698eee56e71f0e0d2 (diff) | |
ENGR00142411-2 [MX50]Fix minor bug of regulator
fix regulator minor bug.
Signed-off-by: Anson Huang <b20788@freescale.com>
| -rw-r--r-- | drivers/regulator/reg-mc34708.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/regulator/reg-mc34708.c b/drivers/regulator/reg-mc34708.c index 64e4abd405f0..b0fa3813f538 100644 --- a/drivers/regulator/reg-mc34708.c +++ b/drivers/regulator/reg-mc34708.c @@ -691,7 +691,7 @@ static int mc34708_sw_set_normal_voltage(struct regulator_dev *reg, int minuV, switch (id) { case MC34708_SW1A: voltage = - uv_to_bit_value(mV * 1000, SW1_MIN_UV, SW1_MAX_UV, + uv_to_bit_value(mV * 1000, SW1_MIN_UV, SW1_MAX_UV, SW1_STEP_UV); register_val = BITFVAL(SW1A, voltage); register_mask = BITFMASK(SW1A); @@ -699,7 +699,7 @@ static int mc34708_sw_set_normal_voltage(struct regulator_dev *reg, int minuV, break; case MC34708_SW1B: voltage = - uv_to_bit_value(mV * 1000, SW1_MIN_UV, SW1_MAX_UV, + uv_to_bit_value(mV * 1000, SW1_MIN_UV, SW1_MAX_UV, SW1_STEP_UV); register_val = BITFVAL(SW1B, voltage); register_mask = BITFMASK(SW1B); @@ -707,14 +707,16 @@ static int mc34708_sw_set_normal_voltage(struct regulator_dev *reg, int minuV, break; case MC34708_SW2: voltage = - uv_to_bit_value(mV, SW2_MIN_UV, SW2_MAX_UV, SW2_STEP_UV); + uv_to_bit_value(mV * 1000, SW2_MIN_UV, SW2_MAX_UV, + SW2_STEP_UV); register_val = BITFVAL(SW2, voltage); register_mask = BITFMASK(SW2); register1 = MC34708_REG_SW2_3; break; case MC34708_SW3: voltage = - mv_to_bit_value(mV, SW3_MIN_MV, SW3_MAX_MV, SW3_STEP_MV); + mv_to_bit_value(mV, SW3_MIN_MV, SW3_MAX_MV, + SW3_STEP_MV); register_val = BITFVAL(SW3, voltage); register_mask = BITFMASK(SW3); register1 = MC34708_REG_SW2_3; |