/* * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include #include #include #include #include "qemu_private.h" /* * The next 3 constants identify the extents of the code, RO data region and the * limit of the BL3-1 image. These addresses are used by the MMU setup code and * therefore they must be page-aligned. It is the responsibility of the linker * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols * refer to page-aligned addresses. */ #define BL31_RO_BASE (unsigned long)(&__RO_START__) #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) #define BL31_END (unsigned long)(&__BL31_END__) /* * Placeholder variables for copying the arguments that have been passed to * BL3-1 from BL2. */ static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; /******************************************************************************* * Perform any BL3-1 early platform setup. Here is an opportunity to copy * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before * they are lost (potentially). This needs to be done before the MMU is * initialized so that the memory layout can be used while creating page * tables. BL2 has flushed this information to memory, so we are guaranteed * to pick up good data. ******************************************************************************/ void bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { /* Initialize the console to provide early debug support */ console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, PLAT_QEMU_CONSOLE_BAUDRATE); /* * Check params passed from BL2 should not be NULL, */ assert(from_bl2 != NULL); assert(from_bl2->h.type == PARAM_BL31); assert(from_bl2->h.version >= VERSION_1); /* * In debug builds, we pass a special value in 'plat_params_from_bl2' * to verify platform parameters from BL2 to BL3-1. * In release builds, it's not used. */ assert(((unsigned long long)plat_params_from_bl2) == QEMU_BL31_PLAT_PARAM_VAL); /* * Copy BL3-2 (if populated by BL2) and BL3-3 entry point information. * They are stored in Secure RAM, in BL2's address space. */ if (from_bl2->bl32_ep_info) bl32_image_ep_info = *from_bl2->bl32_ep_info; bl33_image_ep_info = *from_bl2->bl33_ep_info; } void bl31_plat_arch_setup(void) { qemu_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE), BL31_RO_BASE, BL31_RO_LIMIT, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); } static const unsigned int irq_sec_array[] = { QEMU_IRQ_SEC_SGI_0, QEMU_IRQ_SEC_SGI_1, QEMU_IRQ_SEC_SGI_2, QEMU_IRQ_SEC_SGI_3, QEMU_IRQ_SEC_SGI_4, QEMU_IRQ_SEC_SGI_5, QEMU_IRQ_SEC_SGI_6, QEMU_IRQ_SEC_SGI_7, }; static const struct gicv2_driver_data plat_gicv2_driver_data = { .gicd_base = GICD_BASE, .gicc_base = GICC_BASE, .g0_interrupt_num = ARRAY_SIZE(irq_sec_array), .g0_interrupt_array = irq_sec_array, }; void bl31_platform_setup(void) { /* Initialize the gic cpu and distributor interfaces */ gicv2_driver_init(&plat_gicv2_driver_data); gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); } unsigned int plat_get_syscnt_freq2(void) { return SYS_COUNTER_FREQ_IN_TICKS; } /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image * for the security state specified. BL3-3 corresponds to the non-secure * image type while BL3-2 corresponds to the secure image type. A NULL * pointer is returned if the image does not exist. ******************************************************************************/ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) { entry_point_info_t *next_image_info; assert(sec_state_is_valid(type)); next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info : &bl32_image_ep_info; /* * None of the images on the ARM development platforms can have 0x0 * as the entrypoint */ if (next_image_info->pc) return next_image_info; else return NULL; }