From 5c5a05fd7eb5a008710b2f1db9b63361674b9de9 Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Tue, 6 Jun 2017 15:44:46 -0500 Subject: Fix the pinmux to use correct resource ID for iMX8QM/QX Signed-off-by: Nitin Garg --- plat/imx/imx8qxp/imx8qxp_bl31_setup.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'plat/imx/imx8qxp/imx8qxp_bl31_setup.c') diff --git a/plat/imx/imx8qxp/imx8qxp_bl31_setup.c b/plat/imx/imx8qxp/imx8qxp_bl31_setup.c index 6293d7c2..6737612b 100644 --- a/plat/imx/imx8qxp/imx8qxp_bl31_setup.c +++ b/plat/imx/imx8qxp/imx8qxp_bl31_setup.c @@ -45,6 +45,8 @@ #include #include #include +#include +#include /* linker defined symbols */ #if USE_COHERENT_MEM @@ -228,12 +230,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, while (1); } #if DEBUG_CONSOLE_A35 - /* This maybe updated, need to check SCFW */ - #define SC_P_UART0_RX 30 - #define SC_P_UART0_TX 31 - #define SC_P_UART0_RTS_B 32 - #define SC_P_UART0_CTS_B 33 - /* Power up UART0 */ sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON); @@ -244,14 +240,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, /* Enable UART0 clock root */ sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false); +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT)) /* Configure UART pads */ - sc_pad_set(ipc_handle, SC_P_UART0_RX, 0xc600004c); - - sc_pad_set(ipc_handle, SC_P_UART0_TX, 0xc600004c); - - sc_pad_set(ipc_handle, SC_P_UART0_RTS_B, 0xc600004c); + sc_pad_set(ipc_handle, SC_P_UART0_RX, UART_PAD_CTRL); - sc_pad_set(ipc_handle, SC_P_UART0_CTS_B, 0xc600004c); + sc_pad_set(ipc_handle, SC_P_UART0_TX, UART_PAD_CTRL); lpuart32_serial_init(IMX_BOOT_UART_BASE); #endif -- cgit v1.2.3