From 2edc73640ce2b5b932888c35c44c78ad21940445 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 14 Mar 2017 05:59:28 +0800 Subject: Add i.MX8QXP support Add i.MX8QXP platform support. Signed-off-by: Anson Huang Signed-off-by: Bai Ping Signed-off-by: Peng Fan --- plat/imx/imx8qxp/imx8qxp_bl31_setup.c | 288 ++++++++++++++++++++++++++++++++++ 1 file changed, 288 insertions(+) create mode 100644 plat/imx/imx8qxp/imx8qxp_bl31_setup.c (limited to 'plat/imx/imx8qxp/imx8qxp_bl31_setup.c') diff --git a/plat/imx/imx8qxp/imx8qxp_bl31_setup.c b/plat/imx/imx8qxp/imx8qxp_bl31_setup.c new file mode 100644 index 00000000..e82e0124 --- /dev/null +++ b/plat/imx/imx8qxp/imx8qxp_bl31_setup.c @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* linker defined symbols */ +#if USE_COHERENT_MEM +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + +sc_ipc_t ipc_handle; + +#define BL31_RO_BASE (unsigned long)(&__RO_START__) +#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL31_END (unsigned long)(&__BL31_END__) + +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/* get SPSR for BL33 entry */ +static uint32_t get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned long mode; + uint32_t spsr; + + /* figure out what mode we enter the non-secure world */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} + +#if DEBUG_CONSOLE_A35 +/* + * Note: + * This piece code is from uboot, take care of license issue. + */ +static void lpuart32_serial_setbrg(unsigned int base, int baudrate) +{ + unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; + unsigned int clk; + sc_pm_clock_rate_t rate; + + sc_pm_get_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); + + clk = (unsigned int)rate; + + baud_diff = baudrate; + osr = 0; + sbr = 0; + for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) + { + tmp_sbr = (clk / (baudrate * tmp_osr)); + if (tmp_sbr == 0) + tmp_sbr = 1; + + /*calculate difference in actual buad w/ current values */ + tmp_diff = ( clk / (tmp_osr * tmp_sbr)); + tmp_diff = tmp_diff - baudrate; + + /* select best values between sbr and sbr+1 */ + if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) { + tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1))); + tmp_sbr++; + } + + if (tmp_diff <= baud_diff) { + baud_diff = tmp_diff; + osr = tmp_osr; + sbr = tmp_sbr; + } + } + + /*TODO handle buadrate outside acceptable rate + * if (baudDiff > ((config->baudRate_Bps / 100) * 3)) + * { + * Unacceptable baud rate difference of more than 3% + * return kStatus_LPUART_BaudrateNotSupport; + * } + */ + tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD); + + if ((osr >3) && (osr < 8)) + tmp |= LPUART_BAUD_BOTHEDGE_MASK; + + tmp &= ~LPUART_BAUD_OSR_MASK; + tmp |= LPUART_BAUD_OSR(osr-1); + tmp &= ~LPUART_BAUD_SBR_MASK; + tmp |= LPUART_BAUD_SBR(sbr); + + /* explicitly disable 10 bit mode & set 1 stop bit */ + tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); + + mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp); +} + +static int lpuart32_serial_init(unsigned int base) +{ + unsigned int tmp; + + /*disable TX & RX before enabling clocks */ + tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); + tmp &= ~(CTRL_TE | CTRL_RE); + mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); + + mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0); + mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE)); + + mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0); + + /* + * provide data bits, parity, stop bit, etc + */ + lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE); + + /* eight data bits no parity bit */ + tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); + tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); + mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); + + mmio_write_32(IMX_BOOT_UART_BASE + CTRL , CTRL_RE | CTRL_TE); + + mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); + mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); + mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A); + + return 0; +} +#endif + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + /* open the IPC channel */ + if (sc_ipc_open(&ipc_handle, SC_IPC_CH) != SC_ERR_NONE) { + /* No console available now */ + while (1); + } +#if DEBUG_CONSOLE_A35 + /* This maybe updated, need to check SCFW */ + #define SC_P_UART0_RX 30 + #define SC_P_UART0_TX 31 + #define SC_P_UART0_RTS_B 32 + #define SC_P_UART0_CTS_B 33 + + /* Power up UART0 */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON); + + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + sc_pm_set_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); + + /* Enable UART0 clock root */ + sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false); + + /* Configure UART pads */ + sc_pad_set(ipc_handle, SC_P_UART0_RX, 0xc600004c); + + sc_pad_set(ipc_handle, SC_P_UART0_TX, 0xc600004c); + + sc_pad_set(ipc_handle, SC_P_UART0_RTS_B, 0xc600004c); + + sc_pad_set(ipc_handle, SC_P_UART0_CTS_B, 0xc600004c); + + lpuart32_serial_init(IMX_BOOT_UART_BASE); +#endif + +#if DEBUG_CONSOLE + console_init(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, + IMX_CONSOLE_BAUDRATE); +#endif + + /* + * tell BL3-1 where the non-secure software image is located + * and the entry state information. + */ + bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; + bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +} + +void bl31_plat_arch_setup(void) +{ + /* + * add the mmap + * Change to 128KB? + * Fix Me + */ + mmap_add_region(BL31_BASE, BL31_BASE, 0x10000, + MT_MEMORY | MT_RW); + mmap_add_region(BL31_BASE, BL31_BASE, BL31_RO_LIMIT - BL31_RO_BASE, + MT_MEMORY | MT_RO); + mmap_add_region(IMX_BOOT_UART_BASE, IMX_BOOT_UART_BASE, + 0x1000, MT_DEVICE | MT_RW); + mmap_add_region(0x5d1b0000, 0x5d1b0000, 0x10000, + MT_DEVICE | MT_RW); + mmap_add_region(PLAT_GICD_BASE, PLAT_GICD_BASE, 0x10000, + MT_DEVICE | MT_RW); + mmap_add_region(PLAT_GICR_BASE, PLAT_GICR_BASE, 0xc0000, + MT_DEVICE | MT_RW); +// mmap_add_region(IMX_GPT0_BASE, IMX_GPT0_BASE, 0x10000, +// MT_DEVICE | MT_RW); +#if USE_COHERENT_MEM + mmap_add_region(BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE, + MT_DEVICE | MT_RW); +#endif + + /* setup xlat table */ + init_xlat_tables(); + + /* enable the MMU */ + enable_mmu_el3(0); +} + +void bl31_platform_setup(void) +{ + /* init the GICv3 cpu and distributor interface */ + plat_gic_driver_init(); + plat_gic_init(); +} + +entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) +{ + if (type == NON_SECURE) + return &bl33_image_ep_info; + if (type == SECURE) + return &bl32_image_ep_info; + + return NULL; +} + +unsigned long long plat_get_syscnt_freq(void) +{ + return COUNTER_FREQUENCY; +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return COUNTER_FREQUENCY; +} -- cgit v1.2.3