From 8b2305c1464839bdf2683f8ece9482c52cd30720 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Sun, 10 Jun 2018 20:22:45 +0800 Subject: plat: imx8m: add a common dram PM code for imx8m soc re-design the dram power management code to make it more common for all i.MX8M SOCs. code need to refact and optimize to make more better. Using this common code on i.MX8MM first, for i.MX8MQ, will move to this later. Signed-off-by: Bai Ping --- plat/imx/imx8mm/imx8mm_bl31_setup.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'plat/imx/imx8mm/imx8mm_bl31_setup.c') diff --git a/plat/imx/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8mm/imx8mm_bl31_setup.c index b4ebb60d..036a83d7 100644 --- a/plat/imx/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8mm/imx8mm_bl31_setup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -258,6 +259,9 @@ void bl31_plat_arch_setup(void) /* map GIC */ mmap_add_region(PLAT_GIC_BASE, PLAT_GIC_BASE, 0x100000, MT_DEVICE | MT_RW); + /* Map DDRC/PHY/PERF */ + mmap_add_region(0x3c000000, 0x3c000000, 0xC000000, MT_DEVICE | MT_RW); + #if USE_COHERENT_MEM mmap_add_region(BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE, @@ -275,12 +279,16 @@ void bl31_platform_setup(void) /* select the CKIL source to 32K OSC */ mmio_write_32(0x30360124, 0x1); + /* init the dram info */ + dram_info_init(); + /* init the GICv3 cpu and distributor interface */ plat_gic_driver_init(); plat_gic_init(); /* gpc init */ imx_gpc_init(); + } entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) -- cgit v1.2.3