From f683b0a998ac870a1972591356842e6e5c458bf6 Mon Sep 17 00:00:00 2001
From: Jacky Bai <ping.bai@nxp.com>
Date: Fri, 25 Sep 2020 10:36:49 +0800
Subject: MLK-24914-02 plat: imx8mp:  Remove the wait mode workaround used on
 A0

The i.MX8MP A0 silicon will not be supported anymore, remove the
wait mode workaround to make the cpuidle support more robust & simplify
the code logic.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
---
 plat/imx/imx8m/imx8mp/imx8mp_psci.c | 89 -------------------------------------
 1 file changed, 89 deletions(-)

(limited to 'plat/imx/imx8m/imx8mp/imx8mp_psci.c')

diff --git a/plat/imx/imx8m/imx8mp/imx8mp_psci.c b/plat/imx/imx8m/imx8mp/imx8mp_psci.c
index 2aa34e64..f541fc13 100644
--- a/plat/imx/imx8m/imx8mp/imx8mp_psci.c
+++ b/plat/imx/imx8m/imx8mp/imx8mp_psci.c
@@ -9,102 +9,13 @@
 #include <arch.h>
 #include <arch_helpers.h>
 #include <common/debug.h>
-#include <drivers/delay_timer.h>
 #include <lib/mmio.h>
 #include <lib/psci/psci.h>
 
-#include <dram.h>
 #include <gpc.h>
 #include <imx8m_psci.h>
 #include <plat_imx8.h>
 
-void imx_pwr_domain_off(const psci_power_state_t *target_state)
-{
-	uint64_t mpidr = read_mpidr_el1();
-	unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
-
-	plat_gic_cpuif_disable();
-	imx_set_cpu_pwr_off(core_id);
-
-	/* TODO: Find out why this is still
-	 * needed in order not to break suspend */
-	udelay(50);
-}
-
-void imx_domain_suspend(const psci_power_state_t *target_state)
-{
-	uint64_t base_addr = BL31_BASE;
-	uint64_t mpidr = read_mpidr_el1();
-	unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
-
-	if (is_local_state_off(CORE_PWR_STATE(target_state))) {
-		plat_gic_cpuif_disable();
-		imx_set_cpu_secure_entry(core_id, base_addr);
-		imx_set_cpu_lpm(core_id, true);
-	} else {
-		dsb();
-		write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
-		isb();
-	}
-
-	if (!is_local_state_run(CLUSTER_PWR_STATE(target_state)))
-		imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state));
-
-	if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) {
-		if (!imx_m4_lpa_active()) {
-			imx_set_sys_lpm(core_id, true);
-			dram_enter_retention();
-			imx_anamix_override(true);
-			imx_noc_wrapper_pre_suspend(core_id);
-		} else {
-			/* flag 0xD means DSP LPA buffer is in OCRAM */
-			if (mmio_read_32(IMX_SRC_BASE + 0x98) == 0xD)
-				dram_enter_retention();
-			/*
-			 * when A53 don't enter DSM, only need to
-			 * set the system wakeup option.
-			 */
-			imx_set_sys_wakeup(core_id, true);
-		}
-	}
-}
-
-void imx_domain_suspend_finish(const psci_power_state_t *target_state)
-{
-	uint64_t mpidr = read_mpidr_el1();
-	unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
-
-	if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) {
-		if (!imx_m4_lpa_active()) {
-			imx_noc_wrapper_post_resume(core_id);
-			imx_anamix_override(false);
-			dram_exit_retention();
-			imx_set_sys_lpm(core_id, false);
-		} else {
-			/* flag 0xD means DSP LPA buffer is in OCRAM */
-			if (mmio_read_32(IMX_SRC_BASE + 0x98) == 0xD)
-				dram_exit_retention();
-
-			imx_set_sys_wakeup(core_id, false);
-		}
-	}
-
-	if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) {
-		imx_clear_rbc_count();
-		imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN);
-	}
-
-	if (is_local_state_off(CORE_PWR_STATE(target_state))) {
-		/* mark this core as awake by masking IRQ0 */
-		imx_gpc_set_a53_core_awake(core_id);
-		imx_set_cpu_lpm(core_id, false);
-		plat_gic_cpuif_enable();
-	} else {
-		write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT));
-		isb();
-	}
-}
-
 static const plat_psci_ops_t imx_plat_psci_ops = {
 	.pwr_domain_on = imx_pwr_domain_on,
 	.pwr_domain_on_finish = imx_pwr_domain_on_finish,
-- 
cgit v1.2.3