From 2f45f6e5ef517fe5f201bcd5046368b854442749 Mon Sep 17 00:00:00 2001
From: Nitin Garg <nitin.garg@nxp.com>
Date: Wed, 7 Jun 2017 15:47:04 -0500
Subject: Enable CPU, FP, L2 retention counters to 64 cycles

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
---
 plat/freescale/common/imx8_helpers.S | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

(limited to 'plat/freescale/common')

diff --git a/plat/freescale/common/imx8_helpers.S b/plat/freescale/common/imx8_helpers.S
index f2da325d..ecc2481e 100644
--- a/plat/freescale/common/imx8_helpers.S
+++ b/plat/freescale/common/imx8_helpers.S
@@ -31,6 +31,7 @@
 #include <asm_macros.S>
 #include <platform_def.h>
 #include <cortex_a72.h>
+#include <cortex_a35.h>
 
 	.globl	plat_is_my_cpu_primary
 	.globl	plat_my_core_pos
@@ -112,6 +113,33 @@ endfunc plat_calc_core_pos
 	 * ----------------------------------------------
 	 */
 func plat_reset_handler
+#if ENABLE_L2_DYNAMIC_RETENTION
+	/* ---------------------------
+	 * Enable processor retention
+	 * ---------------------------
+	*/
+	mrs	x0, L2ECTLR_EL1
+	mov	x1, #RETENTION_ENTRY_TICKS_64 << L2ECTLR_RET_CTRL_SHIFT
+	bic	x0, x0, #L2ECTLR_RET_CTRL_MASK
+	orr	x0, x0, x1
+	msr	L2ECTLR_EL1, x0
+	isb
+#endif
+
+#if ENABLE_CPU_DYNAMIC_RETENTION
+	mrs	x1, CORTEX_A72_ECTLR_EL1
+	mov	x2, #RETENTION_ENTRY_TICKS_64 << CPUECTLR_CPU_RET_CTRL_SHIFT
+	bic	x1, x1, #CPUECTLR_CPU_RET_CTRL_MASK
+	orr	x1, x1, x2
+	jump_if_cpu_midr CORTEX_A72_MIDR, SKIP_FP
+	mov	x2, #RETENTION_ENTRY_TICKS_64 << CPUECTLR_FPU_RET_CTRL_SHIFT
+	bic	x1, x1, #CPUECTLR_FPU_RET_CTRL_MASK
+	orr	x1, x1, x2
+SKIP_FP:
+	msr	CORTEX_A72_ECTLR_EL1, x1
+	isb
+#endif
+
 	/* enable EL2 cpuectlr RW access */
 	mov	x0, #0x73
 	msr	actlr_el3, x0
-- 
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