From b1063d955bfed46de9e1bfdf58684f2da9837dcd Mon Sep 17 00:00:00 2001 From: Antonio Nino Diaz Date: Mon, 22 Feb 2016 16:44:41 +0000 Subject: Add cache topology info to FVP DTBs From version 4.0 onwards, the ARM64 Linux kernel expects the device tree to indicate the cache hierarchy. Failing to provide this information results in the following warning message to be printed by the kernel: `Unable to detect cache hierarchy from DT for CPU x` All the FVP device trees provided in the TF source tree have been modified to add this information. Fixes ARM-software/tf-issues#325 Change-Id: I0ff888992e602b81a0fe1744a86151d625727511 --- fdts/fvp-base-gicv2-psci.dtb | Bin 10151 -> 10368 bytes fdts/fvp-base-gicv2-psci.dts | 14 +++++++++++++- fdts/fvp-base-gicv2legacy-psci.dtb | Bin 10151 -> 10368 bytes fdts/fvp-base-gicv2legacy-psci.dts | 14 +++++++++++++- fdts/fvp-base-gicv3-psci.dtb | Bin 10779 -> 10996 bytes fdts/fvp-base-gicv3-psci.dts | 14 +++++++++++++- fdts/fvp-foundation-gicv2-psci.dtb | Bin 7520 -> 7673 bytes fdts/fvp-foundation-gicv2-psci.dts | 10 +++++++++- fdts/fvp-foundation-gicv2legacy-psci.dtb | Bin 7520 -> 7673 bytes fdts/fvp-foundation-gicv2legacy-psci.dts | 10 +++++++++- fdts/fvp-foundation-gicv3-psci.dtb | Bin 8148 -> 8301 bytes fdts/fvp-foundation-gicv3-psci.dts | 10 +++++++++- 12 files changed, 66 insertions(+), 6 deletions(-) (limited to 'fdts') diff --git a/fdts/fvp-base-gicv2-psci.dtb b/fdts/fvp-base-gicv2-psci.dtb index 89318c18..245a6c33 100644 Binary files a/fdts/fvp-base-gicv2-psci.dtb and b/fdts/fvp-base-gicv2-psci.dtb differ diff --git a/fdts/fvp-base-gicv2-psci.dts b/fdts/fvp-base-gicv2-psci.dts index 1d26541c..fc343baa 100644 --- a/fdts/fvp-base-gicv2-psci.dts +++ b/fdts/fvp-base-gicv2-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -125,6 +125,7 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU1:cpu@1 { @@ -133,6 +134,7 @@ reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU2:cpu@2 { @@ -141,6 +143,7 @@ reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU3:cpu@3 { @@ -149,6 +152,7 @@ reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU4:cpu@100 { @@ -157,6 +161,7 @@ reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU5:cpu@101 { @@ -165,6 +170,7 @@ reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU6:cpu@102 { @@ -173,6 +179,7 @@ reg = <0x0 0x102>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU7:cpu@103 { @@ -181,6 +188,11 @@ reg = <0x0 0x103>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; }; }; diff --git a/fdts/fvp-base-gicv2legacy-psci.dtb b/fdts/fvp-base-gicv2legacy-psci.dtb index 0d176201..4c6f37a6 100644 Binary files a/fdts/fvp-base-gicv2legacy-psci.dtb and b/fdts/fvp-base-gicv2legacy-psci.dtb differ diff --git a/fdts/fvp-base-gicv2legacy-psci.dts b/fdts/fvp-base-gicv2legacy-psci.dts index 58d31593..5a7ce2f1 100644 --- a/fdts/fvp-base-gicv2legacy-psci.dts +++ b/fdts/fvp-base-gicv2legacy-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -125,6 +125,7 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU1:cpu@1 { @@ -133,6 +134,7 @@ reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU2:cpu@2 { @@ -141,6 +143,7 @@ reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU3:cpu@3 { @@ -149,6 +152,7 @@ reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU4:cpu@100 { @@ -157,6 +161,7 @@ reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU5:cpu@101 { @@ -165,6 +170,7 @@ reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU6:cpu@102 { @@ -173,6 +179,7 @@ reg = <0x0 0x102>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU7:cpu@103 { @@ -181,6 +188,11 @@ reg = <0x0 0x103>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; }; }; diff --git a/fdts/fvp-base-gicv3-psci.dtb b/fdts/fvp-base-gicv3-psci.dtb index f1dc75ee..0acbe17e 100644 Binary files a/fdts/fvp-base-gicv3-psci.dtb and b/fdts/fvp-base-gicv3-psci.dtb differ diff --git a/fdts/fvp-base-gicv3-psci.dts b/fdts/fvp-base-gicv3-psci.dts index da090f5c..5d54dbf3 100644 --- a/fdts/fvp-base-gicv3-psci.dts +++ b/fdts/fvp-base-gicv3-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -123,6 +123,7 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU1:cpu@1 { @@ -131,6 +132,7 @@ reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU2:cpu@2 { @@ -139,6 +141,7 @@ reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU3:cpu@3 { @@ -147,6 +150,7 @@ reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU4:cpu@100 { @@ -155,6 +159,7 @@ reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU5:cpu@101 { @@ -163,6 +168,7 @@ reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU6:cpu@102 { @@ -171,6 +177,7 @@ reg = <0x0 0x102>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU7:cpu@103 { @@ -179,6 +186,11 @@ reg = <0x0 0x103>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; }; }; diff --git a/fdts/fvp-foundation-gicv2-psci.dtb b/fdts/fvp-foundation-gicv2-psci.dtb index e4579181..5acb139a 100644 Binary files a/fdts/fvp-foundation-gicv2-psci.dtb and b/fdts/fvp-foundation-gicv2-psci.dtb differ diff --git a/fdts/fvp-foundation-gicv2-psci.dts b/fdts/fvp-foundation-gicv2-psci.dts index 5f93daa2..d5c2dfbb 100644 --- a/fdts/fvp-foundation-gicv2-psci.dts +++ b/fdts/fvp-foundation-gicv2-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -110,6 +110,7 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU1:cpu@1 { @@ -118,6 +119,7 @@ reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU2:cpu@2 { @@ -126,6 +128,7 @@ reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU3:cpu@3 { @@ -134,6 +137,11 @@ reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; }; }; diff --git a/fdts/fvp-foundation-gicv2legacy-psci.dtb b/fdts/fvp-foundation-gicv2legacy-psci.dtb index ac7555d9..efded443 100644 Binary files a/fdts/fvp-foundation-gicv2legacy-psci.dtb and b/fdts/fvp-foundation-gicv2legacy-psci.dtb differ diff --git a/fdts/fvp-foundation-gicv2legacy-psci.dts b/fdts/fvp-foundation-gicv2legacy-psci.dts index 4238b330..e6e4012f 100644 --- a/fdts/fvp-foundation-gicv2legacy-psci.dts +++ b/fdts/fvp-foundation-gicv2legacy-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -110,6 +110,7 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU1:cpu@1 { @@ -118,6 +119,7 @@ reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU2:cpu@2 { @@ -126,6 +128,7 @@ reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU3:cpu@3 { @@ -134,6 +137,11 @@ reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; }; }; diff --git a/fdts/fvp-foundation-gicv3-psci.dtb b/fdts/fvp-foundation-gicv3-psci.dtb index f3e0c5d3..44024369 100644 Binary files a/fdts/fvp-foundation-gicv3-psci.dtb and b/fdts/fvp-foundation-gicv3-psci.dtb differ diff --git a/fdts/fvp-foundation-gicv3-psci.dts b/fdts/fvp-foundation-gicv3-psci.dts index daad1fbc..45c699a6 100644 --- a/fdts/fvp-foundation-gicv3-psci.dts +++ b/fdts/fvp-foundation-gicv3-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -108,6 +108,7 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU1:cpu@1 { @@ -116,6 +117,7 @@ reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU2:cpu@2 { @@ -124,6 +126,7 @@ reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; }; CPU3:cpu@3 { @@ -132,6 +135,11 @@ reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; }; }; -- cgit v1.2.3