From 40c711a3608e5529bb212c97afc24caebc7fe2ac Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 7 Aug 2019 18:05:05 +0200 Subject: rcar_get3: drivers: ddr: Clean up common code Do minor coding style changes to the common DDR init code to make it checkpatch compliant and move macros out into rcar_def.h. Signed-off-by: Marek Vasut Change-Id: I67eadf8099e4ff8702105c9e07b13f308d9dbe3d --- drivers/staging/renesas/rcar/ddr/boot_init_dram.h | 12 +-- drivers/staging/renesas/rcar/ddr/dram_sub_func.c | 93 ++++++++++------------- drivers/staging/renesas/rcar/ddr/dram_sub_func.h | 10 +-- 3 files changed, 53 insertions(+), 62 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h b/drivers/staging/renesas/rcar/ddr/boot_init_dram.h index 4b0a9ebe..ac237b2e 100644 --- a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h +++ b/drivers/staging/renesas/rcar/ddr/boot_init_dram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,10 +9,10 @@ extern int32_t rcar_dram_init(void); -#define INITDRAM_OK (0) -#define INITDRAM_NG (0xffffffff) -#define INITDRAM_ERR_I (0xffffffff) -#define INITDRAM_ERR_O (0xfffffffe) -#define INITDRAM_ERR_T (0xfffffff0) +#define INITDRAM_OK 0 +#define INITDRAM_NG 0xffffffff +#define INITDRAM_ERR_I 0xffffffff +#define INITDRAM_ERR_O 0xfffffffe +#define INITDRAM_ERR_T 0xfffffff0 #endif /* BOOT_INIT_DRAM_H */ diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c index c6ab44ab..ab8eabbc 100644 --- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c +++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c @@ -12,38 +12,30 @@ #if RCAR_SYSTEM_SUSPEND /* Local defines */ -#define DRAM_BACKUP_GPIO_USE (0) +#define DRAM_BACKUP_GPIO_USE 0 #include "iic_dvfs.h" #if PMIC_ROHM_BD9571 -#define PMIC_SLAVE_ADDR (0x30U) -#define PMIC_BKUP_MODE_CNT (0x20U) -#define PMIC_QLLM_CNT (0x27U) -#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U)) -#define BIT_QLLM_DDR0_EN ((uint8_t)(1U << 0U)) -#define BIT_QLLM_DDR1_EN ((uint8_t)(1U << 1U)) +#define PMIC_SLAVE_ADDR 0x30U +#define PMIC_BKUP_MODE_CNT 0x20U +#define PMIC_QLLM_CNT 0x27U +#define BIT_BKUP_CTRL_OUT BIT(4) +#define BIT_QLLM_DDR0_EN BIT(0) +#define BIT_QLLM_DDR1_EN BIT(1) #endif -#define GPIO_OUTDT1 (0xE6051008U) -#define GPIO_OUTDT3 (0xE6053008U) -#define GPIO_INDT3 (0xE605300CU) -#define GPIO_OUTDT6 (0xE6055408U) +#define GPIO_BKUP_REQB_SHIFT_SALVATOR 9U /* GP1_9 (BKUP_REQB) */ +#define GPIO_BKUP_TRG_SHIFT_SALVATOR 8U /* GP1_8 (BKUP_TRG) */ +#define GPIO_BKUP_REQB_SHIFT_EBISU 14U /* GP6_14(BKUP_REQB) */ +#define GPIO_BKUP_TRG_SHIFT_EBISU 13U /* GP6_13(BKUP_TRG) */ +#define GPIO_BKUP_REQB_SHIFT_CONDOR 1U /* GP3_1 (BKUP_REQB) */ +#define GPIO_BKUP_TRG_SHIFT_CONDOR 0U /* GP3_0 (BKUP_TRG) */ -#if DRAM_BACKUP_GPIO_USE == 1 -#define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */ -#define GPIO_BKUP_REQB_SHIFT_EBISU (14U) /* GP6_14(BKUP_REQB) */ -#define GPIO_BKUP_REQB_SHIFT_CONDOR (1U) /* GP3_1 (BKUP_REQB) */ -#endif -#define GPIO_BKUP_TRG_SHIFT_SALVATOR (8U) /* GP1_8 (BKUP_TRG) */ -#define GPIO_BKUP_TRG_SHIFT_EBISU (13U) /* GP6_13(BKUP_TRG) */ -#define GPIO_BKUP_TRG_SHIFT_CONDOR (0U) /* GP3_0 (BKUP_TRG) */ - -#define DRAM_BKUP_TRG_LOOP_CNT (1000U) +#define DRAM_BKUP_TRG_LOOP_CNT 1000U #endif -void rcar_dram_get_boot_status(uint32_t * status) +void rcar_dram_get_boot_status(uint32_t *status) { #if RCAR_SYSTEM_SUSPEND - uint32_t reg_data; uint32_t product; uint32_t shift; @@ -62,11 +54,10 @@ void rcar_dram_get_boot_status(uint32_t * status) } reg_data = mmio_read_32(gpio); - if (0U != (reg_data & ((uint32_t)1U << shift))) { + if (reg_data & BIT(shift)) *status = DRAM_BOOT_STATUS_WARM; - } else { + else *status = DRAM_BOOT_STATUS_COLD; - } #else /* RCAR_SYSTEM_SUSPEND */ *status = DRAM_BOOT_STATUS_COLD; #endif /* RCAR_SYSTEM_SUSPEND */ @@ -116,55 +107,55 @@ int32_t rcar_dram_update_boot_status(uint32_t status) } if (status == DRAM_BOOT_STATUS_WARM) { -#if DRAM_BACKUP_GPIO_USE==1 - mmio_setbits_32(outd, 1U << reqb); +#if DRAM_BACKUP_GPIO_USE == 1 + mmio_setbits_32(outd, BIT(reqb)); #else #if PMIC_ROHM_BD9571 /* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */ i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR, - PMIC_BKUP_MODE_CNT, &bkup_mode_cnt); - if (0 != i2c_dvfs_ret) { + PMIC_BKUP_MODE_CNT, + &bkup_mode_cnt); + if (i2c_dvfs_ret) { ERROR("BKUP mode cnt READ ERROR.\n"); ret = DRAM_UPDATE_STATUS_ERR; } else { bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT; i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR, - PMIC_BKUP_MODE_CNT, bkup_mode_cnt); - if (0 != i2c_dvfs_ret) { - ERROR("BKUP mode cnt WRITE ERROR. " - "value = %d\n", bkup_mode_cnt); + PMIC_BKUP_MODE_CNT, + bkup_mode_cnt); + if (i2c_dvfs_ret) { + ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", + bkup_mode_cnt); ret = DRAM_UPDATE_STATUS_ERR; } } #endif /* PMIC_ROHM_BD9571 */ -#endif /* DRAM_BACKUP_GPIO_USE==1 */ +#endif /* DRAM_BACKUP_GPIO_USE == 1 */ /* Wait BKUP_TRG=Low */ loop_count = DRAM_BKUP_TRG_LOOP_CNT; - while (0U < loop_count) { + while (loop_count > 0) { reg_data = mmio_read_32(gpio); - if ((reg_data & - ((uint32_t)1U << trg)) == 0U) { + if (!(reg_data & BIT(trg))) break; - } loop_count--; } - if (0U == loop_count) { - ERROR( "\nWarm booting...\n" \ - " The potential of BKUP_TRG did not switch " \ - "to Low.\n If you expect the operation of " \ - "cold boot,\n check the board configuration" \ - " (ex, Dip-SW) and/or the H/W failure.\n"); + + if (!loop_count) { + ERROR("\nWarm booting...\n" + " The potential of BKUP_TRG did not switch to Low.\n" + " If you expect the operation of cold boot,\n" + " check the board configuration (ex, Dip-SW) and/or the H/W failure.\n"); ret = DRAM_UPDATE_STATUS_ERR; } } #if PMIC_ROHM_BD9571 - if(0 == ret) { - qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN); + if (!ret) { + qllm_cnt = BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN; i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR, - PMIC_QLLM_CNT, qllm_cnt); - if (0 != i2c_dvfs_ret) { - ERROR("QLLM cnt WRITE ERROR. " - "value = %d\n", qllm_cnt); + PMIC_QLLM_CNT, + qllm_cnt); + if (i2c_dvfs_ret) { + ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm_cnt); ret = DRAM_UPDATE_STATUS_ERR; } } diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h b/drivers/staging/renesas/rcar/ddr/dram_sub_func.h index 7e88f422..69c4d860 100644 --- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h +++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,11 +7,11 @@ #ifndef DRAM_SUB_FUNC_H #define DRAM_SUB_FUNC_H -#define DRAM_UPDATE_STATUS_ERR (-1) -#define DRAM_BOOT_STATUS_COLD (0) -#define DRAM_BOOT_STATUS_WARM (1) +#define DRAM_UPDATE_STATUS_ERR -1 +#define DRAM_BOOT_STATUS_COLD 0 +#define DRAM_BOOT_STATUS_WARM 1 int32_t rcar_dram_update_boot_status(uint32_t status); -void rcar_dram_get_boot_status(uint32_t * status); +void rcar_dram_get_boot_status(uint32_t *status); #endif /* DRAM_SUB_FUNC_H */ -- cgit v1.2.3 From f12039be9532f4ff1e9bc01feda61e9b3bb31667 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 7 Aug 2019 18:19:26 +0200 Subject: rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B The ddr_a and ddr_b register macros are the same for the most part, unify them into a single header. Signed-off-by: Marek Vasut Change-Id: I8f55d6d779837215339ac0010e8c8ab5f6748d75 --- .../renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h | 285 +--- .../staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c | 768 +++++------ .../staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c | 1385 ++++++++++---------- .../staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c | 385 +++--- .../renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h | 205 +-- drivers/staging/renesas/rcar/ddr/ddr_regs.h | 257 ++++ 6 files changed, 1529 insertions(+), 1756 deletions(-) create mode 100644 drivers/staging/renesas/rcar/ddr/ddr_regs.h (limited to 'drivers') diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h index 397bde04..0f89b435 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h @@ -5,287 +5,4 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef BOOT_INIT_DRAM_REGDEF_H_ -#define BOOT_INIT_DRAM_REGDEF_H_ - -/* DBSC registers */ -#define DBSC_DBSYSCONF0 0xE6790000U -#define DBSC_DBSYSCONF1 0xE6790004U -#define DBSC_DBPHYCONF0 0xE6790010U -#define DBSC_DBKIND 0xE6790020U -#define DBSC_DBMEMCONF00 0xE6790030U -#define DBSC_DBMEMCONF01 0xE6790034U -#define DBSC_DBMEMCONF02 0xE6790038U -#define DBSC_DBMEMCONF03 0xE679003CU -#define DBSC_DBMEMCONF10 0xE6790040U -#define DBSC_DBMEMCONF11 0xE6790044U -#define DBSC_DBMEMCONF12 0xE6790048U -#define DBSC_DBMEMCONF13 0xE679004CU -#define DBSC_DBMEMCONF20 0xE6790050U -#define DBSC_DBMEMCONF21 0xE6790054U -#define DBSC_DBMEMCONF22 0xE6790058U -#define DBSC_DBMEMCONF23 0xE679005CU -#define DBSC_DBMEMCONF30 0xE6790060U -#define DBSC_DBMEMCONF31 0xE6790064U -#define DBSC_DBMEMCONF32 0xE6790068U -#define DBSC_DBMEMCONF33 0xE679006CU -#define DBSC_DBSYSCNT0 0xE6790100U -#define DBSC_DBSVCR1 0xE6790104U -#define DBSC_DBSTATE0 0xE6790108U -#define DBSC_DBSTATE1 0xE679010CU -#define DBSC_DBINTEN 0xE6790180U -#define DBSC_DBINTSTAT0 0xE6790184U -#define DBSC_DBACEN 0xE6790200U -#define DBSC_DBRFEN 0xE6790204U -#define DBSC_DBCMD 0xE6790208U -#define DBSC_DBWAIT 0xE6790210U -#define DBSC_DBSYSCTRL0 0xE6790280U -#define DBSC_DBTR0 0xE6790300U -#define DBSC_DBTR1 0xE6790304U -#define DBSC_DBTR2 0xE6790308U -#define DBSC_DBTR3 0xE679030CU -#define DBSC_DBTR4 0xE6790310U -#define DBSC_DBTR5 0xE6790314U -#define DBSC_DBTR6 0xE6790318U -#define DBSC_DBTR7 0xE679031CU -#define DBSC_DBTR8 0xE6790320U -#define DBSC_DBTR9 0xE6790324U -#define DBSC_DBTR10 0xE6790328U -#define DBSC_DBTR11 0xE679032CU -#define DBSC_DBTR12 0xE6790330U -#define DBSC_DBTR13 0xE6790334U -#define DBSC_DBTR14 0xE6790338U -#define DBSC_DBTR15 0xE679033CU -#define DBSC_DBTR16 0xE6790340U -#define DBSC_DBTR17 0xE6790344U -#define DBSC_DBTR18 0xE6790348U -#define DBSC_DBTR19 0xE679034CU -#define DBSC_DBTR20 0xE6790350U -#define DBSC_DBTR21 0xE6790354U -#define DBSC_DBTR22 0xE6790358U -#define DBSC_DBTR23 0xE679035CU -#define DBSC_DBTR24 0xE6790360U -#define DBSC_DBTR25 0xE6790364U -#define DBSC_DBBL 0xE6790400U -#define DBSC_DBRFCNF1 0xE6790414U -#define DBSC_DBRFCNF2 0xE6790418U -#define DBSC_DBTSPCNF 0xE6790420U -#define DBSC_DBCALCNF 0xE6790424U -#define DBSC_DBRNK2 0xE6790438U -#define DBSC_DBRNK3 0xE679043CU -#define DBSC_DBRNK4 0xE6790440U -#define DBSC_DBRNK5 0xE6790444U -#define DBSC_DBPDNCNF 0xE6790450U -#define DBSC_DBODT0 0xE6790460U -#define DBSC_DBODT1 0xE6790464U -#define DBSC_DBODT2 0xE6790468U -#define DBSC_DBODT3 0xE679046CU -#define DBSC_DBODT4 0xE6790470U -#define DBSC_DBODT5 0xE6790474U -#define DBSC_DBODT6 0xE6790478U -#define DBSC_DBODT7 0xE679047CU -#define DBSC_DBADJ0 0xE6790500U -#define DBSC_DBDBICNT 0xE6790518U -#define DBSC_DBDFIPMSTRCNF 0xE6790520U -#define DBSC_DBDFIPMSTRSTAT 0xE6790524U -#define DBSC_DBDFILPCNF 0xE6790528U -#define DBSC_DBDFICUPDCNF 0xE679052CU -#define DBSC_DBDFISTAT0 0xE6790600U -#define DBSC_DBDFICNT0 0xE6790604U -#define DBSC_DBPDCNT00 0xE6790610U -#define DBSC_DBPDCNT01 0xE6790614U -#define DBSC_DBPDCNT02 0xE6790618U -#define DBSC_DBPDCNT03 0xE679061CU -#define DBSC_DBPDLK0 0xE6790620U -#define DBSC_DBPDRGA0 0xE6790624U -#define DBSC_DBPDRGD0 0xE6790628U -#define DBSC_DBPDSTAT00 0xE6790630U -#define DBSC_DBDFISTAT1 0xE6790640U -#define DBSC_DBDFICNT1 0xE6790644U -#define DBSC_DBPDCNT10 0xE6790650U -#define DBSC_DBPDCNT11 0xE6790654U -#define DBSC_DBPDCNT12 0xE6790658U -#define DBSC_DBPDCNT13 0xE679065CU -#define DBSC_DBPDLK1 0xE6790660U -#define DBSC_DBPDRGA1 0xE6790664U -#define DBSC_DBPDRGD1 0xE6790668U -#define DBSC_DBPDSTAT10 0xE6790670U -#define DBSC_DBDFISTAT2 0xE6790680U -#define DBSC_DBDFICNT2 0xE6790684U -#define DBSC_DBPDCNT20 0xE6790690U -#define DBSC_DBPDCNT21 0xE6790694U -#define DBSC_DBPDCNT22 0xE6790698U -#define DBSC_DBPDCNT23 0xE679069CU -#define DBSC_DBPDLK2 0xE67906A0U -#define DBSC_DBPDRGA2 0xE67906A4U -#define DBSC_DBPDRGD2 0xE67906A8U -#define DBSC_DBPDSTAT20 0xE67906B0U -#define DBSC_DBDFISTAT3 0xE67906C0U -#define DBSC_DBDFICNT3 0xE67906C4U -#define DBSC_DBPDCNT30 0xE67906D0U -#define DBSC_DBPDCNT31 0xE67906D4U -#define DBSC_DBPDCNT32 0xE67906D8U -#define DBSC_DBPDCNT33 0xE67906DCU -#define DBSC_DBPDLK3 0xE67906E0U -#define DBSC_DBPDRGA3 0xE67906E4U -#define DBSC_DBPDRGD3 0xE67906E8U -#define DBSC_DBPDSTAT30 0xE67906F0U -#define DBSC_DBBUS0CNF0 0xE6790800U -#define DBSC_DBBUS0CNF1 0xE6790804U -#define DBSC_DBCAM0CNF1 0xE6790904U -#define DBSC_DBCAM0CNF2 0xE6790908U -#define DBSC_DBCAM0CNF3 0xE679090CU -#define DBSC_DBCAM0CTRL0 0xE6790940U -#define DBSC_DBCAM0STAT0 0xE6790980U -#define DBSC_DBCAM1STAT0 0xE6790990U -#define DBSC_DBBCAMSWAP 0xE67909F0U -#define DBSC_DBBCAMDIS 0xE67909FCU -#define DBSC_DBSCHCNT0 0xE6791000U -#define DBSC_DBSCHCNT1 0xE6791004U -#define DBSC_DBSCHSZ0 0xE6791010U -#define DBSC_DBSCHRW0 0xE6791020U -#define DBSC_DBSCHRW1 0xE6791024U -#define DBSC_DBSCHQOS00 0xE6791030U -#define DBSC_DBSCHQOS01 0xE6791034U -#define DBSC_DBSCHQOS02 0xE6791038U -#define DBSC_DBSCHQOS03 0xE679103CU -#define DBSC_DBSCHQOS10 0xE6791040U -#define DBSC_DBSCHQOS11 0xE6791044U -#define DBSC_DBSCHQOS12 0xE6791048U -#define DBSC_DBSCHQOS13 0xE679104CU -#define DBSC_DBSCHQOS20 0xE6791050U -#define DBSC_DBSCHQOS21 0xE6791054U -#define DBSC_DBSCHQOS22 0xE6791058U -#define DBSC_DBSCHQOS23 0xE679105CU -#define DBSC_DBSCHQOS30 0xE6791060U -#define DBSC_DBSCHQOS31 0xE6791064U -#define DBSC_DBSCHQOS32 0xE6791068U -#define DBSC_DBSCHQOS33 0xE679106CU -#define DBSC_DBSCHQOS40 0xE6791070U -#define DBSC_DBSCHQOS41 0xE6791074U -#define DBSC_DBSCHQOS42 0xE6791078U -#define DBSC_DBSCHQOS43 0xE679107CU -#define DBSC_DBSCHQOS50 0xE6791080U -#define DBSC_DBSCHQOS51 0xE6791084U -#define DBSC_DBSCHQOS52 0xE6791088U -#define DBSC_DBSCHQOS53 0xE679108CU -#define DBSC_DBSCHQOS60 0xE6791090U -#define DBSC_DBSCHQOS61 0xE6791094U -#define DBSC_DBSCHQOS62 0xE6791098U -#define DBSC_DBSCHQOS63 0xE679109CU -#define DBSC_DBSCHQOS70 0xE67910A0U -#define DBSC_DBSCHQOS71 0xE67910A4U -#define DBSC_DBSCHQOS72 0xE67910A8U -#define DBSC_DBSCHQOS73 0xE67910ACU -#define DBSC_DBSCHQOS80 0xE67910B0U -#define DBSC_DBSCHQOS81 0xE67910B4U -#define DBSC_DBSCHQOS82 0xE67910B8U -#define DBSC_DBSCHQOS83 0xE67910BCU -#define DBSC_DBSCHQOS90 0xE67910C0U -#define DBSC_DBSCHQOS91 0xE67910C4U -#define DBSC_DBSCHQOS92 0xE67910C8U -#define DBSC_DBSCHQOS93 0xE67910CCU -#define DBSC_DBSCHQOS100 0xE67910D0U -#define DBSC_DBSCHQOS101 0xE67910D4U -#define DBSC_DBSCHQOS102 0xE67910D8U -#define DBSC_DBSCHQOS103 0xE67910DCU -#define DBSC_DBSCHQOS110 0xE67910E0U -#define DBSC_DBSCHQOS111 0xE67910E4U -#define DBSC_DBSCHQOS112 0xE67910E8U -#define DBSC_DBSCHQOS113 0xE67910ECU -#define DBSC_DBSCHQOS120 0xE67910F0U -#define DBSC_DBSCHQOS121 0xE67910F4U -#define DBSC_DBSCHQOS122 0xE67910F8U -#define DBSC_DBSCHQOS123 0xE67910FCU -#define DBSC_DBSCHQOS130 0xE6791100U -#define DBSC_DBSCHQOS131 0xE6791104U -#define DBSC_DBSCHQOS132 0xE6791108U -#define DBSC_DBSCHQOS133 0xE679110CU -#define DBSC_DBSCHQOS140 0xE6791110U -#define DBSC_DBSCHQOS141 0xE6791114U -#define DBSC_DBSCHQOS142 0xE6791118U -#define DBSC_DBSCHQOS143 0xE679111CU -#define DBSC_DBSCHQOS150 0xE6791120U -#define DBSC_DBSCHQOS151 0xE6791124U -#define DBSC_DBSCHQOS152 0xE6791128U -#define DBSC_DBSCHQOS153 0xE679112CU -#define DBSC_SCFCTST0 0xE6791700U -#define DBSC_SCFCTST1 0xE6791708U -#define DBSC_SCFCTST2 0xE679170CU -#define DBSC_DBMRRDR0 0xE6791800U -#define DBSC_DBMRRDR1 0xE6791804U -#define DBSC_DBMRRDR2 0xE6791808U -#define DBSC_DBMRRDR3 0xE679180CU -#define DBSC_DBMRRDR4 0xE6791810U -#define DBSC_DBMRRDR5 0xE6791814U -#define DBSC_DBMRRDR6 0xE6791818U -#define DBSC_DBMRRDR7 0xE679181CU -#define DBSC_DBDTMP0 0xE6791820U -#define DBSC_DBDTMP1 0xE6791824U -#define DBSC_DBDTMP2 0xE6791828U -#define DBSC_DBDTMP3 0xE679182CU -#define DBSC_DBDTMP4 0xE6791830U -#define DBSC_DBDTMP5 0xE6791834U -#define DBSC_DBDTMP6 0xE6791838U -#define DBSC_DBDTMP7 0xE679183CU -#define DBSC_DBDQSOSC00 0xE6791840U -#define DBSC_DBDQSOSC01 0xE6791844U -#define DBSC_DBDQSOSC10 0xE6791848U -#define DBSC_DBDQSOSC11 0xE679184CU -#define DBSC_DBDQSOSC20 0xE6791850U -#define DBSC_DBDQSOSC21 0xE6791854U -#define DBSC_DBDQSOSC30 0xE6791858U -#define DBSC_DBDQSOSC31 0xE679185CU -#define DBSC_DBDQSOSC40 0xE6791860U -#define DBSC_DBDQSOSC41 0xE6791864U -#define DBSC_DBDQSOSC50 0xE6791868U -#define DBSC_DBDQSOSC51 0xE679186CU -#define DBSC_DBDQSOSC60 0xE6791870U -#define DBSC_DBDQSOSC61 0xE6791874U -#define DBSC_DBDQSOSC70 0xE6791878U -#define DBSC_DBDQSOSC71 0xE679187CU -#define DBSC_DBOSCTHH00 0xE6791880U -#define DBSC_DBOSCTHH01 0xE6791884U -#define DBSC_DBOSCTHH10 0xE6791888U -#define DBSC_DBOSCTHH11 0xE679188CU -#define DBSC_DBOSCTHH20 0xE6791890U -#define DBSC_DBOSCTHH21 0xE6791894U -#define DBSC_DBOSCTHH30 0xE6791898U -#define DBSC_DBOSCTHH31 0xE679189CU -#define DBSC_DBOSCTHH40 0xE67918A0U -#define DBSC_DBOSCTHH41 0xE67918A4U -#define DBSC_DBOSCTHH50 0xE67918A8U -#define DBSC_DBOSCTHH51 0xE67918ACU -#define DBSC_DBOSCTHH60 0xE67918B0U -#define DBSC_DBOSCTHH61 0xE67918B4U -#define DBSC_DBOSCTHH70 0xE67918B8U -#define DBSC_DBOSCTHH71 0xE67918BCU -#define DBSC_DBOSCTHL00 0xE67918C0U -#define DBSC_DBOSCTHL01 0xE67918C4U -#define DBSC_DBOSCTHL10 0xE67918C8U -#define DBSC_DBOSCTHL11 0xE67918CCU -#define DBSC_DBOSCTHL20 0xE67918D0U -#define DBSC_DBOSCTHL21 0xE67918D4U -#define DBSC_DBOSCTHL30 0xE67918D8U -#define DBSC_DBOSCTHL31 0xE67918DCU -#define DBSC_DBOSCTHL40 0xE67918E0U -#define DBSC_DBOSCTHL41 0xE67918E4U -#define DBSC_DBOSCTHL50 0xE67918E8U -#define DBSC_DBOSCTHL51 0xE67918ECU -#define DBSC_DBOSCTHL60 0xE67918F0U -#define DBSC_DBOSCTHL61 0xE67918F4U -#define DBSC_DBOSCTHL70 0xE67918F8U -#define DBSC_DBOSCTHL71 0xE67918FCU -#define DBSC_DBMEMSWAPCONF0 0xE6792000U - -/* CPG registers */ -#define CPG_SRCR4 0xE61500BCU -#define CPG_PLLECR 0xE61500D0U -#define CPG_CPGWPR 0xE6150900U -#define CPG_CPGWPCR 0xE6150904U -#define CPG_SRSTCLR4 0xE6150950U - -/* MODE Monitor registers */ -#define RST_MODEMR 0xE6160060U - -#endif /* BOOT_INIT_DRAM_REGDEF_H_*/ +#include "../ddr_regs.h" diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c index d03b1b96..a49510ed 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c @@ -8,8 +8,8 @@ #include #include #include - -#include "boot_init_dram_regdef.h" +#include "rcar_def.h" +#include "../ddr_regs.h" #define RCAR_DDR_VERSION "rev.0.01" @@ -23,7 +23,7 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); mmio_write_32(DBSC_DBKIND, 0x00000007); - mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01); + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); mmio_write_32(DBSC_DBTR0, 0x0000000D); mmio_write_32(DBSC_DBTR1, 0x00000009); @@ -51,249 +51,249 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBODT0, 0x00000001); mmio_write_32(DBSC_DBADJ0, 0x00000001); mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); mmio_write_32(DBSC_SCFCTST0, 0x0D020D04); mmio_write_32(DBSC_SCFCTST1, 0x0306040C); - mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01000001); mmio_write_32(DBSC_DBCMD, 0x08000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058A04); - mmio_write_32(DBSC_DBPDRGA0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD0, 0x0A206F89); - mmio_write_32(DBSC_DBPDRGA0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000023); - mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77); - mmio_write_32(DBSC_DBPDRGA0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28); - mmio_write_32(DBSC_DBPDRGA0, 0x00000025); - mmio_write_32(DBSC_DBPDRGD0, 0x30005E00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000026); - mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49); - mmio_write_32(DBSC_DBPDRGA0, 0x00000027); - mmio_write_32(DBSC_DBPDRGD0, 0x00000F14); - mmio_write_32(DBSC_DBPDRGA0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - - mmio_write_32(DBSC_DBPDRGA0, 0x0000000E); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9; + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; r3 = (r2 << 16) + (r2 << 8) + r2; r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; - mmio_write_32(DBSC_DBPDRGA0, 0x00000011); - mmio_write_32(DBSC_DBPDRGD0, r3); - mmio_write_32(DBSC_DBPDRGA0, 0x00000012); - mmio_write_32(DBSC_DBPDRGD0, r3); - mmio_write_32(DBSC_DBPDRGA0, 0x00000016); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000017); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000018); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000019); - mmio_write_32(DBSC_DBPDRGD0, r6); - - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000011); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000012); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000016); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000017); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000018); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000019); + mmio_write_32(DBSC_DBPDRGD_0, r6); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); mmio_write_32(DBSC_DBCMD, 0x08000001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r7); - - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + (r5 << 1)) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x0001F001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000AF); - r2 = mmio_read_32(DBSC_DBPDRGD0); - mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - mmio_write_32(DBSC_DBPDRGA0, 0x000000CF); - r2 = mmio_read_32(DBSC_DBPDRGD0); - mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8); - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; r12 = (r5 >> 0x2); if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); mmio_write_32(DBSC_DBCALCNF, 0x0100401B); @@ -302,7 +302,7 @@ static void init_ddr_d3_1866(void) mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); mmio_write_32(DBSC_DBRFEN, 0x00000001); mmio_write_32(DBSC_DBACEN, 0x00000001); - mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #ifdef ddr_qos_init_setting // only for non qos_init @@ -348,7 +348,7 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); mmio_write_32(DBSC_DBKIND, 0x00000007); - mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01); + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01); mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); mmio_write_32(DBSC_DBTR0, 0x0000000B); mmio_write_32(DBSC_DBTR1, 0x00000008); @@ -376,248 +376,248 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBODT0, 0x00000001); mmio_write_32(DBSC_DBADJ0, 0x00000001); mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); mmio_write_32(DBSC_SCFCTST0, 0x0D020C04); mmio_write_32(DBSC_SCFCTST1, 0x0305040C); - mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01000001); mmio_write_32(DBSC_DBCMD, 0x08000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058904); - mmio_write_32(DBSC_DBPDRGA0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD0, 0x08C05FF0); - mmio_write_32(DBSC_DBPDRGA0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000023); - mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); - mmio_write_32(DBSC_DBPDRGA0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400); - mmio_write_32(DBSC_DBPDRGA0, 0x00000025); - mmio_write_32(DBSC_DBPDRGD0, 0x30005200); - mmio_write_32(DBSC_DBPDRGA0, 0x00000026); - mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); - mmio_write_32(DBSC_DBPDRGA0, 0x00000027); - mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); - mmio_write_32(DBSC_DBPDRGA0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD0, 0x00000098); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000098); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - - mmio_write_32(DBSC_DBPDRGA0, 0x0000000E); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9; + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; r3 = (r2 << 16) + (r2 << 8) + r2; r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; - mmio_write_32(DBSC_DBPDRGA0, 0x00000011); - mmio_write_32(DBSC_DBPDRGD0, r3); - mmio_write_32(DBSC_DBPDRGA0, 0x00000012); - mmio_write_32(DBSC_DBPDRGD0, r3); - mmio_write_32(DBSC_DBPDRGA0, 0x00000016); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000017); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000018); - mmio_write_32(DBSC_DBPDRGD0, r6); - mmio_write_32(DBSC_DBPDRGA0, 0x00000019); - mmio_write_32(DBSC_DBPDRGD0, r6); - - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000011); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000012); + mmio_write_32(DBSC_DBPDRGD_0, r3); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000016); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000017); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000018); + mmio_write_32(DBSC_DBPDRGD_0, r6); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000019); + mmio_write_32(DBSC_DBPDRGD_0, r6); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); mmio_write_32(DBSC_DBCMD, 0x08000001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r7); - - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + (r5 << 1)) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x0001F001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000AF); - r2 = mmio_read_32(DBSC_DBPDRGD0); - mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - mmio_write_32(DBSC_DBPDRGA0, 0x000000CF); - r2 = mmio_read_32(DBSC_DBPDRGD0); - mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); - - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF); + r2 = mmio_read_32(DBSC_DBPDRGD_0); + mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 2; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; r12 = (r5 >> 0x2); if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); mmio_write_32(DBSC_DBCALCNF, 0x0100401B); @@ -626,7 +626,7 @@ static void init_ddr_d3_1600(void) mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); mmio_write_32(DBSC_DBRFEN, 0x00000001); mmio_write_32(DBSC_DBACEN, 0x00000001); - mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #ifdef ddr_qos_init_setting // only for non qos_init diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c index 7aedc88d..fc278ef5 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c @@ -11,7 +11,8 @@ #include #include "boot_init_dram.h" -#include "boot_init_dram_regdef.h" +#include "rcar_def.h" +#include "../ddr_regs.h" #include "../dram_sub_func.h" @@ -78,9 +79,9 @@ uint32_t init_ddr(void) mmio_write_32(DBSC_DBKIND, 0x00000007); #if RCAR_DRAM_DDR3L_MEMCONF == 0 - mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); /* 1GB */ + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); /* 1GB */ #else - mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); /* 2GB(default) */ + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); /* 2GB(default) */ #endif #if RCAR_DRAM_DDR3L_MEMDUAL == 1 @@ -157,7 +158,7 @@ uint32_t init_ddr(void) mmio_write_32(DBSC_DBODT0, 0x00000001); mmio_write_32(DBSC_DBADJ0, 0x00000001); mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); @@ -173,231 +174,231 @@ uint32_t init_ddr(void) /* * Initial_Step0( INITBYP ) */ - mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01840001); mmio_write_32(DBSC_DBCMD, 0x08840000); NOTICE("BL2: [COLD_BOOT]\n"); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training ) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058904); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058A04); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04); - mmio_write_32(DBSC_DBPDRGA0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); - - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step2( DRAMRST/DRAMINT training ) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD0, 0x0780C720); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720); else - mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000004); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); /* Select setting value in bps */ if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) - + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) - + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) - 400 + 0x0A300000); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000023); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77); + mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); - mmio_write_32(DBSC_DBPDRGA0, 0x00000024); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); - mmio_write_32(DBSC_DBPDRGA0, 0x00000025); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x30005200); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x30005E00); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000026); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); - mmio_write_32(DBSC_DBPDRGA0, 0x00000027); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x00000F14); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); - mmio_write_32(DBSC_DBPDRGA0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA0, 0x00000029); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); /* Select setting value in bps */ if (ddr_md == 0) { /* 1584Mbps */ if (REFRESH_RATE > 3900) /* [7]SRT=0 */ - mmio_write_32(DBSC_DBPDRGD0, 0x18); + mmio_write_32(DBSC_DBPDRGD_0, 0x18); else /* [7]SRT=1 */ - mmio_write_32(DBSC_DBPDRGD0, 0x98); + mmio_write_32(DBSC_DBPDRGD_0, 0x98); } else { /* 1856Mbps */ if (REFRESH_RATE > 3900) /* [7]SRT=0 */ - mmio_write_32(DBSC_DBPDRGD0, 0x20); + mmio_write_32(DBSC_DBPDRGD_0, 0x20); else /* [7]SRT=1 */ - mmio_write_32(DBSC_DBPDRGD0, 0xA0); + mmio_write_32(DBSC_DBPDRGD_0, 0xA0); } - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000107); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000108); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000109); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); mmio_write_32(DBSC_DBCMD, 0x08840001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step3( WL/QSG training ) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r7); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + ((r5) << 1)) & 0xFF)); } @@ -406,191 +407,191 @@ uint32_t init_ddr(void) /* * Initial_Step4( WLADJ training ) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step5(Read Data Bit Deskew) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00011001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00011001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } /* * Initial_Step6(Write Data Bit Deskew) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00012001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00012001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step7(Read Data Eye Training) */ if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00014001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00014001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } /* * Initial_Step8(Write Data Eye Training) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00018001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00018001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* * Initial_Step3_2( DQS Gate Training ) */ - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8); - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; r12 = (r5 >> 0x2); if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 + r5 + + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } } @@ -599,40 +600,40 @@ uint32_t init_ddr(void) * Initial_Step5-2_7-2( Rd bit Rd eye ) */ if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (lcdl_ctl == 1) { for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; bdlcount_0c_div2 = bdlcount_0c >> 1; bdlcount_0c_div4 = bdlcount_0c >> 2; @@ -657,43 +658,43 @@ uint32_t init_ddr(void) continue; if (dqsgd_0c <= lcdl_judge2) { - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGD_0, (dqsgd_0c - bdlcount_0c_div8) | regval); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGD0, regval | + mmio_write_32(DBSC_DBPDRGD_0, regval | (gatesl_0c + 1)); - mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD0)); + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); rdqsd_0c = (regval & 0xFF00) >> 8; rdqsnd_0c = (regval & 0xFF0000) >> 16; - mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, (regval & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)); - mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD0)); + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); rbd_0c[0] = (regval) & 0x1f; rbd_0c[1] = (regval >> 8) & 0x1f; rbd_0c[2] = (regval >> 16) & 0x1f; rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xE0E0E0E0; for (j = 0; j < 4; j++) { rbd_0c[j] = rbd_0c[j] + @@ -702,15 +703,15 @@ uint32_t init_ddr(void) rbd_0c[j] = 0x1F; regval = regval | (rbd_0c[j] << 8 * j); } - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD0)); + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); rbd_0c[0] = (regval) & 0x1f; rbd_0c[1] = (regval >> 8) & 0x1f; rbd_0c[2] = (regval >> 16) & 0x1f; rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xE0E0E0E0; for (j = 0; j < 4; j++) { rbd_0c[j] = rbd_0c[j] + @@ -719,25 +720,25 @@ uint32_t init_ddr(void) rbd_0c[j] = 0x1F; regval = regval | (rbd_0c[j] << 8 * j); } - mmio_write_32(DBSC_DBPDRGD0, regval); + mmio_write_32(DBSC_DBPDRGD_0, regval); } } - mmio_write_32(DBSC_DBPDRGA0, 0x2); - mmio_write_32(DBSC_DBPDRGD0, 0x7D81E37); + mmio_write_32(DBSC_DBPDRGA_0, 0x2); + mmio_write_32(DBSC_DBPDRGD_0, 0x7D81E37); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD0, 0x0380C720); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720); else - mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000); @@ -758,34 +759,34 @@ uint32_t init_ddr(void) if (pdqsr_ctl == 1) { mmio_write_32(0xE67F0018, 0x00000001); regval = mmio_read_32(0x40000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000000); - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } /* * Initial_Step9( Initial End ) */ - mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #ifdef ddr_qos_init_setting /* only for non qos_init */ @@ -881,9 +882,9 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) mmio_write_32(DBSC_DBKIND, 0x00000007); #if RCAR_DRAM_DDR3L_MEMCONF == 0 - mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); #else - mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); #endif #if RCAR_DRAM_DDR3L_MEMDUAL == 1 @@ -960,7 +961,7 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) mmio_write_32(DBSC_DBODT0, 0x00000001); mmio_write_32(DBSC_DBADJ0, 0x00000001); mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); mmio_write_32(DBSC_DBSCHRW1, 0x00000046); @@ -976,143 +977,143 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) /* * recovery_Step1(PHY setting 1) */ - mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01840001); mmio_write_32(DBSC_DBCMD, 0x0A840000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000008); /* DDR_PLLCR */ - mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); /* DDR_PGCR1 */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); /* DDR_PLLCR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); /* DDR_PGCR1 */ if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD0, 0x0780C720); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C720); else - mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); - - mmio_write_32(DBSC_DBPDRGA0, 0x00000020); /* DDR_DXCCR */ - mmio_write_32(DBSC_DBPDRGD0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); /* DDR_ACIOCR0 */ - mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); /* DDR_DXCCR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); /* DDR_ACIOCR0 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000004); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); /* Select setting value in bps */ if (ddr_md == 0) { /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) - + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); } else { /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) - + mmio_write_32(DBSC_DBPDRGD_0, (REFRESH_RATE * 928 / 125) - 400 + 0x0A300000); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000023); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77); + mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77); - mmio_write_32(DBSC_DBPDRGA0, 0x00000024); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28); - mmio_write_32(DBSC_DBPDRGA0, 0x00000025); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x30005200); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x30005E00); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000026); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49); - mmio_write_32(DBSC_DBPDRGA0, 0x00000027); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x00000F14); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14); - mmio_write_32(DBSC_DBPDRGA0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD0, 0x00000046); - mmio_write_32(DBSC_DBPDRGA0, 0x00000029); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); /* Select setting value in bps */ if (ddr_md == 0) { /* 1584Mbps */ if (REFRESH_RATE > 3900) - mmio_write_32(DBSC_DBPDRGD0, 0x18); /* [7]SRT=0 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x18); /* [7]SRT=0 */ else - mmio_write_32(DBSC_DBPDRGD0, 0x98); /* [7]SRT=1 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x98); /* [7]SRT=1 */ } else { /* 1856Mbps */ if (REFRESH_RATE > 3900) - mmio_write_32(DBSC_DBPDRGD0, 0x20); /* [7]SRT=0 */ + mmio_write_32(DBSC_DBPDRGD_0, 0x20); /* [7]SRT=0 */ else - mmio_write_32(DBSC_DBPDRGD0, 0xA0); /* [7]SRT=1 */ + mmio_write_32(DBSC_DBPDRGD_0, 0xA0); /* [7]SRT=1 */ } - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); - mmio_write_32(DBSC_DBPDRGA0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); /* DDR_DSGCR */ - mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); /* DDR_DSGCR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x40010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x40010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ - mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ - mmio_write_32(DBSC_DBPDRGD0, 0xC4285FBF); - mmio_write_32(DBSC_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ - mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000092); /* DDR_ZQ0DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000096); /* DDR_ZQ1DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0xC4285FBF); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A); /* DDR_ZQ2DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0xC2C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x00050001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00050001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; /* ddr backupmode end */ @@ -1127,87 +1128,87 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) return INITDRAM_ERR_I; } - mmio_write_32(DBSC_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ - mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ - mmio_write_32(DBSC_DBPDRGD0, 0x04285FBF); - mmio_write_32(DBSC_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ - mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000092); /* DDR_ZQ0DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000096); /* DDR_ZQ1DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x04285FBF); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000009A); /* DDR_ZQ2DR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x02C59AB5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x08000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x08000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x00000003); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00000003); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); /* DDR_ZQCR */ /* Select setting value in bps */ if (ddr_md == 0) /* 1584Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); else /* 1856Mbps */ - mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00); - mmio_write_32(DBSC_DBPDRGA0, 0x0000000C); - mmio_write_32(DBSC_DBPDRGD0, 0x18000040); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000000C); + mmio_write_32(DBSC_DBPDRGD_0, 0x18000040); /* * recovery_Step2(PHY setting 2) */ - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000107); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000108); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000109); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); @@ -1233,258 +1234,258 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) while (mmio_read_32(DBSC_DBWAIT) & BIT(0)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ - mmio_write_32(DBSC_DBPDRGD0, 0x00010701); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD_0, 0x00010701); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r7); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + (r5 << 1)) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0); if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00011001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00011001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00012001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00012001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00014001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00014001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (pdqsr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00018001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00018001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8); - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; r12 = r5 >> 0x2; if (r12 < r6) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF)); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } } if (pdqsr_ctl == 0) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR always off */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000008); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; if (lcdl_ctl == 1) { for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20); - dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x000000FF; - mmio_write_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20); - bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0x000000B0 + i * 0x20); + dqsgd_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x000000FF; + mmio_write_32(DBSC_DBPDRGA_0, 0x000000B1 + i * 0x20); + bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 8; bdlcount_0c_div2 = (bdlcount_0c >> 1); bdlcount_0c_div4 = (bdlcount_0c >> 2); @@ -1509,43 +1510,43 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) continue; if (dqsgd_0c <= lcdl_judge2) { - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGD_0, (dqsgd_0c - bdlcount_0c_div8) | regval); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7; - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + gatesl_0c = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGD_0, regval | (gatesl_0c + 1)); - mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0); + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0); rdqsd_0c = (regval & 0xFF00) >> 8; rdqsnd_0c = (regval & 0xFF0000) >> 16; - mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, + mmio_write_32(DBSC_DBPDRGA_0, 0xAF + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, (regval & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16)); - mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD0)); + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); rbd_0c[0] = (regval) & 0x1f; rbd_0c[1] = (regval >> 8) & 0x1f; rbd_0c[2] = (regval >> 16) & 0x1f; rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xAA + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xE0E0E0E0; for (j = 0; j < 4; j++) { rbd_0c[j] = rbd_0c[j] + @@ -1554,15 +1555,15 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) rbd_0c[j] = 0x1F; regval = regval | (rbd_0c[j] << 8 * j); } - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); - regval = (mmio_read_32(DBSC_DBPDRGD0)); + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD_0)); rbd_0c[0] = regval & 0x1f; rbd_0c[1] = (regval >> 8) & 0x1f; rbd_0c[2] = (regval >> 16) & 0x1f; rbd_0c[3] = (regval >> 24) & 0x1f; - mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); - regval = mmio_read_32(DBSC_DBPDRGD0) & + mmio_write_32(DBSC_DBPDRGA_0, 0xAB + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD_0) & 0xE0E0E0E0; for (j = 0; j < 4; j++) { rbd_0c[j] = rbd_0c[j] + @@ -1571,24 +1572,24 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) rbd_0c[j] = 0x1F; regval = regval | (rbd_0c[j] << 8 * j); } - mmio_write_32(DBSC_DBPDRGD0, regval); + mmio_write_32(DBSC_DBPDRGD_0, regval); } } - mmio_write_32(DBSC_DBPDRGA0, 0x00000002); - mmio_write_32(DBSC_DBPDRGD0, 0x07D81E37); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000002); + mmio_write_32(DBSC_DBPDRGD_0, 0x07D81E37); } - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); if (byp_ctl == 1) - mmio_write_32(DBSC_DBPDRGD0, 0x0380C720); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C720); else - mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); /* * recovery_Step3(DBSC Setting 2) @@ -1599,31 +1600,31 @@ static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) if (pdqsr_ctl == 1) { mmio_write_32(0xE67F0018, 0x00000001); regval = mmio_read_32(0x40000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000000); - mmio_write_32(DBSC_DBPDRGD0, regval); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGD_0, regval); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); } /* PDR dynamic */ if (pdr_ctl == 1) { - mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000103); - mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000000); } - mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #ifdef ddr_qos_init_setting /* only for non qos_init */ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c index 00e1903c..5410771c 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c @@ -9,7 +9,8 @@ #include #include #include "boot_init_dram.h" -#include "boot_init_dram_regdef.h" +#include "rcar_def.h" +#include "../ddr_regs.h" static uint32_t init_ddr_v3m_1600(void) { @@ -18,9 +19,9 @@ static uint32_t init_ddr_v3m_1600(void) mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); mmio_write_32(DBSC_DBKIND, 0x00000007); #if RCAR_DRAM_DDR3L_MEMCONF == 0 - mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); // 1GB: Eagle + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); // 1GB: Eagle #else - mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); // 2GB: V3MSK + mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); // 2GB: V3MSK #endif mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); mmio_write_32(DBSC_DBTR0, 0x0000000B); @@ -79,243 +80,243 @@ static uint32_t init_ddr_v3m_1600(void) mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4); mmio_write_32(DBSC_DBSCHSZ0, 0x00000003); mmio_write_32(DBSC_DBSCHRW1, 0x001a0080); - mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBDFICNT_0, 0x00000010); - mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A); mmio_write_32(DBSC_DBCMD, 0x01000001); mmio_write_32(DBSC_DBCMD, 0x08000000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x80010000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000008); - mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058904); - mmio_write_32(DBSC_DBPDRGA0, 0x00000091); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000095); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000099); - mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010073); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058904); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000090); - mmio_write_32(DBSC_DBPDRGD0, 0x04058900); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD_0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000004); - mmio_write_32(DBSC_DBPDRGD0, 0x08C0C170); - mmio_write_32(DBSC_DBPDRGA0, 0x00000022); - mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); - mmio_write_32(DBSC_DBPDRGA0, 0x00000023); - mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); - mmio_write_32(DBSC_DBPDRGA0, 0x00000024); - mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400); - mmio_write_32(DBSC_DBPDRGA0, 0x00000025); - mmio_write_32(DBSC_DBPDRGD0, 0x30005200); - mmio_write_32(DBSC_DBPDRGA0, 0x00000026); - mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); - mmio_write_32(DBSC_DBPDRGA0, 0x00000027); - mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); - mmio_write_32(DBSC_DBPDRGA0, 0x00000028); - mmio_write_32(DBSC_DBPDRGD0, 0x00000004); - mmio_write_32(DBSC_DBPDRGA0, 0x00000029); - mmio_write_32(DBSC_DBPDRGD0, 0x00000018); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003047); - mmio_write_32(DBSC_DBPDRGA0, 0x00000020); - mmio_write_32(DBSC_DBPDRGD0, 0x00181884); - mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); - mmio_write_32(DBSC_DBPDRGD0, 0x13C03C10); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD_0, 0x08C0C170); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD_0, 0x30005200); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000004); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD_0, 0x00000018); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD_0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD_0, 0x13C03C10); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E7); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E8); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E9); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000107); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000108); - mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000109); - mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010181); mmio_write_32(DBSC_DBCMD, 0x08000001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010601); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; if (r6 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | r7); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | (((r5 << 1) + r6) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00A0); - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010801); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00A0); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000005); - mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00B8); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x0001F001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00B8); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); - mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); - mmio_write_32(DBSC_DBPDRGD0, 0x81003087); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00010401); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD_0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; for (i = 0; i < 4; i++) { - mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); - r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8; - mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); - r6 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF); + mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; + mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); + r6 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF); - mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); - r7 = (mmio_read_32(DBSC_DBPDRGD0) & 0x7); + mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); + r7 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x7); r12 = (r5 >> 2); if (r6 - r12 > 0) { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, ((r6 - r12) & 0xFF) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, ((r6 - r12) & 0xFF) | r2); } else { - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); - mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, (r7 & 0x7) | r2); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); - mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); - mmio_write_32(DBSC_DBPDRGD0, r2 | + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, (r7 & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } } - mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000100); - mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); - mmio_write_32(DBSC_DBPDRGA0, 0x00000001); - mmio_write_32(DBSC_DBPDRGD0, 0x00015001); - mmio_write_32(DBSC_DBPDRGA0, 0x00000006); - while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD_0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000003); - mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); - mmio_write_32(DBSC_DBPDRGA0, 0x00000007); - while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + mmio_write_32(DBSC_DBPDRGA_0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)) ; - mmio_write_32(DBSC_DBPDRGA0, 0x00000021); - mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + mmio_write_32(DBSC_DBPDRGA_0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E); mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000); mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001); @@ -325,7 +326,7 @@ static uint32_t init_ddr_v3m_1600(void) mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); mmio_write_32(DBSC_DBRFEN, 0x00000001); mmio_write_32(DBSC_DBACEN, 0x00000001); - mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBPDLK_0, 0x00000000); mmio_write_32(0xE67F0024, 0x00000001); mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h index abddf0cf..0bc2bc16 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h @@ -32,7 +32,6 @@ #define DBSC_REFINTS (0x0) /* system registers */ -#define CPG_BASE (0xE6150000U) #define CPG_FRQCRB (CPG_BASE + 0x0004U) #define CPG_PLLECR (CPG_BASE + 0x00D0U) @@ -56,179 +55,7 @@ #define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x)) /* DBSC registers */ -#define DBSC_DBSYSCONF1 0xE6790004U -#define DBSC_DBPHYCONF0 0xE6790010U -#define DBSC_DBKIND 0xE6790020U - -#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) -#define DBSC_DBMEMCONF_0_0 0xE6790030U -#define DBSC_DBMEMCONF_0_1 0xE6790034U -#define DBSC_DBMEMCONF_0_2 0xE6790038U -#define DBSC_DBMEMCONF_0_3 0xE679003CU -#define DBSC_DBMEMCONF_1_2 0xE6790048U -#define DBSC_DBMEMCONF_1_3 0xE679004CU -#define DBSC_DBMEMCONF_1_0 0xE6790040U -#define DBSC_DBMEMCONF_1_1 0xE6790044U -#define DBSC_DBMEMCONF_2_0 0xE6790050U -#define DBSC_DBMEMCONF_2_1 0xE6790054U -#define DBSC_DBMEMCONF_2_2 0xE6790058U -#define DBSC_DBMEMCONF_2_3 0xE679005CU -#define DBSC_DBMEMCONF_3_0 0xE6790060U -#define DBSC_DBMEMCONF_3_1 0xE6790064U -#define DBSC_DBMEMCONF_3_2 0xE6790068U -#define DBSC_DBMEMCONF_3_3 0xE679006CU - -#define DBSC_DBSYSCNT0 0xE6790100U - -#define DBSC_DBACEN 0xE6790200U -#define DBSC_DBRFEN 0xE6790204U -#define DBSC_DBCMD 0xE6790208U -#define DBSC_DBWAIT 0xE6790210U -#define DBSC_DBSYSCTRL0 0xE6790280U - -#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x)) -#define DBSC_DBTR0 0xE6790300U -#define DBSC_DBTR1 0xE6790304U -#define DBSC_DBTR3 0xE679030CU -#define DBSC_DBTR4 0xE6790310U -#define DBSC_DBTR5 0xE6790314U -#define DBSC_DBTR6 0xE6790318U -#define DBSC_DBTR7 0xE679031CU -#define DBSC_DBTR8 0xE6790320U -#define DBSC_DBTR9 0xE6790324U -#define DBSC_DBTR10 0xE6790328U -#define DBSC_DBTR11 0xE679032CU -#define DBSC_DBTR12 0xE6790330U -#define DBSC_DBTR13 0xE6790334U -#define DBSC_DBTR14 0xE6790338U -#define DBSC_DBTR15 0xE679033CU -#define DBSC_DBTR16 0xE6790340U -#define DBSC_DBTR17 0xE6790344U -#define DBSC_DBTR18 0xE6790348U -#define DBSC_DBTR19 0xE679034CU -#define DBSC_DBTR20 0xE6790350U -#define DBSC_DBTR21 0xE6790354U -#define DBSC_DBTR22 0xE6790358U -#define DBSC_DBTR23 0xE679035CU -#define DBSC_DBTR24 0xE6790360U -#define DBSC_DBTR25 0xE6790364U -#define DBSC_DBTR26 0xE6790368U - -#define DBSC_DBBL 0xE6790400U -#define DBSC_DBRFCNF1 0xE6790414U -#define DBSC_DBRFCNF2 0xE6790418U -#define DBSC_DBTSPCNF 0xE6790420U -#define DBSC_DBCALCNF 0xE6790424U -#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x)) -#define DBSC_DBRNK2 0xE6790438U -#define DBSC_DBRNK3 0xE679043CU -#define DBSC_DBRNK4 0xE6790440U -#define DBSC_DBRNK5 0xE6790444U -#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x)) - -#define DBSC_DBADJ0 0xE6790500U -#define DBSC_DBDBICNT 0xE6790518U -#define DBSC_DBDFIPMSTRCNF 0xE6790520U -#define DBSC_DBDFICUPDCNF 0xE679052CU - -#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch)) -#define DBSC_DBDFISTAT_0 0xE6790600U -#define DBSC_DBDFISTAT_1 0xE6790640U -#define DBSC_DBDFISTAT_2 0xE6790680U -#define DBSC_DBDFISTAT_3 0xE67906C0U - -#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch)) -#define DBSC_DBDFICNT_0 0xE6790604U -#define DBSC_DBDFICNT_1 0xE6790644U -#define DBSC_DBDFICNT_2 0xE6790684U -#define DBSC_DBDFICNT_3 0xE67906C4U - -#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch)) -#define DBSC_DBPDCNT0_0 0xE6790610U -#define DBSC_DBPDCNT0_1 0xE6790650U -#define DBSC_DBPDCNT0_2 0xE6790690U -#define DBSC_DBPDCNT0_3 0xE67906D0U - -#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch)) -#define DBSC_DBPDCNT1_0 0xE6790614U -#define DBSC_DBPDCNT1_1 0xE6790654U -#define DBSC_DBPDCNT1_2 0xE6790694U -#define DBSC_DBPDCNT1_3 0xE67906D4U - -#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch)) -#define DBSC_DBPDCNT2_0 0xE6790618U -#define DBSC_DBPDCNT2_1 0xE6790658U -#define DBSC_DBPDCNT2_2 0xE6790698U -#define DBSC_DBPDCNT2_3 0xE67906D8U - -#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch)) -#define DBSC_DBPDCNT3_0 0xE679061CU -#define DBSC_DBPDCNT3_1 0xE679065CU -#define DBSC_DBPDCNT3_2 0xE679069CU -#define DBSC_DBPDCNT3_3 0xE67906DCU - -#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch)) -#define DBSC_DBPDLK_0 0xE6790620U -#define DBSC_DBPDLK_1 0xE6790660U -#define DBSC_DBPDLK_2 0xE67906a0U -#define DBSC_DBPDLK_3 0xE67906e0U - -#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch)) -#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch)) -#define DBSC_DBPDRGA_0 0xE6790624U -#define DBSC_DBPDRGD_0 0xE6790628U -#define DBSC_DBPDRGA_1 0xE6790664U -#define DBSC_DBPDRGD_1 0xE6790668U -#define DBSC_DBPDRGA_2 0xE67906A4U -#define DBSC_DBPDRGD_2 0xE67906A8U -#define DBSC_DBPDRGA_3 0xE67906E4U -#define DBSC_DBPDRGD_3 0xE67906E8U - -#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch)) -#define DBSC_DBPDSTAT_0 0xE6790630U -#define DBSC_DBPDSTAT_1 0xE6790670U -#define DBSC_DBPDSTAT_2 0xE67906B0U -#define DBSC_DBPDSTAT_3 0xE67906F0U - -#define DBSC_DBBUS0CNF0 0xE6790800U -#define DBSC_DBBUS0CNF1 0xE6790804U - -#define DBSC_DBCAM0CNF1 0xE6790904U -#define DBSC_DBCAM0CNF2 0xE6790908U -#define DBSC_DBCAM0CNF3 0xE679090CU -#define DBSC_DBBSWAP 0xE67909F0U -#define DBSC_DBBCAMDIS 0xE67909FCU -#define DBSC_DBSCHCNT0 0xE6791000U -#define DBSC_DBSCHCNT1 0xE6791004U -#define DBSC_DBSCHSZ0 0xE6791010U -#define DBSC_DBSCHRW0 0xE6791020U -#define DBSC_DBSCHRW1 0xE6791024U - -#define DBSC_DBSCHQOS_0(x) (0xE6791030U +0x10U * (x)) -#define DBSC_DBSCHQOS_1(x) (0xE6791034U +0x10U * (x)) -#define DBSC_DBSCHQOS_2(x) (0xE6791038U +0x10U * (x)) -#define DBSC_DBSCHQOS_3(x) (0xE679103CU +0x10U * (x)) - -#define DBSC_DBSCTR0 0xE6791700U -#define DBSC_DBSCTR1 0xE6791708U -#define DBSC_DBSCHRW2 0xE679170CU - -#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x)) -#define DBSC_SCFCTST0 0xE6791700U -#define DBSC_SCFCTST1 0xE6791708U -#define DBSC_SCFCTST2 0xE679170CU - -#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab)) -#define DBSC_DBMRRDR_0 0xE6791800U -#define DBSC_DBMRRDR_1 0xE6791804U -#define DBSC_DBMRRDR_2 0xE6791808U -#define DBSC_DBMRRDR_3 0xE679180CU -#define DBSC_DBMRRDR_4 0xE6791810U -#define DBSC_DBMRRDR_5 0xE6791814U -#define DBSC_DBMRRDR_6 0xE6791818U -#define DBSC_DBMRRDR_7 0xE679181CU - -#define DBSC_DBMEMSWAPCONF0 0xE6792000U +#include "../ddr_regs.h" #define DBSC_DBMONCONF4 0xE6793010U @@ -264,33 +91,3 @@ /* other module */ #define THS1_THCTR 0xE6198020U #define THS1_TEMP 0xE6198028U - -#define DBSC_BASE (0xE6790000U) -#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U) -#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U) -#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U) -#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU) -#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U) -#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U) -#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U) -#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU) -#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U) -#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U) -#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U) -#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU) -#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U) -#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U) -#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U) -#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU) -#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U) -#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U) -#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U) -#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU) -#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U) -#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U) -#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U) -#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU) -#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U) -#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U) -#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U) -#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_regs.h b/drivers/staging/renesas/rcar/ddr/ddr_regs.h new file mode 100644 index 00000000..ba26c69c --- /dev/null +++ b/drivers/staging/renesas/rcar/ddr/ddr_regs.h @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOOT_INIT_DRAM_REGDEF_H_ +#define BOOT_INIT_DRAM_REGDEF_H_ + +/* DBSC registers */ +#define DBSC_DBSYSCONF0 0xE6790000U +#define DBSC_DBSYSCONF1 0xE6790004U +#define DBSC_DBPHYCONF0 0xE6790010U +#define DBSC_DBKIND 0xE6790020U +#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0 0xE6790030U +#define DBSC_DBMEMCONF_0_1 0xE6790034U +#define DBSC_DBMEMCONF_0_2 0xE6790038U +#define DBSC_DBMEMCONF_0_3 0xE679003CU +#define DBSC_DBMEMCONF_1_2 0xE6790048U +#define DBSC_DBMEMCONF_1_3 0xE679004CU +#define DBSC_DBMEMCONF_1_0 0xE6790040U +#define DBSC_DBMEMCONF_1_1 0xE6790044U +#define DBSC_DBMEMCONF_2_0 0xE6790050U +#define DBSC_DBMEMCONF_2_1 0xE6790054U +#define DBSC_DBMEMCONF_2_2 0xE6790058U +#define DBSC_DBMEMCONF_2_3 0xE679005CU +#define DBSC_DBMEMCONF_3_0 0xE6790060U +#define DBSC_DBMEMCONF_3_1 0xE6790064U +#define DBSC_DBMEMCONF_3_2 0xE6790068U +#define DBSC_DBMEMCONF_3_3 0xE679006CU +#define DBSC_DBSYSCNT0 0xE6790100U +#define DBSC_DBSVCR1 0xE6790104U +#define DBSC_DBSTATE0 0xE6790108U +#define DBSC_DBSTATE1 0xE679010CU +#define DBSC_DBINTEN 0xE6790180U +#define DBSC_DBINTSTAT0 0xE6790184U +#define DBSC_DBACEN 0xE6790200U +#define DBSC_DBRFEN 0xE6790204U +#define DBSC_DBCMD 0xE6790208U +#define DBSC_DBWAIT 0xE6790210U +#define DBSC_DBSYSCTRL0 0xE6790280U +#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x)) +#define DBSC_DBTR0 0xE6790300U +#define DBSC_DBTR1 0xE6790304U +#define DBSC_DBTR2 0xE6790308U +#define DBSC_DBTR3 0xE679030CU +#define DBSC_DBTR4 0xE6790310U +#define DBSC_DBTR5 0xE6790314U +#define DBSC_DBTR6 0xE6790318U +#define DBSC_DBTR7 0xE679031CU +#define DBSC_DBTR8 0xE6790320U +#define DBSC_DBTR9 0xE6790324U +#define DBSC_DBTR10 0xE6790328U +#define DBSC_DBTR11 0xE679032CU +#define DBSC_DBTR12 0xE6790330U +#define DBSC_DBTR13 0xE6790334U +#define DBSC_DBTR14 0xE6790338U +#define DBSC_DBTR15 0xE679033CU +#define DBSC_DBTR16 0xE6790340U +#define DBSC_DBTR17 0xE6790344U +#define DBSC_DBTR18 0xE6790348U +#define DBSC_DBTR19 0xE679034CU +#define DBSC_DBTR20 0xE6790350U +#define DBSC_DBTR21 0xE6790354U +#define DBSC_DBTR22 0xE6790358U +#define DBSC_DBTR23 0xE679035CU +#define DBSC_DBTR24 0xE6790360U +#define DBSC_DBTR25 0xE6790364U +#define DBSC_DBTR26 0xE6790368U +#define DBSC_DBBL 0xE6790400U +#define DBSC_DBRFCNF1 0xE6790414U +#define DBSC_DBRFCNF2 0xE6790418U +#define DBSC_DBTSPCNF 0xE6790420U +#define DBSC_DBCALCNF 0xE6790424U +#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x)) +#define DBSC_DBRNK2 0xE6790438U +#define DBSC_DBRNK3 0xE679043CU +#define DBSC_DBRNK4 0xE6790440U +#define DBSC_DBRNK5 0xE6790444U +#define DBSC_DBPDNCNF 0xE6790450U +#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x)) +#define DBSC_DBODT0 0xE6790460U +#define DBSC_DBODT1 0xE6790464U +#define DBSC_DBODT2 0xE6790468U +#define DBSC_DBODT3 0xE679046CU +#define DBSC_DBODT4 0xE6790470U +#define DBSC_DBODT5 0xE6790474U +#define DBSC_DBODT6 0xE6790478U +#define DBSC_DBODT7 0xE679047CU +#define DBSC_DBADJ0 0xE6790500U +#define DBSC_DBDBICNT 0xE6790518U +#define DBSC_DBDFIPMSTRCNF 0xE6790520U +#define DBSC_DBDFICUPDCNF 0xE679052CU +#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch)) +#define DBSC_DBDFISTAT_0 0xE6790600U +#define DBSC_DBDFISTAT_1 0xE6790640U +#define DBSC_DBDFISTAT_2 0xE6790680U +#define DBSC_DBDFISTAT_3 0xE67906C0U +#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch)) +#define DBSC_DBDFICNT_0 0xE6790604U +#define DBSC_DBDFICNT_1 0xE6790644U +#define DBSC_DBDFICNT_2 0xE6790684U +#define DBSC_DBDFICNT_3 0xE67906C4U +#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch)) +#define DBSC_DBPDCNT0_0 0xE6790610U +#define DBSC_DBPDCNT0_1 0xE6790650U +#define DBSC_DBPDCNT0_2 0xE6790690U +#define DBSC_DBPDCNT0_3 0xE67906D0U +#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch)) +#define DBSC_DBPDCNT1_0 0xE6790614U +#define DBSC_DBPDCNT1_1 0xE6790654U +#define DBSC_DBPDCNT1_2 0xE6790694U +#define DBSC_DBPDCNT1_3 0xE67906D4U +#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch)) +#define DBSC_DBPDCNT2_0 0xE6790618U +#define DBSC_DBPDCNT2_1 0xE6790658U +#define DBSC_DBPDCNT2_2 0xE6790698U +#define DBSC_DBPDCNT2_3 0xE67906D8U +#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch)) +#define DBSC_DBPDCNT3_0 0xE679061CU +#define DBSC_DBPDCNT3_1 0xE679065CU +#define DBSC_DBPDCNT3_2 0xE679069CU +#define DBSC_DBPDCNT3_3 0xE67906DCU +#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch)) +#define DBSC_DBPDLK_0 0xE6790620U +#define DBSC_DBPDLK_1 0xE6790660U +#define DBSC_DBPDLK_2 0xE67906a0U +#define DBSC_DBPDLK_3 0xE67906e0U +#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch)) +#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch)) +#define DBSC_DBPDRGA_0 0xE6790624U +#define DBSC_DBPDRGD_0 0xE6790628U +#define DBSC_DBPDRGA_1 0xE6790664U +#define DBSC_DBPDRGD_1 0xE6790668U +#define DBSC_DBPDRGA_2 0xE67906A4U +#define DBSC_DBPDRGD_2 0xE67906A8U +#define DBSC_DBPDRGA_3 0xE67906E4U +#define DBSC_DBPDRGD_3 0xE67906E8U +#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch)) +#define DBSC_DBPDSTAT_0 0xE6790630U +#define DBSC_DBPDSTAT_1 0xE6790670U +#define DBSC_DBPDSTAT_2 0xE67906B0U +#define DBSC_DBPDSTAT_3 0xE67906F0U +#define DBSC_DBBUS0CNF0 0xE6790800U +#define DBSC_DBBUS0CNF1 0xE6790804U +#define DBSC_DBCAM0CNF1 0xE6790904U +#define DBSC_DBCAM0CNF2 0xE6790908U +#define DBSC_DBCAM0CNF3 0xE679090CU +#define DBSC_DBBSWAP 0xE67909F0U +#define DBSC_DBBCAMDIS 0xE67909FCU +#define DBSC_DBSCHCNT0 0xE6791000U +#define DBSC_DBSCHCNT1 0xE6791004U +#define DBSC_DBSCHSZ0 0xE6791010U +#define DBSC_DBSCHRW0 0xE6791020U +#define DBSC_DBSCHRW1 0xE6791024U +#define DBSC_DBSCHQOS_0(x) (0xE6791030U + 0x10U * (x)) +#define DBSC_DBSCHQOS_1(x) (0xE6791034U + 0x10U * (x)) +#define DBSC_DBSCHQOS_2(x) (0xE6791038U + 0x10U * (x)) +#define DBSC_DBSCHQOS_3(x) (0xE679103CU + 0x10U * (x)) +#define DBSC_DBSCHQOS00 0xE6791030U +#define DBSC_DBSCHQOS01 0xE6791034U +#define DBSC_DBSCHQOS02 0xE6791038U +#define DBSC_DBSCHQOS03 0xE679103CU +#define DBSC_DBSCHQOS10 0xE6791040U +#define DBSC_DBSCHQOS11 0xE6791044U +#define DBSC_DBSCHQOS12 0xE6791048U +#define DBSC_DBSCHQOS13 0xE679104CU +#define DBSC_DBSCHQOS20 0xE6791050U +#define DBSC_DBSCHQOS21 0xE6791054U +#define DBSC_DBSCHQOS22 0xE6791058U +#define DBSC_DBSCHQOS23 0xE679105CU +#define DBSC_DBSCHQOS30 0xE6791060U +#define DBSC_DBSCHQOS31 0xE6791064U +#define DBSC_DBSCHQOS32 0xE6791068U +#define DBSC_DBSCHQOS33 0xE679106CU +#define DBSC_DBSCHQOS40 0xE6791070U +#define DBSC_DBSCHQOS41 0xE6791074U +#define DBSC_DBSCHQOS42 0xE6791078U +#define DBSC_DBSCHQOS43 0xE679107CU +#define DBSC_DBSCHQOS50 0xE6791080U +#define DBSC_DBSCHQOS51 0xE6791084U +#define DBSC_DBSCHQOS52 0xE6791088U +#define DBSC_DBSCHQOS53 0xE679108CU +#define DBSC_DBSCHQOS60 0xE6791090U +#define DBSC_DBSCHQOS61 0xE6791094U +#define DBSC_DBSCHQOS62 0xE6791098U +#define DBSC_DBSCHQOS63 0xE679109CU +#define DBSC_DBSCHQOS70 0xE67910A0U +#define DBSC_DBSCHQOS71 0xE67910A4U +#define DBSC_DBSCHQOS72 0xE67910A8U +#define DBSC_DBSCHQOS73 0xE67910ACU +#define DBSC_DBSCHQOS80 0xE67910B0U +#define DBSC_DBSCHQOS81 0xE67910B4U +#define DBSC_DBSCHQOS82 0xE67910B8U +#define DBSC_DBSCHQOS83 0xE67910BCU +#define DBSC_DBSCHQOS90 0xE67910C0U +#define DBSC_DBSCHQOS91 0xE67910C4U +#define DBSC_DBSCHQOS92 0xE67910C8U +#define DBSC_DBSCHQOS93 0xE67910CCU +#define DBSC_DBSCHQOS100 0xE67910D0U +#define DBSC_DBSCHQOS101 0xE67910D4U +#define DBSC_DBSCHQOS102 0xE67910D8U +#define DBSC_DBSCHQOS103 0xE67910DCU +#define DBSC_DBSCHQOS110 0xE67910E0U +#define DBSC_DBSCHQOS111 0xE67910E4U +#define DBSC_DBSCHQOS112 0xE67910E8U +#define DBSC_DBSCHQOS113 0xE67910ECU +#define DBSC_DBSCHQOS120 0xE67910F0U +#define DBSC_DBSCHQOS121 0xE67910F4U +#define DBSC_DBSCHQOS122 0xE67910F8U +#define DBSC_DBSCHQOS123 0xE67910FCU +#define DBSC_DBSCHQOS130 0xE6791100U +#define DBSC_DBSCHQOS131 0xE6791104U +#define DBSC_DBSCHQOS132 0xE6791108U +#define DBSC_DBSCHQOS133 0xE679110CU +#define DBSC_DBSCHQOS140 0xE6791110U +#define DBSC_DBSCHQOS141 0xE6791114U +#define DBSC_DBSCHQOS142 0xE6791118U +#define DBSC_DBSCHQOS143 0xE679111CU +#define DBSC_DBSCHQOS150 0xE6791120U +#define DBSC_DBSCHQOS151 0xE6791124U +#define DBSC_DBSCHQOS152 0xE6791128U +#define DBSC_DBSCHQOS153 0xE679112CU +#define DBSC_DBSCTR0 0xE6791700U +#define DBSC_DBSCTR1 0xE6791708U +#define DBSC_DBSCHRW2 0xE679170CU +#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x)) +#define DBSC_SCFCTST0 0xE6791700U +#define DBSC_SCFCTST1 0xE6791708U +#define DBSC_SCFCTST2 0xE679170CU +#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab)) +#define DBSC_DBMRRDR_0 0xE6791800U +#define DBSC_DBMRRDR_1 0xE6791804U +#define DBSC_DBMRRDR_2 0xE6791808U +#define DBSC_DBMRRDR_3 0xE679180CU +#define DBSC_DBMRRDR_4 0xE6791810U +#define DBSC_DBMRRDR_5 0xE6791814U +#define DBSC_DBMRRDR_6 0xE6791818U +#define DBSC_DBMRRDR_7 0xE679181CU +#define DBSC_DBMEMSWAPCONF0 0xE6792000U + +/* CPG registers */ +#define CPG_BASE 0xE6150000U +#define CPG_FRQCRB (CPG_BASE + 0x0004U) +#define CPG_PLLECR (CPG_BASE + 0x00D0U) +#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) +#define CPG_SRCR4 (CPG_BASE + 0x00BCU) +#define CPG_PLL3CR (CPG_BASE + 0x00DCU) +#define CPG_ZB3CKCR (CPG_BASE + 0x0380U) +#define CPG_FRQCRD (CPG_BASE + 0x00E4U) +#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) +#define CPG_CPGWPR (CPG_BASE + 0x0900U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) + +#endif /* BOOT_INIT_DRAM_REGDEF_H_*/ -- cgit v1.2.3 From a8497fdb72a904162fce823af6555ccb12dbce82 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 7 Aug 2019 19:02:26 +0200 Subject: rcar_get3: drivers: ddr_b: Basic checkpatch fixes Do basic automated checkpatch fixes on the ddr_b, no functional change. Signed-off-by: Marek Vasut Change-Id: Ie401ec049a05d2c4c8044749994391adea171679 --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 169 ++++---- .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 450 ++++++++++----------- .../staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h | 8 +- 3 files changed, 318 insertions(+), 309 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index 2cce6533..c8e9ae80 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -45,30 +45,30 @@ #ifndef RCAR_LSI #define RCAR_LSI RCAR_AUTO #endif -#if(RCAR_LSI==RCAR_AUTO) +#if (RCAR_LSI == RCAR_AUTO) static uint32_t Prr_Product; static uint32_t Prr_Cut; #else -#if(RCAR_LSI==RCAR_H3) +#if (RCAR_LSI == RCAR_H3) static const uint32_t Prr_Product = PRR_PRODUCT_H3; -#elif(RCAR_LSI==RCAR_M3) +#elif(RCAR_LSI == RCAR_M3) static const uint32_t Prr_Product = PRR_PRODUCT_M3; -#elif(RCAR_LSI==RCAR_M3N) +#elif(RCAR_LSI == RCAR_M3N) static const uint32_t Prr_Product = PRR_PRODUCT_M3N; -#elif(RCAR_LSI==RCAR_H3N) +#elif(RCAR_LSI == RCAR_H3N) static const uint32_t Prr_Product = PRR_PRODUCT_H3; #endif /* RCAR_LSI */ #ifndef RCAR_LSI_CUT static uint32_t Prr_Cut; #else /* RCAR_LSI_CUT */ -#if(RCAR_LSI_CUT==RCAR_CUT_10) +#if (RCAR_LSI_CUT == RCAR_CUT_10) static const uint32_t Prr_Cut = PRR_PRODUCT_10; -#elif(RCAR_LSI_CUT==RCAR_CUT_11) +#elif(RCAR_LSI_CUT == RCAR_CUT_11) static const uint32_t Prr_Cut = PRR_PRODUCT_11; -#elif(RCAR_LSI_CUT==RCAR_CUT_20) +#elif(RCAR_LSI_CUT == RCAR_CUT_20) static const uint32_t Prr_Cut = PRR_PRODUCT_20; -#elif(RCAR_LSI_CUT==RCAR_CUT_30) +#elif(RCAR_LSI_CUT == RCAR_CUT_30) static const uint32_t Prr_Cut = PRR_PRODUCT_30; #endif /* RCAR_LSI_CUT */ #endif /* RCAR_LSI_CUT */ @@ -130,7 +130,7 @@ uint32_t ddrBackup; #define OPERATING_FREQ (400U) /* Mhz */ #define BASE_SUB_SLOT_NUM (0x6U) #define SUB_SLOT_CYCLE (0x7EU) /* 126 */ -#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ +#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) /* unit:ns */ uint32_t get_refperiod(void) { @@ -249,21 +249,21 @@ static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); static void ddr_setval_ach(uint32_t regdef, uint32_t val); static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); -static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p); -static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p); -static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size); -static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val); -static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef); +static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p); +static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p); +static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); +static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); +static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); static uint32_t ddrphy_regif_chk(void); -static inline void ddrphy_regif_idle(); +static inline void ddrphy_regif_idle(void); static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, uint16_t cyc); static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, - uint16_t * js2); + uint16_t *js2); static int16_t _f_scale_adj(int16_t ps); static void ddrtbl_load(void); static void ddr_config_sub(void); -static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz); +static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz); static void ddr_config_sub_h3v1x(void); static void ddr_config(void); static void dbsc_regset(void); @@ -297,6 +297,7 @@ struct DdrtData { uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */ }; + struct DdrtData tcal; static void pvtcode_update(void); @@ -341,10 +342,10 @@ static inline uint32_t vch_nxt(uint32_t pos) } #define foreach_vch(ch) \ -for(ch=vch_nxt(0);ch cyc) - return (uint16_t) div; + return (uint16_t)div; return cyc; } static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, - uint16_t * js2) + uint16_t *js2) { int i; @@ -1046,11 +1048,11 @@ static int16_t _f_scale_adj(int16_t ps) = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 */ tmp = - (int32_t) 4 *(int32_t) ps *(int32_t) ddr_mbps / - (int32_t) ddr_mbpsdiv; - tmp = (int32_t) tmp / (int32_t) 15625; + (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / + (int32_t)ddr_mbpsdiv; + tmp = (int32_t)tmp / (int32_t)15625; - return (int16_t) tmp; + return (int16_t)tmp; } const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = { @@ -1180,7 +1182,7 @@ static void regif_pll_wa(void) } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), - _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]); + _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]); /* protect register interface */ ddrphy_regif_idle(); @@ -1219,8 +1221,8 @@ static void regif_pll_wa(void) dsb_sev(); foreach_ech(ch) - if (((Boardcnf->phyvalid) & (1U << ch))) - while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) ; + if (((Boardcnf->phyvalid) & (1U << ch))) + while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f); dsb_sev(); } @@ -1245,7 +1247,7 @@ static void ddrtbl_load(void) if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) break; } - if (JS1_USABLEC_SPEC_HI < i) + if (i > JS1_USABLEC_SPEC_HI) js1_ind = JS1_USABLEC_SPEC_HI; else js1_ind = i; @@ -1533,7 +1535,7 @@ static void ddrtbl_load(void) FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) ***********************************************************************/ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); /*********************************************************************** @@ -1624,6 +1626,7 @@ static void ddr_config_sub(void) uint32_t tmp; uint8_t high_byte[SLICE_CNT]; const uint32_t _par_CALVL_DEVICE_MAP = 1; + foreach_vch(ch) { /*********************************************************************** BOARD SETTINGS (DQ,DM,VREF_DRIVING) @@ -1747,11 +1750,12 @@ static void ddr_config_sub(void) } } -static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz) +static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) { uint32_t slice; uint32_t tmp; uint32_t tgt; + if (ddr_csn / 2) { tgt = 3; } else { @@ -1920,7 +1924,7 @@ static void ddr_config(void) _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( + ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), _cnf_DDR_PHY_ADR_V_REGSET[ ddr_regdef_adr( @@ -1935,7 +1939,7 @@ static void ddr_config(void) _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( + ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), _cnf_DDR_PHY_ADR_G_REGSET[ ddr_regdef_adr( @@ -1952,7 +1956,7 @@ static void ddr_config(void) _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( + ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + 0x0100, _cnf_DDR_PHY_ADR_V_REGSET[ @@ -1964,7 +1968,7 @@ static void ddr_config(void) } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); /*********************************************************************** WDQDM DLY @@ -2037,7 +2041,7 @@ static void dbsc_regset_pre(void) * set all ranks as density=0(4Gb) for PHY initialization */ foreach_vch(ch) - for (csab = 0; csab < 4; csab++) + for (csab = 0; csab < 4; csab++) mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0)); if (Prr_Product == PRR_PRODUCT_M3) { @@ -2275,11 +2279,11 @@ static void dbsc_regset(void) if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { mmio_write_32(DBSC_DBSCHRW1, tmp[0] + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps - 3); + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3); } else { mmio_write_32(DBSC_DBSCHRW1, tmp[0] + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps); + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps); } /*********************************************************************** @@ -2651,6 +2655,7 @@ static uint32_t set_term_code(void) uint32_t pvtr; uint32_t pvtp; uint32_t pvtn; + term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_DATA_TERM); override = 0; @@ -2801,6 +2806,7 @@ static inline uint32_t wait_freqchgreq(uint32_t assert) uint32_t dataL; uint32_t count; uint32_t ch; + count = 100000; /* H3 Ver.1.x cannot see frqchg_req */ @@ -2833,6 +2839,7 @@ static inline void set_freqchgack(uint32_t assert) { uint32_t ch; uint32_t dataL; + if (assert) dataL = 0x0CF20000; else @@ -2845,6 +2852,7 @@ static inline void set_freqchgack(uint32_t assert) static inline void set_dfifrequency(uint32_t freq) { uint32_t ch; + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { foreach_vch(ch) mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); @@ -3404,7 +3412,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); wdqdm_le[ch][cs][slice][i] = dataL; win = - (int32_t) wdqdm_te[ch][cs][slice][i] - + (int32_t)wdqdm_te[ch][cs][slice][i] - wdqdm_le[ch][cs][slice][i]; if (min_win > win) min_win = win; @@ -3825,7 +3833,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) dataL; win = - (int32_t) rdqdm_te[ch][cs][slice + + (int32_t)rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] - rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; @@ -3881,7 +3889,7 @@ static uint32_t rdqdm_man1(void) if (ch_have_this_cs[ddr_csn] & (1U << ch)) { for (slice = 0; slice < SLICE_CNT; slice++) { if (ddr_getval_s(ch, slice, - _reg_PHY_RDLVL_STATUS_OBS) != + _reg_PHY_RDLVL_STATUS_OBS) != 0x0D00FFFF) { err = (1U << ch) | (0x10U << slice); @@ -4043,7 +4051,7 @@ static uint32_t rx_offset_cal(void) ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp); } dsb_sev(); - ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *) tmp_ach_as); + ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as); foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -4100,7 +4108,7 @@ static uint32_t rx_offset_cal_hw(void) ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); } foreach_vch(ch) - for (slice = 0; slice < SLICE_CNT; slice++) + for (slice = 0; slice < SLICE_CNT; slice++) tmp_ach_as[ch][slice] = ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]); @@ -4140,6 +4148,7 @@ static void adjust_rddqs_latency(void) uint32_t maxlatx2; uint32_t tmp; uint32_t rdlat_adjx2[SLICE_CNT]; + foreach_vch(ch) { maxlatx2 = 0; for (slice = 0; slice < SLICE_CNT; slice++) { @@ -4236,7 +4245,7 @@ int32_t rcar_dram_init(void) Judge product and cut ***********************************************************************/ #ifdef RCAR_DDR_FIXED_LSI_TYPE -#if(RCAR_LSI==RCAR_AUTO) +#if (RCAR_LSI == RCAR_AUTO) Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; #else /* RCAR_LSI */ @@ -4304,7 +4313,7 @@ int32_t rcar_dram_init(void) } foreach_ech(ch) - for (cs = 0; cs < CS_CNT; cs++) + for (cs = 0; cs < CS_CNT; cs++) ddr_density[ch][cs] = 0xff; foreach_vch(ch) { @@ -4340,9 +4349,8 @@ int32_t rcar_dram_init(void) ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); - ddr_mul = - CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, - brd_clkdiv * (brd_clkdiva + 1)); + ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, + brd_clkdiv * (brd_clkdiva + 1)); /*********************************************************************** Adjust tccd @@ -4487,6 +4495,7 @@ void pvtcode_update(void) void pvtcode_update2(void) { uint32_t ch; + foreach_vch(ch) { reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), tcal.init_cal[ch] | 0x00020000); @@ -4522,27 +4531,27 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) dataL = mmio_read_32(THS1_TEMP); if (dataL < 2800) { tcal.init_temp = - (143 * (int32_t) dataL - 359000) / 1000; + (143 * (int32_t)dataL - 359000) / 1000; } else { tcal.init_temp = - (121 * (int32_t) dataL - 296300) / 1000; + (121 * (int32_t)dataL - 296300) / 1000; } foreach_vch(ch) { pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F; pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F; - if ((int32_t) pvtp > + if ((int32_t)pvtp > ((tcal.init_temp * 29 - 3625) / 1000)) pvtp = - (int32_t) pvtp + + (int32_t)pvtp + ((3625 - tcal.init_temp * 29) / 1000); else pvtp = 0; - if ((int32_t) pvtn > + if ((int32_t)pvtn > ((tcal.init_temp * 54 - 6750) / 1000)) pvtn = - (int32_t) pvtn + + (int32_t)pvtn + ((6750 - tcal.init_temp * 54) / 1000); else pvtn = 0; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index aaa5f008..58c9a7a4 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -115,7 +115,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } + } } }, /* boardcnf[1] RENESAS KRIEK board with M3-W/SoC */ @@ -126,8 +126,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00345201, 0x3201, @@ -147,7 +147,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00302154, 0x2310, @@ -166,8 +166,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) */ { @@ -177,8 +177,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { -320, 0x300, 0x0a0, - { - { + { + { {0x02, 0xff}, 0x00543210, 0x3210, @@ -198,7 +198,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x3102, @@ -218,7 +218,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x0213, @@ -238,7 +238,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x0213, @@ -257,8 +257,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) */ { @@ -268,8 +268,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x0300, 0x00a0, - { - { + { + { {0x02, 0xFF}, 0x00543210U, 0x3201, @@ -289,7 +289,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xFF}, 0x00543210, 0x2310, @@ -308,8 +308,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC */ { @@ -319,8 +319,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { -320, 0x300, 0x0a0, - { - { + { + { {0x02, 0xff}, 0x00315024, 0x3120, @@ -340,7 +340,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00025143, 0x3210, @@ -360,7 +360,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00523104, 0x2301, @@ -380,7 +380,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00153402, 0x2031, @@ -399,8 +399,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC */ { @@ -410,8 +410,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0xff}, 0x00345201, 0x3201, @@ -431,7 +431,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00302154, 0x2310, @@ -450,8 +450,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) */ { @@ -461,8 +461,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { -320, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00543210, 0x3210, @@ -482,7 +482,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00543210, 0x3102, @@ -502,7 +502,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00543210, 0x0213, @@ -522,7 +522,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00543210, 0x0213, @@ -541,8 +541,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[7] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 1rank) */ { @@ -552,8 +552,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0xff}, 0x00543210, 0x2310, @@ -573,7 +573,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00105432, 0x3210, @@ -593,7 +593,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x2301, @@ -613,7 +613,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x2301, @@ -632,8 +632,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[8] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 2rank) */ { @@ -647,8 +647,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00543210, 0x2310, @@ -669,7 +669,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2)) - { + { {0x02, 0x02}, 0x00543210, 0x2301, @@ -690,7 +690,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #else - { + { {0x02, 0x02}, 0x00105432, 0x3210, @@ -711,7 +711,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #endif - { + { {0x02, 0x02}, 0x00543210, 0x2301, @@ -731,7 +731,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00543210, 0x2301, @@ -750,8 +750,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC */ { @@ -761,8 +761,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0xff}, 0x00543210, 0x3210, @@ -782,7 +782,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00543210, 0x2301, @@ -802,7 +802,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00452103, 0x3210, @@ -822,7 +822,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0xff}, 0x00520413, 0x2301, @@ -841,8 +841,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC */ { @@ -852,8 +852,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00345201, 0x3201, @@ -872,8 +872,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) */ { @@ -883,8 +883,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { #if (RCAR_DRAM_LPDDR4_MEMCONF == 2) {0x04, 0x04}, #else @@ -907,8 +907,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[12] RENESAS CONDOR board with V3H/SoC */ { @@ -918,8 +918,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00501342, 0x3201, @@ -938,8 +938,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[13] RENESAS KRIEK board with PM3/SoC */ { @@ -949,8 +949,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { -320, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00345201, 0x3201, @@ -970,7 +970,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00302154, 0x2310, @@ -990,7 +990,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00302154, 0x2310, @@ -1010,7 +1010,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0xff, 0xff}, 0, 0, @@ -1029,8 +1029,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[14] SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) */ { @@ -1044,8 +1044,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x04, 0xff}, 0x00543210, 0x2310, @@ -1066,7 +1066,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2)) - { + { {0x04, 0xff}, 0x00543210, 0x2301, @@ -1087,7 +1087,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #else - { + { {0x04, 0xff}, 0x00105432, 0x3210, @@ -1108,7 +1108,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0} }, #endif - { + { {0x04, 0xff}, 0x00543210, 0x2301, @@ -1128,7 +1128,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x04, 0xff}, 0x00543210, 0x2301, @@ -1147,8 +1147,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[15] RENESAS KRIEK board with H3N */ { @@ -1158,8 +1158,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x300, 0x0a0, - { - { + { + { {0x02, 0x02}, 0x00345201, 0x3201, @@ -1179,7 +1179,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00302154, 0x2310, @@ -1199,7 +1199,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x02, 0x02}, 0x00302154, 0x2310, @@ -1219,7 +1219,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0xff, 0xff}, 0, 0, @@ -1238,8 +1238,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */ { @@ -1249,8 +1249,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x0300, 0x00a0, - { - { + { + { {0x04, 0x04}, 0x520314FFFF523041, 0x3201, @@ -1270,7 +1270,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x04, 0x04}, 0x314250FFFF312405, 0x2310, @@ -1289,8 +1289,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */ { @@ -1300,8 +1300,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x0300, 0x00a0, - { - { + { + { {0x04, 0x04}, 0x520314FFFF523041, 0x3201, @@ -1320,8 +1320,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */ { @@ -1331,8 +1331,8 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0x0300, 0x00a0, - { - { + { + { {0x04, 0x04}, 0x00543210, 0x3201, @@ -1352,7 +1352,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x04, 0x04}, 0x00543210, 0x2310, @@ -1371,19 +1371,19 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { {0x04, 0xff}, 0x00543210, 0x3201, @@ -1403,7 +1403,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }, - { + { {0x04, 0xff}, 0x00543210, 0x2310, @@ -1422,114 +1422,114 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - } - } + } + } }, /* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { - {0x04, 0x04}, - 0x00345201, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0x04}, + 0x00345201, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { {0x04, 0x04}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - }, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, /* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */ - { - 0x03, - 0x01, - 0x02c0, - 0, - 0x0300, - 0x00a0, - { - { - {0x04, 0xff}, - 0x00345201, - 0x3201, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - }, - { - {0x04, 0xff}, - 0x00302154, - 0x2310, - {0x01672543, 0x45361207, 0x45632107, 0x60715234}, - {0x08, 0x08, 0x08, 0x08}, - WDQLVL_PAT, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0} - } - } - } + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0xff}, + 0x00345201, + 0x3201, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x04, 0xff}, + 0x00302154, + 0x2310, + {0x01672543, 0x45361207, 0x45632107, 0x60715234}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + } }; -void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div) +void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) { uint32_t md; @@ -1560,7 +1560,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div) (void)brd; } -void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div) +void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) { uint32_t md; @@ -1616,13 +1616,13 @@ static const uint32_t TermcodeBySample[20][3] = { /* * SAMPLE board detect function */ -#define PFC_PMMR 0xE6060000U +#define PFC_PMMR 0xE6060000U #define PFC_PUEN5 0xE6060414U #define PFC_PUEN6 0xE6060418U #define PFC_PUD5 0xE6060454U #define PFC_PUD6 0xE6060458U #define GPIO_INDT5 0xE605500CU -#define GPIO_GPSR6 0xE6060118U +#define GPIO_GPSR6 0xE6060118U #if (RCAR_GEN3_ULCB == 0) static void pfc_write_and_poll(uint32_t a, uint32_t v) @@ -1630,7 +1630,7 @@ static void pfc_write_and_poll(uint32_t a, uint32_t v) mmio_write_32(PFC_PMMR, ~v); v = ~mmio_read_32(PFC_PMMR); mmio_write_32(a, v); - while (v != mmio_read_32(a)) ; + while (v != mmio_read_32(a)); dsb_sev(); } #endif @@ -1699,7 +1699,7 @@ static uint32_t opencheck_SSI_WS6(void) static uint32_t _board_judge(void) { uint32_t brd; -#if (RCAR_GEN3_ULCB==1) +#if (RCAR_GEN3_ULCB == 1) /* Starter Kit */ if (Prr_Product == PRR_PRODUCT_H3) { if (Prr_Cut <= PRR_PRODUCT_11) { @@ -1725,7 +1725,7 @@ static uint32_t _board_judge(void) usb2_ovc_open = opencheck_SSI_WS6(); - /* RENESAS Eva-borad */ + /* RENESAS Eva-board */ brd = 99; if (Prr_Product == PRR_PRODUCT_V3H) { /* RENESAS Condor board */ @@ -1738,7 +1738,7 @@ static uint32_t _board_judge(void) /* RENESAS Kriek board with M3-W */ brd = 1; } else if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut<=PRR_PRODUCT_11)) { + && (Prr_Cut <= PRR_PRODUCT_11)) { /* RENESAS Kriek board with PM3 */ brd = 13; } else if ((Prr_Product == PRR_PRODUCT_H3) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h index bad1de90..7f27b398 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h @@ -1178,9 +1178,9 @@ #define _reg_PI_TSDO_F1 0x00000493U #define _reg_PI_TSDO_F2 0x00000494U -#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff) -#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff) -#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff) +#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffff) +#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xff) +#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xff) static const uint32_t DDR_REGDEF_TBL[4][1173] = { { @@ -5882,5 +5882,5 @@ static const uint32_t DDR_REGDEF_TBL[4][1173] = { /*0492*/ 0x0808031dU, /*0493*/ 0x1008031dU, /*0494*/ 0x1808031dU, - } + } }; -- cgit v1.2.3 From fcd81d6f93c3f187ed29afae9c55a120d6225d94 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 7 Aug 2019 19:17:42 +0200 Subject: rcar_gen3: drivers: ddr_b: Clean up camel case Signed-off-by: Marek Vasut Change-Id: Ifda28578f326b1d4518560384d50ae98806db26e --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 1194 ++++++++++---------- .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 38 +- 2 files changed, 616 insertions(+), 616 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index c8e9ae80..244caf6e 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -31,10 +31,10 @@ #ifdef RCAR_DDR_FIXED_LSI_TYPE #ifndef RCAR_AUTO #define RCAR_AUTO 99 -#define RCAR_H3 0 -#define RCAR_M3 1 +#define RCAR_H3 0 +#define RCAR_M3 1 #define RCAR_M3N 2 -#define RCAR_E3 3 /* NON */ +#define RCAR_E3 3 /* NON */ #define RCAR_H3N 4 #define RCAR_CUT_10 0 @@ -45,42 +45,41 @@ #ifndef RCAR_LSI #define RCAR_LSI RCAR_AUTO #endif + #if (RCAR_LSI == RCAR_AUTO) -static uint32_t Prr_Product; -static uint32_t Prr_Cut; +static uint32_t prr_product; +static uint32_t prr_cut; #else #if (RCAR_LSI == RCAR_H3) -static const uint32_t Prr_Product = PRR_PRODUCT_H3; +static const uint32_t prr_product = PRR_PRODUCT_H3; #elif(RCAR_LSI == RCAR_M3) -static const uint32_t Prr_Product = PRR_PRODUCT_M3; +static const uint32_t prr_product = PRR_PRODUCT_M3; #elif(RCAR_LSI == RCAR_M3N) -static const uint32_t Prr_Product = PRR_PRODUCT_M3N; +static const uint32_t prr_product = PRR_PRODUCT_M3N; #elif(RCAR_LSI == RCAR_H3N) -static const uint32_t Prr_Product = PRR_PRODUCT_H3; +static const uint32_t prr_product = PRR_PRODUCT_H3; #endif /* RCAR_LSI */ #ifndef RCAR_LSI_CUT -static uint32_t Prr_Cut; +static uint32_t prr_cut; #else /* RCAR_LSI_CUT */ #if (RCAR_LSI_CUT == RCAR_CUT_10) -static const uint32_t Prr_Cut = PRR_PRODUCT_10; +static const uint32_t prr_cut = PRR_PRODUCT_10; #elif(RCAR_LSI_CUT == RCAR_CUT_11) -static const uint32_t Prr_Cut = PRR_PRODUCT_11; +static const uint32_t prr_cut = PRR_PRODUCT_11; #elif(RCAR_LSI_CUT == RCAR_CUT_20) -static const uint32_t Prr_Cut = PRR_PRODUCT_20; +static const uint32_t prr_cut = PRR_PRODUCT_20; #elif(RCAR_LSI_CUT == RCAR_CUT_30) -static const uint32_t Prr_Cut = PRR_PRODUCT_30; +static const uint32_t prr_cut = PRR_PRODUCT_30; #endif /* RCAR_LSI_CUT */ #endif /* RCAR_LSI_CUT */ #endif /* RCAR_AUTO_NON */ #else /* RCAR_DDR_FIXED_LSI_TYPE */ -static uint32_t Prr_Product; -static uint32_t Prr_Cut; +static uint32_t prr_product; +static uint32_t prr_cut; #endif /* RCAR_DDR_FIXED_LSI_TYPE */ -char *pRCAR_DDR_VERSION; -uint32_t _cnf_BOARDTYPE; -static const uint32_t *pDDR_REGDEF_TBL; +static const uint32_t *p_ddr_regdef_tbl; static uint32_t brd_clk; static uint32_t brd_clkdiv; static uint32_t brd_clkdiva; @@ -88,7 +87,7 @@ static uint32_t ddr_mbps; static uint32_t ddr_mbpsdiv; static uint32_t ddr_tccd; static uint32_t ddr_phycaslice; -static const struct _boardcnf *Boardcnf; +static const struct _boardcnf *board_cnf; static uint32_t ddr_phyvalid; static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; static uint32_t ch_have_this_cs[CS_CNT] __attribute__ ((aligned(64))); @@ -119,10 +118,10 @@ static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX]; static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; -static uint32_t Pll3Mode; +static uint32_t pll3_mode; static uint32_t loop_max; #ifdef DDR_BACKUPMODE -uint32_t ddrBackup; +uint32_t ddr_backup; /* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */ #endif @@ -292,13 +291,13 @@ static uint32_t rx_offset_cal_hw(void); static void adjust_rddqs_latency(void); static void adjust_wpath_latency(void); -struct DdrtData { +struct ddrt_data { int32_t init_temp; /* Initial Temperature (do) */ uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */ }; -struct DdrtData tcal; +static struct ddrt_data tcal; static void pvtcode_update(void); static void pvtcode_update2(void); @@ -363,129 +362,129 @@ static void cpg_write_32(uint32_t a, uint32_t v) static void pll3_control(uint32_t high) { - uint32_t dataL, dataDIV, dataMUL, tmpDIV; + uint32_t data_l, data_div, data_mul, tmp_div; if (high) { - tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) / + tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr_mul) / 2; - dataMUL = (((ddr_mul * tmpDIV) - 1) << 24) | + data_mul = (((ddr_mul * tmp_div) - 1) << 24) | (brd_clkdiva << 7); - Pll3Mode = 1; + pll3_mode = 1; loop_max = 2; } else { - tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) / + tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr0800_mul) / 2; - dataMUL = (((ddr0800_mul * tmpDIV) - 1) << 24) | + data_mul = (((ddr0800_mul * tmp_div) - 1) << 24) | (brd_clkdiva << 7); - Pll3Mode = 0; + pll3_mode = 0; loop_max = 8; } - switch (tmpDIV) { + switch (tmp_div) { case 1: - dataDIV = 0; + data_div = 0; break; case 2: case 3: case 4: - dataDIV = tmpDIV; + data_div = tmp_div; break; default: - dataDIV = 6; - dataMUL = (dataMUL * tmpDIV) / 3; + data_div = 6; + data_mul = (data_mul * tmp_div) / 3; break; } - dataMUL = dataMUL | (brd_clkdiva << 7); + data_mul = data_mul | (brd_clkdiva << 7); /* PLL3 disable */ - dataL = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; - cpg_write_32(CPG_PLLECR, dataL); + data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; + cpg_write_32(CPG_PLLECR, data_l); dsb_sev(); - if ((Prr_Product == PRR_PRODUCT_M3) || - ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_20))) { + if ((prr_product == PRR_PRODUCT_M3) || + ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) { /* PLL3 DIV resetting(Lowest value:3) */ - dataL = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); + data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, data_l); dsb_sev(); /* zb3 clk stop */ - dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); - cpg_write_32(CPG_ZB3CKCR, dataL); + data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); + cpg_write_32(CPG_ZB3CKCR, data_l); dsb_sev(); /* PLL3 enable */ - dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); - cpg_write_32(CPG_PLLECR, dataL); + data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); + cpg_write_32(CPG_PLLECR, data_l); dsb_sev(); do { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); dsb_sev(); /* PLL3 DIV resetting (Highest value:0) */ - dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); + data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, data_l); dsb_sev(); /* DIV SET KICK */ - dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, dataL); + data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, data_l); dsb_sev(); /* PLL3 multiplie set */ - cpg_write_32(CPG_PLL3CR, dataMUL); + cpg_write_32(CPG_PLL3CR, data_mul); dsb_sev(); do { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); dsb_sev(); /* PLL3 DIV resetting(Target value) */ - dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); + data_l = (data_div << 16) | data_div | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, data_l); dsb_sev(); /* DIV SET KICK */ - dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, dataL); + data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, data_l); dsb_sev(); do { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); dsb_sev(); /* zb3 clk start */ - dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); - cpg_write_32(CPG_ZB3CKCR, dataL); + data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); + cpg_write_32(CPG_ZB3CKCR, data_l); dsb_sev(); } else { /* H3Ver.3.0/M3N/V3H */ /* PLL3 multiplie set */ - cpg_write_32(CPG_PLL3CR, dataMUL); + cpg_write_32(CPG_PLL3CR, data_mul); dsb_sev(); /* PLL3 DIV set(Target value) */ - dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); + data_l = (data_div << 16) | data_div | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, data_l); /* DIV SET KICK */ - dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, dataL); + data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, data_l); dsb_sev(); /* PLL3 enable */ - dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); - cpg_write_32(CPG_PLLECR, dataL); + data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); + cpg_write_32(CPG_PLLECR, data_l); dsb_sev(); do { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + data_l = mmio_read_32(CPG_PLLECR); + } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0); dsb_sev(); } } @@ -503,15 +502,15 @@ static inline void dsb_sev(void) ******************************************************************************/ static void wait_dbcmd(void) { - uint32_t dataL; + uint32_t data_l; /* dummy read */ - dataL = mmio_read_32(DBSC_DBCMD); + data_l = mmio_read_32(DBSC_DBCMD); dsb_sev(); while (1) { /* wait DBCMD 1=busy, 0=ready */ - dataL = mmio_read_32(DBSC_DBWAIT); + data_l = mmio_read_32(DBSC_DBWAIT); dsb_sev(); - if ((dataL & 0x00000001) == 0x00) + if ((data_l & 0x00000001) == 0x00) break; } } @@ -533,8 +532,8 @@ static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) uint32_t loop; val = 0; - if ((Prr_Product != PRR_PRODUCT_M3N) - && (Prr_Product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) + && (prr_product != PRR_PRODUCT_V3H)) { mmio_write_32(DBSC_DBPDRGA(phyno), regadd); dsb_sev(); @@ -580,8 +579,8 @@ static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) uint32_t val; uint32_t loop; - if ((Prr_Product != PRR_PRODUCT_M3N) - && (Prr_Product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) + && (prr_product != PRR_PRODUCT_V3H)) { mmio_write_32(DBSC_DBPDRGA(phyno), regadd); dsb_sev(); for (loop = 0; loop < loop_max; loop++) { @@ -629,8 +628,8 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) uint32_t val; uint32_t loop; - if ((Prr_Product != PRR_PRODUCT_M3N) - && (Prr_Product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) + && (prr_product != PRR_PRODUCT_V3H)) { foreach_vch(ch) { mmio_write_32(DBSC_DBPDRGA(ch), regadd); dsb_sev(); @@ -668,17 +667,17 @@ static inline void ddrphy_regif_idle(void) ******************************************************************************/ static inline uint32_t ddr_regdef(uint32_t _regdef) { - return pDDR_REGDEF_TBL[_regdef]; + return p_ddr_regdef_tbl[_regdef]; } static inline uint32_t ddr_regdef_adr(uint32_t _regdef) { - return DDR_REGDEF_ADR(pDDR_REGDEF_TBL[_regdef]); + return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]); } static inline uint32_t ddr_regdef_lsb(uint32_t _regdef) { - return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]); + return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]); } static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, @@ -864,8 +863,8 @@ static uint32_t ddrphy_regif_chk(void) uint32_t err; uint32_t PI_VERSION_CODE; - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3)) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3)) { PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ } else { PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ @@ -885,11 +884,11 @@ static uint32_t ddrphy_regif_chk(void) ******************************************************************************/ struct _jedec_spec1 { uint16_t fx3; - uint8_t RLwoDBI; - uint8_t RLwDBI; + uint8_t rlwodbi; + uint8_t rlwdbi; uint8_t WL; - uint8_t nWR; - uint8_t nRTP; + uint8_t nwr; + uint8_t nrtp; uint8_t MR1; uint8_t MR2; }; @@ -915,33 +914,33 @@ struct _jedec_spec2 { uint16_t cyc; }; -#define JS2_tSR 0 -#define JS2_tXP 1 -#define JS2_tRTP 2 -#define JS2_tRCD 3 -#define JS2_tRPpb 4 -#define JS2_tRPab 5 -#define JS2_tRAS 6 -#define JS2_tWR 7 -#define JS2_tWTR 8 -#define JS2_tRRD 9 -#define JS2_tPPD 10 -#define JS2_tFAW 11 -#define JS2_tDQSCK 12 -#define JS2_tCKEHCMD 13 -#define JS2_tCKELCMD 14 -#define JS2_tCKELPD 15 -#define JS2_tMRR 16 -#define JS2_tMRW 17 -#define JS2_tMRD 18 -#define JS2_tZQCALns 19 -#define JS2_tZQLAT 20 -#define JS2_tIEdly 21 +#define js2_tsr 0 +#define js2_txp 1 +#define js2_trtp 2 +#define js2_trcd 3 +#define js2_trppb 4 +#define js2_trpab 5 +#define js2_tras 6 +#define js2_twr 7 +#define js2_twtr 8 +#define js2_trrd 9 +#define js2_tppd 10 +#define js2_tfaw 11 +#define js2_tdqsck 12 +#define js2_tckehcmd 13 +#define js2_tckelcmd 14 +#define js2_tckelpd 15 +#define js2_tmrr 16 +#define js2_tmrw 17 +#define js2_tmrd 18 +#define js2_tzqcalns 19 +#define js2_tzqlat 20 +#define js2_tiedly 21 #define JS2_TBLCNT 22 -#define JS2_tRCpb (JS2_TBLCNT) -#define JS2_tRCab (JS2_TBLCNT + 1) -#define JS2_tRFCab (JS2_TBLCNT + 2) +#define js2_trcpb (JS2_TBLCNT) +#define js2_trcab (JS2_TBLCNT + 1) +#define js2_trfcab (JS2_TBLCNT + 2) #define JS2_CNT (JS2_TBLCNT + 3) #ifndef JS2_DERATE @@ -997,7 +996,7 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { } }; -const uint16_t jedec_spec2_tRFC_ab[7] = { +const uint16_t jedec_spec2_trfc_ab[7] = { /* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */ 130, 180, 180, 280, 280, 560, 560 }; @@ -1034,8 +1033,8 @@ static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, jedec_spec2[JS2_DERATE][i].cyc); } - js2[JS2_tRCpb] = js2[JS2_tRAS] + js2[JS2_tRPpb]; - js2[JS2_tRCab] = js2[JS2_tRAS] + js2[JS2_tRPab]; + js2[js2_trcpb] = js2[js2_tras] + js2[js2_trppb]; + js2[js2_trcab] = js2[js2_tras] + js2[js2_trpab]; } /* scaler for DELAY value */ @@ -1055,7 +1054,7 @@ static int16_t _f_scale_adj(int16_t ps) return (int16_t)tmp; } -const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = { +static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR1_DATA_F0_0, _reg_PI_MR1_DATA_F0_1, @@ -1068,7 +1067,7 @@ const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = { _reg_PI_MR1_DATA_F1_3} }; -const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = { +static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR2_DATA_F0_0, _reg_PI_MR2_DATA_F0_1, @@ -1081,7 +1080,7 @@ const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = { _reg_PI_MR2_DATA_F1_3} }; -const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = { +static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR3_DATA_F0_0, _reg_PI_MR3_DATA_F0_1, @@ -1094,7 +1093,7 @@ const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = { _reg_PI_MR3_DATA_F1_3} }; -const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = { +const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR11_DATA_F0_0, _reg_PI_MR11_DATA_F0_1, @@ -1107,7 +1106,7 @@ const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = { _reg_PI_MR11_DATA_F1_3} }; -const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = { +const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR12_DATA_F0_0, _reg_PI_MR12_DATA_F0_1, @@ -1120,7 +1119,7 @@ const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = { _reg_PI_MR12_DATA_F1_3} }; -const uint32_t _reg_PI_MR14_DATA_Fx_CSx[2][CSAB_CNT] = { +const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = { { _reg_PI_MR14_DATA_F0_0, _reg_PI_MR14_DATA_F0_1, @@ -1140,7 +1139,7 @@ static void regif_pll_wa(void) { uint32_t ch; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { // PLL setting for PHY : H3 Ver.1.x reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), (0x0064U << @@ -1188,7 +1187,7 @@ static void regif_pll_wa(void) ddrphy_regif_idle(); pll3_control(0); - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { /* non */ } else { reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN), @@ -1221,7 +1220,7 @@ static void regif_pll_wa(void) dsb_sev(); foreach_ech(ch) - if (((Boardcnf->phyvalid) & (1U << ch))) + if (((board_cnf->phyvalid) & (1U << ch))) while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f); dsb_sev(); } @@ -1235,7 +1234,7 @@ static void ddrtbl_load(void) uint32_t slice; uint32_t csab; uint32_t adr; - uint32_t dataL; + uint32_t data_l; uint32_t tmp[3]; uint16_t dataS; @@ -1252,10 +1251,10 @@ static void ddrtbl_load(void) else js1_ind = i; - if (Boardcnf->dbi_en) - RL = js1[js1_ind].RLwDBI; + if (board_cnf->dbi_en) + RL = js1[js1_ind].rlwdbi; else - RL = js1[js1_ind].RLwoDBI; + RL = js1[js1_ind].rlwodbi; WL = js1[js1_ind].WL; @@ -1265,8 +1264,8 @@ static void ddrtbl_load(void) /*********************************************************************** PREPARE TBL ***********************************************************************/ - if (Prr_Product == PRR_PRODUCT_H3) { - if (Prr_Cut <= PRR_PRODUCT_11) { + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { /* H3 Ver.1.x */ _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, DDR_PHY_SLICE_REGSET_H3, @@ -1342,7 +1341,7 @@ static void ddrtbl_load(void) DDR_PHY_ADR_I_NUM = 0; } - } else if (Prr_Product == PRR_PRODUCT_M3) { + } else if (prr_product == PRR_PRODUCT_M3) { /* M3-W */ _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3); @@ -1408,7 +1407,7 @@ static void ddrtbl_load(void) /*********************************************************************** PLL CODE CHANGE ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, 0x1142); ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, @@ -1418,7 +1417,7 @@ static void ddrtbl_load(void) /*********************************************************************** on fly gate adjust ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10)) { + if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) { ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_ON_FLY_GATE_ADJUST_EN, 0x00); } @@ -1430,7 +1429,7 @@ static void ddrtbl_load(void) for (i = 0; i < 2; i++) { for (csab = 0; csab < CSAB_CNT; csab++) { ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR11_DATA_Fx_CSx[i][csab], + reg_pi_mr11_data_fx_csx[i][csab], _def_LPDDR4_ODT); } } @@ -1440,43 +1439,43 @@ static void ddrtbl_load(void) for (i = 0; i < 2; i++) { for (csab = 0; csab < CSAB_CNT; csab++) { ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR12_DATA_Fx_CSx[i][csab], + reg_pi_mr12_data_fx_csx[i][csab], _def_LPDDR4_VREFCA); } } #endif /* _def_LPDDR4_VREFCA */ - if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { - js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; - if (js2[JS2_tIEdly] > (RL)) - js2[JS2_tIEdly] = RL; - } else if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_11)) { - js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; - } else if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { - js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); - } - - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { - if ((js2[JS2_tIEdly]) >= 0x1e) + if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { + js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; + if (js2[js2_tiedly] > (RL)) + js2[js2_tiedly] = RL; + } else if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_11)) { + js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; + } else if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { + js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); + } + + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { + if ((js2[js2_tiedly]) >= 0x1e) dataS = 0x1e; else - dataS = js2[JS2_tIEdly]; + dataS = js2[js2_tiedly]; } else { - if ((js2[JS2_tIEdly]) >= 0x0e) + if ((js2[js2_tiedly]) >= 0x0e) dataS = 0x0e; else - dataS = js2[JS2_tIEdly]; + dataS = js2[js2_tiedly]; } ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, (dataS - 2)); - if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_OE_DLY, dataS); } @@ -1484,14 +1483,14 @@ static void ddrtbl_load(void) if (ddrtbl_getval (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) { - dataL = WL - 1; + data_l = WL - 1; } else { - dataL = WL; + data_l = WL; } - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, dataL - 2); - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, dataL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l); - if (Boardcnf->dbi_en) { + if (board_cnf->dbi_en) { ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 0x01); ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, @@ -1505,27 +1504,27 @@ static void ddrtbl_load(void) tmp[0] = js1[js1_ind].MR1; tmp[1] = js1[js1_ind].MR2; - dataL = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); - if (Boardcnf->dbi_en) - tmp[2] = dataL | 0xc0; + data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); + if (board_cnf->dbi_en) + tmp[2] = data_l | 0xc0; else - tmp[2] = dataL & (~0xc0); + tmp[2] = data_l & (~0xc0); for (i = 0; i < 2; i++) { for (csab = 0; csab < CSAB_CNT; csab++) { ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR1_DATA_Fx_CSx[i][csab], tmp[0]); + reg_pi_mr1_data_fx_csx[i][csab], tmp[0]); ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR2_DATA_Fx_CSx[i][csab], tmp[1]); + reg_pi_mr2_data_fx_csx[i][csab], tmp[1]); ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR3_DATA_Fx_CSx[i][csab], tmp[2]); + reg_pi_mr3_data_fx_csx[i][csab], tmp[2]); } } /*********************************************************************** DDRPHY INT START ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { /* non */ } else { regif_pll_wa(); @@ -1559,9 +1558,9 @@ static void ddrtbl_load(void) reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); } - if (((Prr_Product == PRR_PRODUCT_M3) - || (Prr_Product == PRR_PRODUCT_M3N)) && - ((0x00ffffff & (uint32_t)((Boardcnf->ch[0].ca_swap) >> 40)) + if (((prr_product == PRR_PRODUCT_M3) + || (prr_product == PRR_PRODUCT_M3N)) && + ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40)) != 0x00)) { adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { @@ -1576,7 +1575,7 @@ static void ddrtbl_load(void) for (i = 0; i < 2; i++) { for (csab = 0; csab < CSAB_CNT; csab++) { ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR11_DATA_Fx_CSx[i][csab], + reg_pi_mr11_data_fx_csx[i][csab], 0x66); } } @@ -1622,7 +1621,7 @@ static void ddr_config_sub(void) { uint32_t i; uint32_t ch, slice; - uint32_t dataL; + uint32_t data_l; uint32_t tmp; uint8_t high_byte[SLICE_CNT]; const uint32_t _par_CALVL_DEVICE_MAP = 1; @@ -1633,11 +1632,11 @@ static void ddr_config_sub(void) ***********************************************************************/ for (slice = 0; slice < SLICE_CNT; slice++) { high_byte[slice] = - (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) % 2; + (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2; ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, - Boardcnf->ch[ch].dq_swap[slice]); + board_cnf->ch[ch].dq_swap[slice]); ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, - Boardcnf->ch[ch].dm_swap[slice]); + board_cnf->ch[ch].dm_swap[slice]); if (high_byte[slice]) { /* HIGHER 16 BYTE */ ddr_setval_s(ch, slice, @@ -1654,56 +1653,56 @@ static void ddr_config_sub(void) /*********************************************************************** BOARD SETTINGS (CA,ADDR_SEL) ***********************************************************************/ - dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) | + data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) | 0x00888888; /* --- ADR_CALVL_SWIZZLE --- */ - if (Prr_Product == PRR_PRODUCT_M3) { - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); + if (prr_product == PRR_PRODUCT_M3) { + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); } else { - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); } /* --- ADR_ADDR_SEL --- */ - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_11)) { - dataL = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap; + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_11)) { + data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; } else { - dataL = 0; - tmp = Boardcnf->ch[ch].ca_swap; + data_l = 0; + tmp = board_cnf->ch[ch].ca_swap; for (i = 0; i < 6; i++) { - dataL |= ((tmp & 0x0f) << (i * 5)); + data_l |= ((tmp & 0x0f) << (i * 5)); tmp = tmp >> 4; } } - ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL); + ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l); if (ddr_phycaslice == 1) { /* ----------- adr slice2 swap ----------- */ - tmp = (uint32_t)((Boardcnf->ch[ch].ca_swap) >> 40); - dataL = (tmp & 0x00ffffff) | 0x00888888; + tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40); + data_l = (tmp & 0x00ffffff) | 0x00888888; /* --- ADR_CALVL_SWIZZLE --- */ - if (Prr_Product == PRR_PRODUCT_M3) { - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); + if (prr_product == PRR_PRODUCT_M3) { + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL); + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); } else { - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL); + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP, @@ -1711,42 +1710,42 @@ static void ddr_config_sub(void) } /* --- ADR_ADDR_SEL --- */ - dataL = 0; + data_l = 0; for (i = 0; i < 6; i++) { - dataL |= ((tmp & 0x0f) << (i * 5)); + data_l |= ((tmp & 0x0f) << (i * 5)); tmp = tmp >> 4; } - ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, dataL); + ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l); } /*********************************************************************** BOARD SETTINGS (BYTE_ORDER_SEL) ***********************************************************************/ - if (Prr_Product == PRR_PRODUCT_M3) { + if (prr_product == PRR_PRODUCT_M3) { /* --- DATA_BYTE_SWAP --- */ - dataL = 0; - tmp = Boardcnf->ch[ch].dqs_swap; + data_l = 0; + tmp = board_cnf->ch[ch].dqs_swap; for (i = 0; i < 4; i++) { - dataL |= ((tmp & 0x03) << (i * 2)); + data_l |= ((tmp & 0x03) << (i * 2)); tmp = tmp >> 4; } } else { /* --- DATA_BYTE_SWAP --- */ - dataL = Boardcnf->ch[ch].dqs_swap; + data_l = board_cnf->ch[ch].dqs_swap; ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01); ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, - (dataL) & 0x0f); + (data_l) & 0x0f); ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, - (dataL >> 4 * 1) & 0x0f); + (data_l >> 4 * 1) & 0x0f); ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2, - (dataL >> 4 * 2) & 0x0f); + (data_l >> 4 * 2) & 0x0f); ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, - (dataL >> 4 * 3) & 0x0f); + (data_l >> 4 * 3) & 0x0f); ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00); } - ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, dataL); + ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l); } } @@ -1763,11 +1762,11 @@ static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) } for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (tgt == tmp) break; } - tmp = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap; + tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; if (slice % 2) tmp |= 0x00888888; *p_swz = tmp; @@ -1776,7 +1775,7 @@ static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) static void ddr_config_sub_h3v1x(void) { uint32_t ch, slice; - uint32_t dataL; + uint32_t data_l; uint32_t tmp; uint8_t high_byte[SLICE_CNT]; uint32_t ca_swizzle; @@ -1798,14 +1797,14 @@ static void ddr_config_sub_h3v1x(void) ***********************************************************************/ csmap = 0; for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; high_byte[slice] = tmp % 2; if (tmp == 1 && (slice >= 2)) csmap |= 0x05; if (tmp == 3 && (slice >= 2)) csmap |= 0x50; ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING, - Boardcnf->ch[ch].dq_swap[slice]); + board_cnf->ch[ch].dq_swap[slice]); if (high_byte[slice]) { /* HIGHER 16 BYTE */ ddr_setval_s(ch, slice, @@ -1821,7 +1820,7 @@ static void ddr_config_sub_h3v1x(void) /*********************************************************************** BOARD SETTINGS (CA,ADDR_SEL) ***********************************************************************/ - ca = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap; + ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); @@ -1844,7 +1843,7 @@ static void ddr_config_sub_h3v1x(void) else o_inv = o_mr15; - tmp = Boardcnf->ch[ch].dq_swap[slice]; + tmp = board_cnf->ch[ch].dq_swap[slice]; inv = 0; j = 0; for (bit_soc = 0; bit_soc < 8; bit_soc++) { @@ -1853,13 +1852,13 @@ static void ddr_config_sub_h3v1x(void) if (o_inv & (1U << bit_mem)) inv |= (1U << bit_soc); } - dataL = o_mr32_mr40; + data_l = o_mr32_mr40; if (!high_byte[slice]) - dataL |= (inv << 24); + data_l |= (inv << 24); if (high_byte[slice]) - dataL |= (inv << 16); + data_l |= (inv << 16); ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8, - dataL); + data_l); } } } @@ -1868,7 +1867,7 @@ static void ddr_config(void) { int32_t i; uint32_t ch, slice; - uint32_t dataL; + uint32_t data_l; uint32_t tmp; int8_t _adj; int16_t adj; @@ -1882,7 +1881,7 @@ static void ddr_config(void) /*********************************************************************** configure ddrphy registers ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_config_sub_h3v1x(); } else { ddr_config_sub(); /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ @@ -1895,7 +1894,7 @@ static void ddr_config(void) for (slice = 0; slice < SLICE_CNT; slice++) { patm = 0; for (i = 0; i < 16; i++) { - tmp = Boardcnf->ch[ch].wdqlvl_patt[i]; + tmp = board_cnf->ch[ch].wdqlvl_patt[i]; patt.ui8[i] = tmp & 0xff; if (tmp & 0x100) patm |= (1U << i); @@ -1915,14 +1914,14 @@ static void ddr_config(void) /*********************************************************************** CACS DLY ***********************************************************************/ - dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); + data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U); foreach_vch(ch) { for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj); + data_l + adj); reg_ddrphy_write(ch, ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), @@ -1934,10 +1933,10 @@ static void ddr_config(void) for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj); + data_l + adj); reg_ddrphy_write(ch, ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), @@ -1950,11 +1949,11 @@ static void ddr_config(void) if (ddr_phycaslice == 1) { for (i = 0; i < 6; i++) { adj = _f_scale_adj( - Boardcnf->ch[ch].cacs_adj[ + board_cnf->ch[ch].cacs_adj[ i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj); + data_l + adj); reg_ddrphy_write(ch, ddr_regdef_adr( _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + @@ -1973,19 +1972,19 @@ static void ddr_config(void) /*********************************************************************** WDQDM DLY ***********************************************************************/ - dataL = Boardcnf->dqdm_dly_w; + data_l = board_cnf->dqdm_dly_w; foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { for (i = 0; i <= 8; i++) { dq = slice * 8 + i; if (i == 8) - _adj = Boardcnf->ch[ch].dm_adj_w[slice]; + _adj = board_cnf->ch[ch].dm_adj_w[slice]; else - _adj = Boardcnf->ch[ch].dq_adj_w[dq]; + _adj = board_cnf->ch[ch].dq_adj_w[dq]; adj = _f_scale_adj(_adj); ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], - dataL + adj); + data_l + adj); } } } @@ -1993,22 +1992,22 @@ static void ddr_config(void) /*********************************************************************** RDQDM DLY ***********************************************************************/ - dataL = Boardcnf->dqdm_dly_r; + data_l = board_cnf->dqdm_dly_r; foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { for (i = 0; i <= 8; i++) { dq = slice * 8 + i; if (i == 8) - _adj = Boardcnf->ch[ch].dm_adj_r[slice]; + _adj = board_cnf->ch[ch].dm_adj_r[slice]; else - _adj = Boardcnf->ch[ch].dq_adj_r[dq]; + _adj = board_cnf->ch[ch].dq_adj_r[dq]; adj = _f_scale_adj(_adj); ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY - [i], dataL + adj); + [i], data_l + adj); ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY - [i], dataL + adj); + [i], data_l + adj); } } } @@ -2020,7 +2019,7 @@ static void ddr_config(void) static void dbsc_regset_pre(void) { uint32_t ch, csab; - uint32_t dataL; + uint32_t data_l; /*********************************************************************** PRIMARY SETTINGS @@ -2034,7 +2033,7 @@ static void dbsc_regset_pre(void) mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); /* Chanel map (H3 Ver.1.x) */ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); /* DRAM SIZE REGISTER: @@ -2044,20 +2043,20 @@ static void dbsc_regset_pre(void) for (csab = 0; csab < 4; csab++) mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0)); - if (Prr_Product == PRR_PRODUCT_M3) { - dataL = 0xe4e4e4e4; + if (prr_product == PRR_PRODUCT_M3) { + data_l = 0xe4e4e4e4; foreach_ech(ch) { if ((ddr_phyvalid & (1U << ch))) - dataL = (dataL & (~(0x000000FF << (ch * 8)))) - | (((Boardcnf->ch[ch].dqs_swap & 0x0003) - | ((Boardcnf->ch[ch].dqs_swap & 0x0030) + data_l = (data_l & (~(0x000000FF << (ch * 8)))) + | (((board_cnf->ch[ch].dqs_swap & 0x0003) + | ((board_cnf->ch[ch].dqs_swap & 0x0030) >> 2) - | ((Boardcnf->ch[ch].dqs_swap & 0x0300) + | ((board_cnf->ch[ch].dqs_swap & 0x0300) >> 4) - | ((Boardcnf->ch[ch].dqs_swap & 0x3000) + | ((board_cnf->ch[ch].dqs_swap & 0x3000) >> 6)) << (ch * 8)); } - mmio_write_32(DBSC_DBBSWAP, dataL); + mmio_write_32(DBSC_DBBSWAP, data_l); } } @@ -2065,20 +2064,20 @@ static void dbsc_regset(void) { int32_t i; uint32_t ch; - uint32_t dataL; - uint32_t dataL2; + uint32_t data_l; + uint32_t data_l2; uint32_t tmp[4]; /* RFC */ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_20) + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) && (max_density == 0)) { - js2[JS2_tRFCab] = + js2[js2_trfcab] = _f_scale(ddr_mbps, ddr_mbpsdiv, - 1UL * jedec_spec2_tRFC_ab[1] * 1000, 0); + 1UL * jedec_spec2_trfc_ab[1] * 1000, 0); } else { - js2[JS2_tRFCab] = + js2[js2_trfcab] = _f_scale(ddr_mbps, ddr_mbpsdiv, - 1UL * jedec_spec2_tRFC_ab[max_density] * + 1UL * jedec_spec2_trfc_ab[max_density] * 1000, 0); } @@ -2092,46 +2091,46 @@ static void dbsc_regset(void) mmio_write_32(DBSC_DBTR(2), 0); /* DBTR3.TRCD: tRCD */ - mmio_write_32(DBSC_DBTR(3), js2[JS2_tRCD]); + mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]); /* DBTR4.TRPA,TRP: tRPab,tRPpb */ - mmio_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]); + mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]); /* DBTR5.TRC : use tRCpb */ - mmio_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]); + mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]); /* DBTR6.TRAS : tRAS */ - mmio_write_32(DBSC_DBTR(6), js2[JS2_tRAS]); + mmio_write_32(DBSC_DBTR(6), js2[js2_tras]); /* DBTR7.TRRD : tRRD */ - mmio_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]); + mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]); /* DBTR8.TFAW : tFAW */ - mmio_write_32(DBSC_DBTR(8), js2[JS2_tFAW]); + mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]); /* DBTR9.TRDPR : tRTP */ - mmio_write_32(DBSC_DBTR(9), js2[JS2_tRTP]); + mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]); - /* DBTR10.TWR : nWR */ - mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nWR); + /* DBTR10.TWR : nwr */ + mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr); /* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */ mmio_write_32(DBSC_DBTR(11), - RL + js2[JS2_tDQSCK] + (16 / 2) + 1 - WL + 2 + 2); + RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2); /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ - dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR]; - mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL); + data_l = WL + 1 + (16 / 2) + js2[js2_twtr]; + mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l); /* DBTR13.TRFCAB : tRFCab */ - mmio_write_32(DBSC_DBTR(13), (js2[JS2_tRFCab])); + mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab])); /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */ mmio_write_32(DBSC_DBTR(14), - (js2[JS2_tCKEHCMD] << 16) | (js2[JS2_tCKEHCMD])); + (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd])); /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */ - mmio_write_32(DBSC_DBTR(15), (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD])); + mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd])); /* DBTR16 */ /* WDQL : tphy_wrlat + tphy_wrdata */ @@ -2154,13 +2153,13 @@ static void dbsc_regset(void) /* WRCSGAP = 5 */ tmp[1] = 5; /* RDCSLAT = RDLAT_ADJ +2 */ - if (Prr_Product == PRR_PRODUCT_M3) { + if (prr_product == PRR_PRODUCT_M3) { tmp[2] = tmp[3]; } else { tmp[2] = tmp[3] + 2; } /* RDCSGAP = 6 */ - if (Prr_Product == PRR_PRODUCT_M3) { + if (prr_product == PRR_PRODUCT_M3) { tmp[3] = 4; } else { tmp[3] = 6; @@ -2170,7 +2169,7 @@ static void dbsc_regset(void) /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */ mmio_write_32(DBSC_DBTR(17), - (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16)); + (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16)); /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ mmio_write_32(DBSC_DBTR(18), 0); @@ -2179,32 +2178,32 @@ static void dbsc_regset(void) mmio_write_32(DBSC_DBTR(19), 0); /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ - dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD]; - mmio_write_32(DBSC_DBTR(20), (dataL << 16) | dataL); + data_l = js2[js2_trfcab] + js2[js2_tckehcmd]; + mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l); /* DBTR21.TCCD */ /* DBTR23.TCCD */ /* H3 Ver.1.0 cannot use TBTR23 feature */ if (ddr_tccd == 8 && - !((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_10)) + !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10)) ) { - dataL = 8; - mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); + data_l = 8; + mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); mmio_write_32(DBSC_DBTR(23), 0x00000002); } else if (ddr_tccd <= 11) { - dataL = 11; - mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); + data_l = 11; + mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); mmio_write_32(DBSC_DBTR(23), 0x00000000); } else { - dataL = ddr_tccd; - mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); + data_l = ddr_tccd; + mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l); mmio_write_32(DBSC_DBTR(23), 0x00000000); } /* DBTR22.ZQLAT : */ - dataL = js2[JS2_tZQCALns] * 100; /* 1000 * 1000 ps */ - dataL = (dataL << 16) | (js2[JS2_tZQLAT] + 24 + 20); - mmio_write_32(DBSC_DBTR(22), dataL); + data_l = js2[js2_tzqcalns] * 100; /* 1000 * 1000 ps */ + data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20); + mmio_write_32(DBSC_DBTR(22), data_l); /* DBTR25 : do not use in LPDDR4 */ mmio_write_32(DBSC_DBTR(25), 0); @@ -2219,16 +2218,16 @@ static void dbsc_regset(void) #define _par_DBRNK_VAL (0x7007) for (i = 0; i < 4; i++) { - dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) { - dataL += 1; + data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_11) && (i == 0)) { + data_l += 1; } - dataL2 = 0; + data_l2 = 0; foreach_vch(ch) { - dataL2 = dataL2 | (dataL << (4 * ch)); + data_l2 = data_l2 | (data_l << (4 * ch)); } - mmio_write_32(DBSC_DBRNK(2 + i), dataL2); + mmio_write_32(DBSC_DBRNK(2 + i), data_l2); } mmio_write_32(DBSC_DBADJ0, 0x00000000); @@ -2237,17 +2236,17 @@ static void dbsc_regset(void) ***********************************************************************/ /* SCFCTST0 */ /* SCFCTST0 ACT-ACT */ - tmp[3] = 1UL * js2[JS2_tRCpb] * 800 * ddr_mbpsdiv / ddr_mbps; + tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps; /* SCFCTST0 RDA-ACT */ tmp[2] = - 1UL * ((16 / 2) + js2[JS2_tRTP] - 8 + - js2[JS2_tRPpb]) * 800 * ddr_mbpsdiv / ddr_mbps; + 1UL * ((16 / 2) + js2[js2_trtp] - 8 + + js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps; /* SCFCTST0 WRA-ACT */ tmp[1] = 1UL * (WL + 1 + (16 / 2) + - js1[js1_ind].nWR) * 800 * ddr_mbpsdiv / ddr_mbps; + js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps; /* SCFCTST0 PRE-ACT */ - tmp[0] = 1UL * js2[JS2_tRPpb]; + tmp[0] = 1UL * js2[js2_trppb]; mmio_write_32(DBSC_SCFCTST0, (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); @@ -2261,7 +2260,7 @@ static void dbsc_regset(void) 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv / ddr_mbps; /* SCFCTST1 ACT-RD/WR */ - tmp[1] = 1UL * js2[JS2_tRCD] * 800 * ddr_mbpsdiv / ddr_mbps; + tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps; /* SCFCTST1 ASYNCOFS */ tmp[0] = 12; mmio_write_32(DBSC_SCFCTST1, @@ -2269,14 +2268,14 @@ static void dbsc_regset(void) /* DBSCHRW1 */ /* DBSCHRW1 SCTRFCAB */ - tmp[0] = 1UL * js2[JS2_tRFCab] * 800 * ddr_mbpsdiv / ddr_mbps; - dataL = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) + tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps; + data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; - if (tmp[0] < dataL) - tmp[0] = dataL; + if (tmp[0] < data_l) + tmp[0] = data_l; - if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { + if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { mmio_write_32(DBSC_DBSCHRW1, tmp[0] + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3); @@ -2334,18 +2333,18 @@ static void dbsc_regset(void) mmio_write_32(QOSCTRL_RAEN, 0x00000001U); #endif /* ddr_qos_init_setting */ /* H3 Ver.1.1 need to set monitor function */ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { mmio_write_32(DBSC_DBMONCONF4, 0x00700000); } - if (Prr_Product == PRR_PRODUCT_H3) { - if (Prr_Cut == PRR_PRODUCT_10) { + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut == PRR_PRODUCT_10) { /* resrdis, simple mode, sc off */ mmio_write_32(DBSC_DBBCAMDIS, 0x00000007); - } else if (Prr_Cut == PRR_PRODUCT_11) { + } else if (prr_cut == PRR_PRODUCT_11) { /* resrdis, simple mode */ mmio_write_32(DBSC_DBBCAMDIS, 0x00000005); - } else if (Prr_Cut < PRR_PRODUCT_30) { + } else if (prr_cut < PRR_PRODUCT_30) { /* H3 Ver.2.0 */ /* resrdis */ mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); @@ -2362,7 +2361,7 @@ static void dbsc_regset(void) static void dbsc_regset_post(void) { uint32_t ch, cs; - uint32_t dataL; + uint32_t data_l; uint32_t slice, rdlat_max, rdlat_min; rdlat_max = 0; @@ -2374,18 +2373,18 @@ static void dbsc_regset_post(void) ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_LATENCY_ADJUST); - if (dataL > rdlat_max) - rdlat_max = dataL; - if (dataL < rdlat_min) - rdlat_min = dataL; + if (data_l > rdlat_max) + rdlat_max = data_l; + if (data_l < rdlat_min) + rdlat_min = data_l; } } } } - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) { mmio_write_32(DBSC_DBTR(24), ((rdlat_max * 2 - rdlat_min + 4) << 24) + ((rdlat_min + 2) << 16) + @@ -2415,24 +2414,24 @@ static void dbsc_regset_post(void) mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); /*set DBI */ - if (Boardcnf->dbi_en) + if (board_cnf->dbi_en) mmio_write_32(DBSC_DBDBICNT, 0x00000003); /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ - if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en)) + if ((((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) && (board_cnf->dbi_en)) reg_ddrphy_write_a(0x00001010, 0x01000000); /*set REFCYCLE */ - dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; - mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff)); + data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; + mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff)); mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); #ifdef DDR_BACKUPMODE - if (ddrBackup == DRAM_BOOT_STATUS_WARM) { + if (ddr_backup == DRAM_BOOT_STATUS_WARM) { #ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */ - PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1); + DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1); send_dbcmd(0x08040001); wait_dbcmd(); send_dbcmd(0x0A040001); @@ -2440,7 +2439,7 @@ static void dbsc_regset_post(void) send_dbcmd(0x04040010); wait_dbcmd(); - if (Prr_Product == PRR_PRODUCT_H3) { + if (prr_product == PRR_PRODUCT_H3) { send_dbcmd(0x08140001); wait_dbcmd(); send_dbcmd(0x0A140001); @@ -2462,8 +2461,8 @@ static void dbsc_regset_post(void) #if RCAR_REWT_TRAINING != 0 /* Periodic-WriteDQ Training seeting */ - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10))) { /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ } else { /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H -> Periodic-WriteDQ Training seeting */ @@ -2487,7 +2486,7 @@ static void dbsc_regset_post(void) ddr_setval_ach(_reg_PI_TREF_F1, 0x0000); ddr_setval_ach(_reg_PI_TREF_F2, 0x0000); - if (Prr_Product == PRR_PRODUCT_M3) { + if (prr_product == PRR_PRODUCT_M3) { ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02); } else { ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02); @@ -2500,13 +2499,13 @@ static void dbsc_regset_post(void) #endif /* RCAR_REWT_TRAINING */ /* periodic dram zqcal and phy ctrl update enable */ mmio_write_32(DBSC_DBCALCNF, 0x01000010); - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { #if RCAR_DRAM_SPLIT == 2 - if ((Prr_Product == PRR_PRODUCT_H3) - && (Boardcnf->phyvalid == 0x05)) + if ((prr_product == PRR_PRODUCT_H3) + && (board_cnf->phyvalid == 0x05)) mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); else mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); @@ -2531,10 +2530,10 @@ static uint32_t dfi_init_start(void) uint32_t ch; uint32_t phytrainingok; uint32_t retry; - uint32_t dataL; + uint32_t data_l; const uint32_t RETRY_MAX = 0x10000; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { /*********************************************************************** PLL3 Disable ***********************************************************************/ @@ -2584,8 +2583,8 @@ static uint32_t dfi_init_start(void) retry = 0; while (retry++ < RETRY_MAX) { foreach_vch(ch) { - dataL = mmio_read_32(DBSC_DBDFISTAT(ch)); - if (dataL & 0x00000001) + data_l = mmio_read_32(DBSC_DBDFISTAT(ch)); + if (data_l & 0x00000001) phytrainingok |= (1U << ch); } dsb_sev(); @@ -2621,7 +2620,7 @@ static void change_lpddr4_en(uint32_t mode) { uint32_t ch; uint32_t i; - uint32_t dataL; + uint32_t data_l; const uint32_t _reg_PHY_PAD_DRIVE_X[3] = { _reg_PHY_PAD_ADDR_DRIVE, _reg_PHY_PAD_CLK_DRIVE, @@ -2630,13 +2629,13 @@ static void change_lpddr4_en(uint32_t mode) foreach_vch(ch) { for (i = 0; i < 3; i++) { - dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); + data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); if (mode) { - dataL |= (1U << 14); + data_l |= (1U << 14); } else { - dataL &= ~(1U << 14); + data_l &= ~(1U << 14); } - ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], dataL); + ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l); } } } @@ -2648,7 +2647,7 @@ static uint32_t set_term_code(void) { int32_t i; uint32_t ch, index; - uint32_t dataL; + uint32_t data_l; uint32_t chip_id[2]; uint32_t term_code; uint32_t override; @@ -2664,12 +2663,12 @@ static uint32_t set_term_code(void) index = 0; while (1) { - if (TermcodeBySample[index][0] == 0xffffffff) { + if (termcode_by_sample[index][0] == 0xffffffff) { break; } - if ((TermcodeBySample[index][0] == chip_id[0]) - && (TermcodeBySample[index][1] == chip_id[1])) { - term_code = TermcodeBySample[index][2]; + if ((termcode_by_sample[index][0] == chip_id[0]) + && (termcode_by_sample[index][1] == chip_id[1])) { + term_code = termcode_by_sample[index][2]; override = 1; break; } @@ -2678,14 +2677,14 @@ static uint32_t set_term_code(void) if (override) { for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { - dataL = + data_l = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_TERM_X[index]); - dataL = (dataL & 0xfffe0000) | term_code; - ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL); + data_l = (data_l & 0xfffe0000) | term_code; + ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l); } - } else if ((Prr_Product == PRR_PRODUCT_M3) - && (Prr_Cut == PRR_PRODUCT_10)) { + } else if ((prr_product == PRR_PRODUCT_M3) + && (prr_cut == PRR_PRODUCT_10)) { /* non */ } else { ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], @@ -2696,55 +2695,55 @@ static uint32_t set_term_code(void) ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01); foreach_vch(ch) { do { - dataL = + data_l = ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); - } while (!(dataL & 0x00800000)); + } while (!(data_l & 0x00800000)); } - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { - dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); - pvtr = (dataL >> 12) & 0x1f; + data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); + pvtr = (data_l >> 12) & 0x1f; pvtr += 8; if (pvtr > 0x1f) pvtr = 0x1f; - dataL = + data_l = ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); - pvtn = (dataL >> 6) & 0x03f; - pvtp = (dataL >> 0) & 0x03f; + pvtn = (data_l >> 6) & 0x03f; + pvtp = (data_l >> 0) & 0x03f; for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { - dataL = + data_l = ddrtbl_getval (_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_TERM_X[index]); - dataL = (dataL & 0xfffe0000) + data_l = (data_l & 0xfffe0000) | (pvtr << 12) | (pvtn << 6) | (pvtp); ddr_setval(ch, _reg_PHY_PAD_TERM_X[index], - dataL); + data_l); } } } else { /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ foreach_vch(ch) { for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { - dataL = + data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X [index]); ddr_setval(ch, _reg_PHY_PAD_TERM_X[index], - (dataL & 0xFFFE0FFF) | + (data_l & 0xFFFE0FFF) | 0x00015000); } } } } - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { /* non */ } else { ddr_padcal_tcompensate_getinit(override); @@ -2766,32 +2765,32 @@ static void ddr_register_set(void) tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr1_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840100 | tmp); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr2_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840200 | tmp); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr3_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840300 | tmp); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr11_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840b00 | tmp); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr12_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840c00 | tmp); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, - _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]); + reg_pi_mr14_data_fx_csx[fspwp][0]); send_dbcmd(0x0e840e00 | tmp); /* MR22 */ send_dbcmd(0x0e841616); @@ -2803,33 +2802,33 @@ static void ddr_register_set(void) ******************************************************************************/ static inline uint32_t wait_freqchgreq(uint32_t assert) { - uint32_t dataL; + uint32_t data_l; uint32_t count; uint32_t ch; count = 100000; /* H3 Ver.1.x cannot see frqchg_req */ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { return 0; } if (assert) { do { - dataL = 1; + data_l = 1; foreach_vch(ch) { - dataL &= mmio_read_32(DBSC_DBPDSTAT(ch)); + data_l &= mmio_read_32(DBSC_DBPDSTAT(ch)); } count = count - 1; - } while (((dataL & 0x01) != 0x01) & (count != 0)); + } while (((data_l & 0x01) != 0x01) & (count != 0)); } else { do { - dataL = 0; + data_l = 0; foreach_vch(ch) { - dataL |= mmio_read_32(DBSC_DBPDSTAT(ch)); + data_l |= mmio_read_32(DBSC_DBPDSTAT(ch)); } count = count - 1; - } while (((dataL & 0x01) != 0x00) & (count != 0)); + } while (((data_l & 0x01) != 0x00) & (count != 0)); } return (count == 0); @@ -2838,22 +2837,22 @@ static inline uint32_t wait_freqchgreq(uint32_t assert) static inline void set_freqchgack(uint32_t assert) { uint32_t ch; - uint32_t dataL; + uint32_t data_l; if (assert) - dataL = 0x0CF20000; + data_l = 0x0CF20000; else - dataL = 0x00000000; + data_l = 0x00000000; foreach_vch(ch) - mmio_write_32(DBSC_DBPDCNT2(ch), dataL); + mmio_write_32(DBSC_DBPDCNT2(ch), data_l); } static inline void set_dfifrequency(uint32_t freq) { uint32_t ch; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); } else { @@ -2904,7 +2903,7 @@ static void update_dly(void) static uint32_t pi_training_go(void) { uint32_t flag; - uint32_t dataL; + uint32_t data_l; uint32_t retry; const uint32_t RETRY_MAX = 4096 * 16; uint32_t ch; @@ -2939,8 +2938,8 @@ static uint32_t pi_training_go(void) frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; /* H3 Ver.1.x cannot see frqchg_req */ - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { if ((retry % 4096) == 1) { frqchg_req = 1; } else { @@ -2965,9 +2964,9 @@ static uint32_t pi_training_go(void) foreach_vch(ch) { if (complete & (1U << ch)) continue; - dataL = + data_l = ddr_getval(ch, _reg_PI_INT_STATUS); - if (dataL & 0x01) { + if (data_l & 0x01) { complete |= (1U << ch); } } @@ -2978,9 +2977,9 @@ static uint32_t pi_training_go(void) } while (--retry); foreach_vch(ch) { /* dummy read */ - dataL = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); - dataL = ddr_getval(ch, _reg_PI_INT_STATUS); - ddr_setval(ch, _reg_PI_INT_ACK, dataL); + data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); + data_l = ddr_getval(ch, _reg_PI_INT_STATUS); + ddr_setval(ch, _reg_PI_INT_ACK, data_l); } if (ddrphy_regif_chk()) { return (0xfd); @@ -2994,7 +2993,7 @@ static uint32_t pi_training_go(void) static uint32_t init_ddr(void) { int32_t i; - uint32_t dataL; + uint32_t data_l; uint32_t phytrainingok; uint32_t ch, slice; uint32_t err; @@ -3003,7 +3002,7 @@ static uint32_t init_ddr(void) MSG_LF("init_ddr:0\n"); #ifdef DDR_BACKUPMODE - rcar_dram_get_boot_status(&ddrBackup); + rcar_dram_get_boot_status(&ddr_backup); #endif /*********************************************************************** @@ -3014,9 +3013,9 @@ static uint32_t init_ddr(void) mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); dsb_sev(); - if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en)) + if ((((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) && (board_cnf->dbi_en)) reg_ddrphy_write_a(0x00001010, 0x01000001); else reg_ddrphy_write_a(0x00001010, 0x00000001); @@ -3069,12 +3068,12 @@ static uint32_t init_ddr(void) ddr backupmode end ***********************************************************************/ #ifdef DDR_BACKUPMODE - if (ddrBackup) { + if (ddr_backup) { NOTICE("BL2: [WARM_BOOT]\n"); } else { NOTICE("BL2: [COLD_BOOT]\n"); } - err = rcar_dram_update_boot_status(ddrBackup); + err = rcar_dram_update_boot_status(ddr_backup); if (err) { NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); return INITDRAM_ERR_I; @@ -3094,8 +3093,8 @@ static uint32_t init_ddr(void) /*********************************************************************** rx offset calibration ***********************************************************************/ - if ((Prr_Cut > PRR_PRODUCT_11) || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { err = rx_offset_cal_hw(); } else { err = rx_offset_cal(); @@ -3139,8 +3138,8 @@ static uint32_t init_ddr(void) Thermal sensor setting ***********************************************************************/ /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ - dataL = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; - mmio_write_32(THS1_THCTR, dataL); + data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; + mmio_write_32(THS1_THCTR, data_l); /* LPDDR4 MODE */ change_lpddr4_en(1); @@ -3151,10 +3150,10 @@ static uint32_t init_ddr(void) mask CS_MAP if RANKx is not found ***********************************************************************/ foreach_vch(ch) { - dataL = ddr_getval(ch, _reg_PI_CS_MAP); + data_l = ddr_getval(ch, _reg_PI_CS_MAP); if (!(ch_have_this_cs[1] & (1U << ch))) - dataL = dataL & 0x05; - ddr_setval(ch, _reg_PI_CS_MAP, dataL); + data_l = data_l & 0x05; + ddr_setval(ch, _reg_PI_CS_MAP, data_l); } /*********************************************************************** @@ -3164,7 +3163,7 @@ static uint32_t init_ddr(void) BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); } else { foreach_vch(ch) { @@ -3188,19 +3187,19 @@ static uint32_t init_ddr(void) /*********************************************************************** CACS DLY ADJUST ***********************************************************************/ - dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); + data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); foreach_vch(ch) { for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj); + data_l + adj); } if (ddr_phycaslice == 1) { for (i = 0; i < 6; i++) { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj + data_l + adj ); } } @@ -3212,7 +3211,7 @@ static uint32_t init_ddr(void) /*********************************************************************** H3 fix rd latency to avoid bug in elasitic buffe ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { adjust_rddqs_latency(); } @@ -3255,9 +3254,9 @@ static uint32_t init_ddr(void) /*********************************************************************** training complete, setup dbsc ***********************************************************************/ - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); } @@ -3274,7 +3273,7 @@ static uint32_t init_ddr(void) static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) { uint32_t ch; - uint32_t dataL; + uint32_t data_l; uint32_t retry; uint32_t waiting; uint32_t err; @@ -3303,8 +3302,8 @@ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) foreach_vch(ch) { if (!(waiting & (1U << ch))) continue; - dataL = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); - if (dataL & 0x01) + data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); + if (data_l & 0x01) waiting &= ~(1U << ch); } retry--; @@ -3329,15 +3328,15 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) { int32_t i, k; uint32_t cs, slice; - uint32_t dataL; + uint32_t data_l; /*********************************************************************** clr of training results buffer ***********************************************************************/ cs = ddr_csn % 2; - dataL = Boardcnf->dqdm_dly_w; + data_l = board_cnf->dqdm_dly_w; for (slice = 0; slice < SLICE_CNT; slice++) { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) continue; @@ -3346,7 +3345,7 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) wdqdm_dly[ch][cs][slice][i] = wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; else - wdqdm_dly[ch][cs][slice][i] = dataL; + wdqdm_dly[ch][cs][slice][i] = data_l; wdqdm_le[ch][cs][slice][i] = 0; wdqdm_te[ch][cs][slice][i] = 0; } @@ -3359,7 +3358,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) { int32_t i, k; uint32_t cs, slice; - uint32_t dataL; + uint32_t data_l; uint32_t err; const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0; @@ -3374,7 +3373,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) ***********************************************************************/ err = 0; for (slice = 0; slice < SLICE_CNT; slice += 1) { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) continue; @@ -3383,44 +3382,44 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) for (i = 0; i < 9; i++) { dq = slice * 8 + i; if (i == 8) - _adj = Boardcnf->ch[ch].dm_adj_w[slice]; + _adj = board_cnf->ch[ch].dm_adj_w[slice]; else - _adj = Boardcnf->ch[ch].dq_adj_w[dq]; + _adj = board_cnf->ch[ch].dq_adj_w[dq]; adj = _f_scale_adj(_adj); - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj; ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], - dataL); - wdqdm_dly[ch][cs][slice][i] = dataL; + data_l); + wdqdm_dly[ch][cs][slice][i] = data_l; } ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); - dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); - wdqdm_st[ch][cs][slice] = dataL; + data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); + wdqdm_st[ch][cs][slice] = data_l; min_win = INT_LEAST32_MAX; for (i = 0; i <= 8; i++) { ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT, i); - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS); - wdqdm_te[ch][cs][slice][i] = dataL; - dataL = + wdqdm_te[ch][cs][slice][i] = data_l; + data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); - wdqdm_le[ch][cs][slice][i] = dataL; + wdqdm_le[ch][cs][slice][i] = data_l; win = (int32_t)wdqdm_te[ch][cs][slice][i] - wdqdm_le[ch][cs][slice][i]; if (min_win > win) min_win = win; - if (dataL >= _par_WDQLVL_RETRY_THRES) + if (data_l >= _par_WDQLVL_RETRY_THRES) err = 2; } wdqdm_win[ch][cs][slice] = min_win; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01); } else { ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, @@ -3474,7 +3473,7 @@ static uint32_t wdqdm_man1(void) int32_t k; uint32_t ch, cs, slice; uint32_t ddr_csn; - uint32_t dataL; + uint32_t data_l; uint32_t err; uint32_t high_dq[DRAM_CH_CNT]; uint32_t mr14_csab0_bak[DRAM_CH_CNT]; @@ -3485,11 +3484,11 @@ static uint32_t wdqdm_man1(void) /*********************************************************************** manual execution of training ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { high_dq[ch] = 0; for (slice = 0; slice < SLICE_CNT; slice++) { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (k >= 2) high_dq[ch] |= (1U << slice); } @@ -3500,10 +3499,10 @@ static uint32_t wdqdm_man1(void) /* CLEAR PREV RESULT */ for (cs = 0; cs < CS_CNT; cs++) { ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); - if (((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01); } else { @@ -3517,33 +3516,33 @@ static uint32_t wdqdm_man1(void) err_flg = 0; #endif/* DDR_FAST_INIT */ for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { - dataL = mmio_read_32(DBSC_DBDFICNT(ch)); - dataL &= ~(0x00ffU << 16); + data_l = mmio_read_32(DBSC_DBDFICNT(ch)); + data_l &= ~(0x00ffU << 16); if (ddr_csn >= 2) k = (high_dq[ch] ^ 0x0f); else k = high_dq[ch]; - dataL |= (k << 16); - mmio_write_32(DBSC_DBDFICNT(ch), dataL); + data_l |= (k << 16); + mmio_write_32(DBSC_DBDFICNT(ch), data_l); ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); } } - if (((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) - && (Prr_Cut == PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) + && (prr_cut == PRR_PRODUCT_10))) { wdqdm_cp(ddr_csn, 0); } foreach_vch(ch) { - dataL = + data_l = ddr_getval(ch, - _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]); - ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], dataL); + reg_pi_mr14_data_fx_csx[1][ddr_csn]); + ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l); } /* KICK WDQLVL */ @@ -3554,10 +3553,10 @@ static uint32_t wdqdm_man1(void) if (ddr_csn == 0) foreach_vch(ch) { mr14_csab0_bak[ch] = - ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0]); + ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]); } else foreach_vch(ch) { - ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], + ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], mr14_csab0_bak[ch]); } #ifndef DDR_FAST_INIT @@ -3577,12 +3576,12 @@ err_exit: #ifndef DDR_FAST_INIT err |= err_flg; #endif/* DDR_FAST_INIT */ - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01); foreach_vch(ch) { - dataL = mmio_read_32(DBSC_DBDFICNT(ch)); - dataL &= ~(0x00ffU << 16); - mmio_write_32(DBSC_DBDFICNT(ch), dataL); + data_l = mmio_read_32(DBSC_DBDFICNT(ch)); + data_l &= ~(0x00ffU << 16); + mmio_write_32(DBSC_DBDFICNT(ch), data_l); ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); } } @@ -3596,9 +3595,9 @@ static uint32_t wdqdm_man(void) uint32_t ch, ddr_csn, mr14_bkup[4][4]; ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12); - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, (DBSC_DBTR(12) & 0xFF) + 1); } else { @@ -3610,15 +3609,15 @@ static uint32_t wdqdm_man(void) retry_cnt = 0; err = 0; do { - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { err = wdqdm_man1(); } else { ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x01); - if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x0C); } else { @@ -3630,14 +3629,14 @@ static uint32_t wdqdm_man(void) for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { mr14_bkup[ch][ddr_csn] = ddr_getval(ch, - _reg_PI_MR14_DATA_Fx_CSx + reg_pi_mr14_data_fx_csx [1][ddr_csn]); dsb_sev(); } } - if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x04); } else { @@ -3650,10 +3649,10 @@ static uint32_t wdqdm_man(void) mr14_bkup[ch][ddr_csn] = (mr14_bkup[ch][ddr_csn] + ddr_getval(ch, - _reg_PI_MR14_DATA_Fx_CSx + reg_pi_mr14_data_fx_csx [1][ddr_csn])) / 2; ddr_setval(ch, - _reg_PI_MR14_DATA_Fx_CSx[1] + reg_pi_mr14_data_fx_csx[1] [ddr_csn], mr14_bkup[ch][ddr_csn]); } @@ -3661,8 +3660,8 @@ static uint32_t wdqdm_man(void) ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x00); - if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x00); ddr_setval_ach @@ -3689,8 +3688,8 @@ static uint32_t wdqdm_man(void) } } while (err && (++retry_cnt < retry_max)); - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { wdqdm_cp(0, 1); } @@ -3705,15 +3704,15 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) { int32_t i, k; uint32_t cs, slice; - uint32_t dataL; + uint32_t data_l; /*********************************************************************** clr of training results buffer ***********************************************************************/ cs = ddr_csn % 2; - dataL = Boardcnf->dqdm_dly_r; + data_l = board_cnf->dqdm_dly_r; for (slice = 0; slice < SLICE_CNT; slice++) { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) continue; @@ -3726,8 +3725,8 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) SLICE_CNT] [i]; } else { - rdqdm_dly[ch][cs][slice][i] = dataL; - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL; + rdqdm_dly[ch][cs][slice][i] = data_l; + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; } rdqdm_le[ch][cs][slice][i] = 0; rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; @@ -3745,7 +3744,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) { int32_t i, k; uint32_t cs, slice; - uint32_t dataL; + uint32_t data_l; uint32_t err; int8_t _adj; int16_t adj; @@ -3759,7 +3758,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) ***********************************************************************/ err = 0; for (slice = 0; slice < SLICE_CNT; slice++) { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) continue; @@ -3773,36 +3772,36 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) for (i = 0; i <= 8; i++) { dq = slice * 8 + i; if (i == 8) - _adj = Boardcnf->ch[ch].dm_adj_r[slice]; + _adj = board_cnf->ch[ch].dm_adj_r[slice]; else - _adj = Boardcnf->ch[ch].dq_adj_r[dq]; + _adj = board_cnf->ch[ch].dq_adj_r[dq]; adj = _f_scale_adj(_adj); - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], - dataL); - rdqdm_dly[ch][cs][slice][i] = dataL; + data_l); + rdqdm_dly[ch][cs][slice][i] = data_l; - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], - dataL); - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL; + data_l); + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; } min_win = INT_LEAST32_MAX; for (i = 0; i <= 8; i++) { - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS); - rdqdm_st[ch][cs][slice] = dataL; - rdqdm_st[ch][cs][slice + SLICE_CNT] = dataL; + rdqdm_st[ch][cs][slice] = data_l; + rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l; /* k : rise/fall */ for (k = 0; k < 2; k++) { if (i == 8) { @@ -3814,23 +3813,23 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT, rdq_status_obs_select); - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = - dataL; + data_l; - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = - dataL; + data_l; - dataL = + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS); rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = - dataL; + data_l; win = (int32_t)rdqdm_te[ch][cs][slice + @@ -3858,7 +3857,7 @@ static uint32_t rdqdm_man1(void) uint32_t ddr_csn; #ifdef DDR_FAST_INIT uint32_t slice; - uint32_t i, adj, dataL; + uint32_t i, adj, data_l; #endif/* DDR_FAST_INIT */ uint32_t err; @@ -3897,26 +3896,26 @@ static uint32_t rdqdm_man1(void) } } } - if (((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) - && (Prr_Cut <= PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) + && (prr_cut <= PRR_PRODUCT_10))) { for (slice = 0; slice < SLICE_CNT; slice++) { for (i = 0; i <= 8; i++) { if (i == 8) - adj = _f_scale_adj(Boardcnf->ch[ch].dm_adj_r[slice]); + adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]); else - adj = _f_scale_adj(Boardcnf->ch[ch].dq_adj_r[slice * 8 + i]); + adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]); ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn); - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL); - rdqdm_dly[ch][ddr_csn][slice][i] = dataL; - rdqdm_dly[ch][ddr_csn | 1][slice][i] = dataL; - - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL); - rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = dataL; - rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = dataL; + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l); + rdqdm_dly[ch][ddr_csn][slice][i] = data_l; + rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l; + + data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l); + rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l; + rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l; } } } @@ -4003,7 +4002,7 @@ static uint32_t _rx_offset_cal_updn(uint32_t code) const uint32_t CODE_MAX = 0x40; uint32_t tmp; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { if (code == 0) tmp = (1U << 6) | (CODE_MAX - 1); else if (code <= 0x20) @@ -4117,10 +4116,10 @@ static uint32_t rx_offset_cal_hw(void) for (slice = 0; slice < SLICE_CNT; slice++) { tmp = tmp_ach_as[ch][slice]; tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); - if (((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_11)) - || (Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_11)) + || (prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { if (tmp != 0x3E) complete = 0; } else { @@ -4222,60 +4221,61 @@ static void adjust_wpath_latency(void) int32_t rcar_dram_init(void) { uint32_t ch, cs; - uint32_t dataL; + uint32_t data_l; uint32_t bus_mbps, bus_mbpsdiv; uint32_t tmp_tccd; uint32_t failcount; + uint32_t cnf_boardtype; /*********************************************************************** Thermal sensor setting ***********************************************************************/ - dataL = mmio_read_32(CPG_MSTPSR5); - if (dataL & BIT(22)) { /* case THS/TSC Standby */ - dataL &= ~(BIT(22)); - cpg_write_32(CPG_SMSTPCR5, dataL); + data_l = mmio_read_32(CPG_MSTPSR5); + if (data_l & BIT(22)) { /* case THS/TSC Standby */ + data_l &= ~(BIT(22)); + cpg_write_32(CPG_SMSTPCR5, data_l); while ((BIT(22)) & mmio_read_32(CPG_MSTPSR5)); /* wait bit=0 */ } /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ - dataL = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; - mmio_write_32(THS1_THCTR, dataL); + data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; + mmio_write_32(THS1_THCTR, data_l); /*********************************************************************** Judge product and cut ***********************************************************************/ #ifdef RCAR_DDR_FIXED_LSI_TYPE #if (RCAR_LSI == RCAR_AUTO) - Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; - Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; #else /* RCAR_LSI */ #ifndef RCAR_LSI_CUT - Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; #endif /* RCAR_LSI_CUT */ #endif /* RCAR_LSI */ #else /* RCAR_DDR_FIXED_LSI_TYPE */ - Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; - Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK; #endif /* RCAR_DDR_FIXED_LSI_TYPE */ - if (Prr_Product == PRR_PRODUCT_H3) { - if (Prr_Cut <= PRR_PRODUCT_11) { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[0][0]; + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { + p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[0][0]; } else { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[2][0]; + p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[2][0]; } - } else if (Prr_Product == PRR_PRODUCT_M3) { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[1][0]; - } else if ((Prr_Product == PRR_PRODUCT_M3N) - || (Prr_Product == PRR_PRODUCT_V3H)) { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[3][0]; + } else if (prr_product == PRR_PRODUCT_M3) { + p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[1][0]; + } else if ((prr_product == PRR_PRODUCT_M3N) + || (prr_product == PRR_PRODUCT_V3H)) { + p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[3][0]; } else { FATAL_MSG("BL2: DDR:Unknown Product\n"); return 0xff; } - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); @@ -4284,26 +4284,26 @@ int32_t rcar_dram_init(void) /*********************************************************************** Judge board type ***********************************************************************/ - _cnf_BOARDTYPE = boardcnf_get_brd_type(); - if (_cnf_BOARDTYPE >= BOARDNUM) { + cnf_boardtype = boardcnf_get_brd_type(); + if (cnf_boardtype >= BOARDNUM) { FATAL_MSG("BL2: DDR:Unknown Board\n"); return 0xff; } - Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE]; + board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype]; /* RCAR_DRAM_SPLIT_2CH (2U) */ #if RCAR_DRAM_SPLIT == 2 /*********************************************************************** H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_H3) && (Boardcnf->phyvalid == 0x05)) { + if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) { mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); ddr_phyvalid = 0x03; } else { - ddr_phyvalid = Boardcnf->phyvalid; + ddr_phyvalid = board_cnf->phyvalid; } #else /* RCAR_DRAM_SPLIT_2CH */ - ddr_phyvalid = Boardcnf->phyvalid; + ddr_phyvalid = board_cnf->phyvalid; #endif /* RCAR_DRAM_SPLIT_2CH */ max_density = 0; @@ -4318,15 +4318,15 @@ int32_t rcar_dram_init(void) foreach_vch(ch) { for (cs = 0; cs < CS_CNT; cs++) { - dataL = Boardcnf->ch[ch].ddr_density[cs]; - ddr_density[ch][cs] = dataL; + data_l = board_cnf->ch[ch].ddr_density[cs]; + ddr_density[ch][cs] = data_l; - if (dataL == 0xff) + if (data_l == 0xff) continue; - if (dataL > max_density) - max_density = dataL; - if ((cs == 1) && (Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) + if (data_l > max_density) + max_density = data_l; + if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) continue; ch_have_this_cs[cs] |= (1U << ch); } @@ -4335,7 +4335,7 @@ int32_t rcar_dram_init(void) /*********************************************************************** Judge board clock frequency (in MHz) ***********************************************************************/ - boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv); + boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv); if ((brd_clk / brd_clkdiv) > 25) { brd_clkdiva = 1; } else { @@ -4345,7 +4345,7 @@ int32_t rcar_dram_init(void) /*********************************************************************** Judge ddr operating frequency clock(in Mbps) ***********************************************************************/ - boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv); + boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv); ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); @@ -4355,10 +4355,10 @@ int32_t rcar_dram_init(void) /*********************************************************************** Adjust tccd ***********************************************************************/ - dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; + data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; bus_mbps = 0; bus_mbpsdiv = 0; - switch (dataL) { + switch (data_l) { case 0: bus_mbps = brd_clk * 0x60 * 2; bus_mbpsdiv = brd_clkdiv * 1; @@ -4401,8 +4401,8 @@ int32_t rcar_dram_init(void) /*********************************************************************** initialize DDR ***********************************************************************/ - dataL = init_ddr(); - if (dataL == ddr_phyvalid) { + data_l = init_ddr(); + if (data_l == ddr_phyvalid) { failcount = 0; } else { failcount = 1; @@ -4410,8 +4410,8 @@ int32_t rcar_dram_init(void) foreach_vch(ch) mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); - if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) - || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) + || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); @@ -4427,7 +4427,7 @@ int32_t rcar_dram_init(void) void pvtcode_update(void) { uint32_t ch; - uint32_t dataL; + uint32_t data_l; uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init; int32_t pvtp_tmp, pvtn_tmp; @@ -4453,41 +4453,41 @@ void pvtcode_update(void) pvtn_init) / (pvtn_tmp) + 6 * pvtp_tmp + pvtp_init; } - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { - dataL = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000); + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { + data_l = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), - dataL | 0x00020000); + data_l | 0x00020000); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), - dataL); + data_l); } else { - dataL = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; + data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), - dataL | 0x00020000); + data_l | 0x00020000); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), - dataL); + data_l); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), - dataL); + data_l); } } } @@ -4513,7 +4513,7 @@ void pvtcode_update2(void) void ddr_padcal_tcompensate_getinit(uint32_t override) { uint32_t ch; - uint32_t dataL; + uint32_t data_l; uint32_t pvtp, pvtn; tcal.init_temp = 0; @@ -4528,13 +4528,13 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) } if (!override) { - dataL = mmio_read_32(THS1_TEMP); - if (dataL < 2800) { + data_l = mmio_read_32(THS1_TEMP); + if (data_l < 2800) { tcal.init_temp = - (143 * (int32_t)dataL - 359000) / 1000; + (143 * (int32_t)data_l - 359000) / 1000; } else { tcal.init_temp = - (121 * (int32_t)dataL - 296300) / 1000; + (121 * (int32_t)data_l - 296300) / 1000; } foreach_vch(ch) { @@ -4556,8 +4556,8 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) else pvtn = 0; - if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { tcal.init_cal[ch] = (tcal. init_cal[ch] & 0xfffff000) | (pvtn << 6) | diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index 58c9a7a4..cb3a482e 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -1533,7 +1533,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) { uint32_t md; - if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_10)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_10)) { *clk = 50; *div = 3; } else { @@ -1599,7 +1599,7 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) #define M3_SAMPLE_SS_E28 0xB866CC10, 0x3C231421 #define M3_SAMPLE_SS_E32 0xB866CC10, 0x3C241421 -static const uint32_t TermcodeBySample[20][3] = { +static const uint32_t termcode_by_sample[20][3] = { {M3_SAMPLE_TT_A84, 0x000158D5}, {M3_SAMPLE_TT_A85, 0x00015955}, {M3_SAMPLE_TT_A86, 0x00015955}, @@ -1701,8 +1701,8 @@ static uint32_t _board_judge(void) uint32_t brd; #if (RCAR_GEN3_ULCB == 1) /* Starter Kit */ - if (Prr_Product == PRR_PRODUCT_H3) { - if (Prr_Cut <= PRR_PRODUCT_11) { + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { /* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */ brd = 2; } else { @@ -1713,7 +1713,7 @@ static uint32_t _board_judge(void) brd = 8; #endif } - } else if (Prr_Product == PRR_PRODUCT_M3) { + } else if (prr_product == PRR_PRODUCT_M3) { /* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */ brd = 3; } else { @@ -1727,31 +1727,31 @@ static uint32_t _board_judge(void) /* RENESAS Eva-board */ brd = 99; - if (Prr_Product == PRR_PRODUCT_V3H) { + if (prr_product == PRR_PRODUCT_V3H) { /* RENESAS Condor board */ brd = 12; } else if (usb2_ovc_open) { - if (Prr_Product == PRR_PRODUCT_M3N) { + if (prr_product == PRR_PRODUCT_M3N) { /* RENESAS Kriek board with M3-N */ brd = 10; - } else if (Prr_Product == PRR_PRODUCT_M3) { + } else if (prr_product == PRR_PRODUCT_M3) { /* RENESAS Kriek board with M3-W */ brd = 1; - } else if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut <= PRR_PRODUCT_11)) { + } else if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut <= PRR_PRODUCT_11)) { /* RENESAS Kriek board with PM3 */ brd = 13; - } else if ((Prr_Product == PRR_PRODUCT_H3) - && (Prr_Cut > PRR_PRODUCT_20)) { + } else if ((prr_product == PRR_PRODUCT_H3) + && (prr_cut > PRR_PRODUCT_20)) { /* RENESAS Kriek board with H3N */ brd = 15; } } else { - if (Prr_Product == PRR_PRODUCT_H3) { - if (Prr_Cut <= PRR_PRODUCT_11) { + if (prr_product == PRR_PRODUCT_H3) { + if (prr_cut <= PRR_PRODUCT_11) { /* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */ brd = 2; - } else if (Prr_Cut < PRR_PRODUCT_30) { + } else if (prr_cut < PRR_PRODUCT_30) { /* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */ brd = 7; // 8Gbit/1rank } else { @@ -1762,16 +1762,16 @@ static uint32_t _board_judge(void) brd = 8; #endif } - } else if (Prr_Product == PRR_PRODUCT_M3N) { + } else if (prr_product == PRR_PRODUCT_M3N) { /* RENESAS SALVATOR-X (M3-N/SIP) */ brd = 11; - } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20)) { + } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_20)) { /* RENESAS SALVATOR-X (M3-W/SIP) */ brd = 0; - } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { + } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */ brd = 19; - } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) { + } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut >= PRR_PRODUCT_30)) { /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */ brd = 18; } -- cgit v1.2.3 From 087561475e17afca1884afa729c3c88384453afc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 7 Aug 2019 19:56:09 +0200 Subject: rcar_gen3: drivers: ddr_b: Further checkpatch cleanups Address more checkpatch CHECKs and ERRORs, no functional change. Signed-off-by: Marek Vasut Change-Id: Ife682288cef3afa860571b2aca647c9ffe936125 --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 752 ++++++++------------- .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 19 +- 2 files changed, 291 insertions(+), 480 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index 244caf6e..d1068729 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -25,9 +25,7 @@ #define DDR_BACKUPMODE #define FATAL_MSG(x) NOTICE(x) -/******************************************************************************* - * variables - ******************************************************************************/ +/* variables */ #ifdef RCAR_DDR_FIXED_LSI_TYPE #ifndef RCAR_AUTO #define RCAR_AUTO 99 @@ -90,7 +88,7 @@ static uint32_t ddr_phycaslice; static const struct _boardcnf *board_cnf; static uint32_t ddr_phyvalid; static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; -static uint32_t ch_have_this_cs[CS_CNT] __attribute__ ((aligned(64))); +static uint32_t ch_have_this_cs[CS_CNT] __aligned(64); static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; static uint32_t max_density; static uint32_t ddr0800_mul; @@ -129,7 +127,9 @@ uint32_t ddr_backup; #define OPERATING_FREQ (400U) /* Mhz */ #define BASE_SUB_SLOT_NUM (0x6U) #define SUB_SLOT_CYCLE (0x7EU) /* 126 */ -#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) /* unit:ns */ +#define QOSWT_WTSET0_CYCLE \ + ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \ + OPERATING_FREQ) /* unit:ns */ uint32_t get_refperiod(void) { @@ -155,8 +155,7 @@ static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { }; #define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 -static const uint32_t - _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, @@ -170,8 +169,7 @@ static const uint32_t }; #define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 -static const uint32_t - _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, @@ -184,8 +182,7 @@ static const uint32_t }; #define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 -static const uint32_t - _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, @@ -210,8 +207,7 @@ static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { }; #define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 -static const uint32_t - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { +static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, @@ -225,9 +221,7 @@ static const uint32_t _reg_PHY_GRP_SLAVE_DELAY_3 }; -/******************************************************************************* - * Prototypes - ******************************************************************************/ +/* Prototypes */ static inline uint32_t vch_nxt(uint32_t pos); static void cpg_write_32(uint32_t a, uint32_t v); static void pll3_control(uint32_t high); @@ -292,9 +286,9 @@ static void adjust_rddqs_latency(void); static void adjust_wpath_latency(void); struct ddrt_data { - int32_t init_temp; /* Initial Temperature (do) */ - uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ - uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */ + int32_t init_temp; /* Initial Temperature (do) */ + uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ + uint32_t tcomp_cal[4]; /* Temp. compensated io-code (4 is for H3) */ }; static struct ddrt_data tcal; @@ -303,9 +297,7 @@ static void pvtcode_update(void); static void pvtcode_update2(void); static void ddr_padcal_tcompensate_getinit(uint32_t override); -/******************************************************************************* - * load board configuration - ******************************************************************************/ +/* load board configuration */ #include "boot_init_dram_config.c" #ifndef DDR_FAST_INIT @@ -326,9 +318,7 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn); static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn); #endif/* DDR_FAST_INIT */ -/******************************************************************************* - * macro for channel selection loop - ******************************************************************************/ +/* macro for channel selection loop */ static inline uint32_t vch_nxt(uint32_t pos) { uint32_t posn; @@ -346,14 +336,10 @@ for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1)) #define foreach_ech(ch) \ for (ch = 0; ch < DRAM_CH_CNT; ch++) -/******************************************************************************* - * Printing functions - ******************************************************************************/ +/* Printing functions */ #define MSG_LF(...) -/******************************************************************************* - * clock settings, reset control - ******************************************************************************/ +/* clock settings, reset control */ static void cpg_write_32(uint32_t a, uint32_t v) { mmio_write_32(CPG_CPGWPR, ~v); @@ -443,7 +429,8 @@ static void pll3_control(uint32_t high) dsb_sev(); /* PLL3 DIV resetting(Target value) */ - data_l = (data_div << 16) | data_div | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + data_l = (data_div << 16) | data_div | + (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); cpg_write_32(CPG_FRQCRD, data_l); dsb_sev(); @@ -469,7 +456,8 @@ static void pll3_control(uint32_t high) dsb_sev(); /* PLL3 DIV set(Target value) */ - data_l = (data_div << 16) | data_div | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + data_l = (data_div << 16) | data_div | + (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80); cpg_write_32(CPG_FRQCRD, data_l); /* DIV SET KICK */ @@ -489,17 +477,13 @@ static void pll3_control(uint32_t high) } } -/******************************************************************************* - * barrier - ******************************************************************************/ +/* barrier */ static inline void dsb_sev(void) { __asm__ __volatile__("dsb sy"); } -/******************************************************************************* - * DDR memory register access - ******************************************************************************/ +/* DDR memory register access */ static void wait_dbcmd(void) { uint32_t data_l; @@ -523,17 +507,15 @@ static void send_dbcmd(uint32_t cmd) dsb_sev(); } -/******************************************************************************* - * DDRPHY register access (raw) - ******************************************************************************/ +/* DDRPHY register access (raw) */ static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) { uint32_t val; uint32_t loop; val = 0; - if ((prr_product != PRR_PRODUCT_M3N) - && (prr_product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) && + (prr_product != PRR_PRODUCT_V3H)) { mmio_write_32(DBSC_DBPDRGA(phyno), regadd); dsb_sev(); @@ -579,8 +561,8 @@ static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) uint32_t val; uint32_t loop; - if ((prr_product != PRR_PRODUCT_M3N) - && (prr_product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) && + (prr_product != PRR_PRODUCT_V3H)) { mmio_write_32(DBSC_DBPDRGA(phyno), regadd); dsb_sev(); for (loop = 0; loop < loop_max; loop++) { @@ -628,8 +610,8 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) uint32_t val; uint32_t loop; - if ((prr_product != PRR_PRODUCT_M3N) - && (prr_product != PRR_PRODUCT_V3H)) { + if ((prr_product != PRR_PRODUCT_M3N) && + (prr_product != PRR_PRODUCT_V3H)) { foreach_vch(ch) { mmio_write_32(DBSC_DBPDRGA(ch), regadd); dsb_sev(); @@ -662,9 +644,7 @@ static inline void ddrphy_regif_idle(void) (void)val; } -/******************************************************************************* - * DDRPHY register access (field modify) - ******************************************************************************/ +/* DDRPHY register access (field modify) */ static inline uint32_t ddr_regdef(uint32_t _regdef) { return p_ddr_regdef_tbl[_regdef]; @@ -780,9 +760,7 @@ static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) return p[0]; } -/******************************************************************************* - * handling functions for setteing ddrphy value table - ******************************************************************************/ +/* handling functions for setteing ddrphy value table */ static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) { uint32_t i; @@ -853,9 +831,7 @@ static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) return tmp; } -/******************************************************************************* - * DDRPHY register access handling - ******************************************************************************/ +/* DDRPHY register access handling */ static uint32_t ddrphy_regif_chk(void) { uint32_t tmp_ach[DRAM_CH_CNT]; @@ -863,11 +839,11 @@ static uint32_t ddrphy_regif_chk(void) uint32_t err; uint32_t PI_VERSION_CODE; - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3)) { - PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3)) { + PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ } else { - PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ + PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ } ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach); @@ -879,9 +855,7 @@ static uint32_t ddrphy_regif_chk(void) return err; } -/******************************************************************************* - * functions and parameters for timing setting - ******************************************************************************/ +/* functions and parameters for timing setting */ struct _jedec_spec1 { uint16_t fx3; uint8_t rlwodbi; @@ -1042,9 +1016,9 @@ static int16_t _f_scale_adj(int16_t ps) { int32_t tmp; /* - tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000; - = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125 - = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 + * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000; + * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125 + * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125 */ tmp = (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / @@ -1132,9 +1106,9 @@ const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = { _reg_PI_MR14_DATA_F1_3} }; -/******************************************************************************* +/* * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA ) - *******************************************************************************/ + */ static void regif_pll_wa(void) { uint32_t ch; @@ -1177,11 +1151,14 @@ static void regif_pll_wa(void) reg_ddrphy_write_a(ddr_regdef_adr (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL), ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, - _reg_PHY_LP4_BOOT_TOP_PLL_CTRL)); + _reg_PHY_LP4_BOOT_TOP_PLL_CTRL + )); } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), - _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]); + _cnf_DDR_PHY_ADR_G_REGSET + [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - + DDR_PHY_ADR_G_REGSET_OFS]); /* protect register interface */ ddrphy_regif_idle(); @@ -1196,9 +1173,7 @@ static void regif_pll_wa(void) ddrphy_regif_idle(); } - /*********************************************************************** - init start - ***********************************************************************/ + /* init start */ /* dbdficnt0: * dfi_dram_clk_disable=1 * dfi_frequency = 0 @@ -1220,14 +1195,13 @@ static void regif_pll_wa(void) dsb_sev(); foreach_ech(ch) - if (((board_cnf->phyvalid) & (1U << ch))) - while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f); + if ((board_cnf->phyvalid) & BIT(ch)) + while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) + ; dsb_sev(); } -/******************************************************************************* - * load table data into DDR registers - ******************************************************************************/ +/* load table data into DDR registers */ static void ddrtbl_load(void) { uint32_t i; @@ -1238,9 +1212,7 @@ static void ddrtbl_load(void) uint32_t tmp[3]; uint16_t dataS; - /*********************************************************************** - TIMING REGISTERS - ***********************************************************************/ + /* TIMING REGISTERS */ /* search jedec_spec1 index */ for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) { if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) @@ -1261,9 +1233,7 @@ static void ddrtbl_load(void) /* calculate jedec_spec2 */ _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); - /*********************************************************************** - PREPARE TBL - ***********************************************************************/ + /* PREPARE TBL */ if (prr_product == PRR_PRODUCT_H3) { if (prr_cut <= PRR_PRODUCT_11) { /* H3 Ver.1.x */ @@ -1404,9 +1374,7 @@ static void ddrtbl_load(void) DDR_PHY_ADR_I_NUM = 2; } - /*********************************************************************** - PLL CODE CHANGE - ***********************************************************************/ + /* PLL CODE CHANGE */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) { ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, 0x1142); @@ -1414,17 +1382,13 @@ static void ddrtbl_load(void) _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142); } - /*********************************************************************** - on fly gate adjust - ***********************************************************************/ + /* on fly gate adjust */ if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) { ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_ON_FLY_GATE_ADJUST_EN, 0x00); } - /*********************************************************************** - Adjust PI parameters - ***********************************************************************/ + /* Adjust PI parameters */ #ifdef _def_LPDDR4_ODT for (i = 0; i < 2; i++) { for (csab = 0; csab < CSAB_CNT; csab++) { @@ -1444,22 +1408,22 @@ static void ddrtbl_load(void) } } #endif /* _def_LPDDR4_VREFCA */ - if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; if (js2[js2_tiedly] > (RL)) js2[js2_tiedly] = RL; - } else if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_11)) { + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) { js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; - } else if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); } - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { if ((js2[js2_tiedly]) >= 0x1e) dataS = 0x1e; else @@ -1474,8 +1438,8 @@ static void ddrtbl_load(void) ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, (dataS - 2)); - if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_OE_DLY, dataS); } @@ -1521,25 +1485,19 @@ static void ddrtbl_load(void) } } - /*********************************************************************** - DDRPHY INT START - ***********************************************************************/ + /* DDRPHY INT START */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { /* non */ } else { regif_pll_wa(); } - /*********************************************************************** - FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) - ***********************************************************************/ + /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); - /*********************************************************************** - SET DATA SLICE TABLE - ***********************************************************************/ + /* SET DATA SLICE TABLE */ for (slice = 0; slice < SLICE_CNT; slice++) { adr = DDR_PHY_SLICE_REGSET_OFS + @@ -1550,16 +1508,14 @@ static void ddrtbl_load(void) } } - /*********************************************************************** - SET ADR SLICE TABLE - ***********************************************************************/ + /* SET ADR SLICE TABLE */ adr = DDR_PHY_ADR_V_REGSET_OFS; for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); } - if (((prr_product == PRR_PRODUCT_M3) - || (prr_product == PRR_PRODUCT_M3N)) && + if (((prr_product == PRR_PRODUCT_M3) || + (prr_product == PRR_PRODUCT_M3N)) && ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40)) != 0x00)) { adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; @@ -1597,26 +1553,20 @@ static void ddrtbl_load(void) } } - /*********************************************************************** - SET ADRCTRL SLICE TABLE - ***********************************************************************/ + /* SET ADRCTRL SLICE TABLE */ adr = DDR_PHY_ADR_G_REGSET_OFS; for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); } - /*********************************************************************** - SET PI REGISTERS - ***********************************************************************/ + /* SET PI REGISTERS */ adr = DDR_PI_REGSET_OFS; for (i = 0; i < DDR_PI_REGSET_NUM; i++) { reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); } } -/******************************************************************************* - * CONFIGURE DDR REGISTERS - ******************************************************************************/ +/* CONFIGURE DDR REGISTERS */ static void ddr_config_sub(void) { uint32_t i; @@ -1627,9 +1577,7 @@ static void ddr_config_sub(void) const uint32_t _par_CALVL_DEVICE_MAP = 1; foreach_vch(ch) { - /*********************************************************************** - BOARD SETTINGS (DQ,DM,VREF_DRIVING) - ***********************************************************************/ + /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ for (slice = 0; slice < SLICE_CNT; slice++) { high_byte[slice] = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2; @@ -1650,9 +1598,7 @@ static void ddr_config_sub(void) } } - /*********************************************************************** - BOARD SETTINGS (CA,ADDR_SEL) - ***********************************************************************/ + /* BOARD SETTINGS (CA,ADDR_SEL) */ data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) | 0x00888888; @@ -1674,8 +1620,8 @@ static void ddr_config_sub(void) } /* --- ADR_ADDR_SEL --- */ - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) { data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; } else { data_l = 0; @@ -1719,9 +1665,7 @@ static void ddr_config_sub(void) ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l); } - /*********************************************************************** - BOARD SETTINGS (BYTE_ORDER_SEL) - ***********************************************************************/ + /* BOARD SETTINGS (BYTE_ORDER_SEL) */ if (prr_product == PRR_PRODUCT_M3) { /* --- DATA_BYTE_SWAP --- */ data_l = 0; @@ -1792,9 +1736,7 @@ static void ddr_config_sub_h3v1x(void) const uint16_t o_mr32_mr40 = 0x5a3c; foreach_vch(ch) { - /*********************************************************************** - BOARD SETTINGS (DQ,DM,VREF_DRIVING) - ***********************************************************************/ + /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ csmap = 0; for (slice = 0; slice < SLICE_CNT; slice++) { tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; @@ -1817,9 +1759,7 @@ static void ddr_config_sub_h3v1x(void) 0x01); } } - /*********************************************************************** - BOARD SETTINGS (CA,ADDR_SEL) - ***********************************************************************/ + /* BOARD SETTINGS (CA,ADDR_SEL) */ ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap; ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); @@ -1878,18 +1818,14 @@ static void ddr_config(void) } patt; uint16_t patm; - /*********************************************************************** - configure ddrphy registers - ***********************************************************************/ + /* configure ddrphy registers */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_config_sub_h3v1x(); } else { ddr_config_sub(); /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ } - /*********************************************************************** - WDQ_USER_PATT - ***********************************************************************/ + /* WDQ_USER_PATT */ foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { patm = 0; @@ -1911,9 +1847,7 @@ static void ddr_config(void) } } - /*********************************************************************** - CACS DLY - ***********************************************************************/ + /* CACS DLY */ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U); foreach_vch(ch) { @@ -1923,11 +1857,11 @@ static void ddr_config(void) _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], data_l + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), - _cnf_DDR_PHY_ADR_V_REGSET[ - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - + ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), + _cnf_DDR_PHY_ADR_V_REGSET + [ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_V_REGSET_OFS]); } @@ -1938,29 +1872,30 @@ static void ddr_config(void) _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], data_l + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), - _cnf_DDR_PHY_ADR_G_REGSET[ - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - + ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), + _cnf_DDR_PHY_ADR_G_REGSET + [ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_G_REGSET_OFS]); } if (ddr_phycaslice == 1) { for (i = 0; i < 6; i++) { - adj = _f_scale_adj( - board_cnf->ch[ch].cacs_adj[ - i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); + adj = _f_scale_adj + (board_cnf->ch[ch].cacs_adj + [i + + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], data_l + adj); reg_ddrphy_write(ch, - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + + ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + 0x0100, - _cnf_DDR_PHY_ADR_V_REGSET[ - ddr_regdef_adr( - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - + _cnf_DDR_PHY_ADR_V_REGSET + [ddr_regdef_adr + (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_V_REGSET_OFS]); } } @@ -1969,9 +1904,7 @@ static void ddr_config(void) reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); - /*********************************************************************** - WDQDM DLY - ***********************************************************************/ + /* WDQDM DLY */ data_l = board_cnf->dqdm_dly_w; foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -1989,9 +1922,7 @@ static void ddr_config(void) } } - /*********************************************************************** - RDQDM DLY - ***********************************************************************/ + /* RDQDM DLY */ data_l = board_cnf->dqdm_dly_r; foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -2013,17 +1944,13 @@ static void ddr_config(void) } } -/******************************************************************************* - * DBSC register setting functions - ******************************************************************************/ +/* DBSC register setting functions */ static void dbsc_regset_pre(void) { uint32_t ch, csab; uint32_t data_l; - /*********************************************************************** - PRIMARY SETTINGS - ***********************************************************************/ + /* PRIMARY SETTINGS */ /* LPDDR4, BL=16, DFI interface */ mmio_write_32(DBSC_DBKIND, 0x0000000a); mmio_write_32(DBSC_DBBL, 0x00000002); @@ -2069,8 +1996,8 @@ static void dbsc_regset(void) uint32_t tmp[4]; /* RFC */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) - && (max_density == 0)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) && + (max_density == 0)) { js2[js2_trfcab] = _f_scale(ddr_mbps, ddr_mbpsdiv, 1UL * jedec_spec2_trfc_ab[1] * 1000, 0); @@ -2219,8 +2146,8 @@ static void dbsc_regset(void) for (i = 0; i < 4; i++) { data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_11) && (i == 0)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11) && (i == 0)) { data_l += 1; } data_l2 = 0; @@ -2231,9 +2158,7 @@ static void dbsc_regset(void) } mmio_write_32(DBSC_DBADJ0, 0x00000000); - /*********************************************************************** - timing registers for Scheduler - ***********************************************************************/ + /* timing registers for Scheduler */ /* SCFCTST0 */ /* SCFCTST0 ACT-ACT */ tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps; @@ -2285,9 +2210,7 @@ static void dbsc_regset(void) * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps); } - /*********************************************************************** - QOS and CAM - ***********************************************************************/ + /* QOS and CAM */ #ifdef ddr_qos_init_setting /* only for non qos_init */ /*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */ mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); @@ -2418,9 +2341,11 @@ static void dbsc_regset_post(void) mmio_write_32(DBSC_DBDBICNT, 0x00000003); /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ - if ((((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) && (board_cnf->dbi_en)) + if ((((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) && + board_cnf->dbi_en) reg_ddrphy_write_a(0x00001010, 0x01000000); /*set REFCYCLE */ @@ -2461,11 +2386,16 @@ static void dbsc_regset_post(void) #if RCAR_REWT_TRAINING != 0 /* Periodic-WriteDQ Training seeting */ - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut == PRR_PRODUCT_10))) { /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ } else { - /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H -> Periodic-WriteDQ Training seeting */ + /* + * H3 Ver.2.0 or later/M3-W Ver.1.1 or + * later/M3-N/V3H -> Periodic-WriteDQ Training seeting + */ /* Periodic WriteDQ Training seeting */ mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000); @@ -2499,13 +2429,15 @@ static void dbsc_regset_post(void) #endif /* RCAR_REWT_TRAINING */ /* periodic dram zqcal and phy ctrl update enable */ mmio_write_32(DBSC_DBCALCNF, 0x01000010); - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { #if RCAR_DRAM_SPLIT == 2 - if ((prr_product == PRR_PRODUCT_H3) - && (board_cnf->phyvalid == 0x05)) + if ((prr_product == PRR_PRODUCT_H3) && + (board_cnf->phyvalid == 0x05)) mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); else mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); @@ -2522,9 +2454,7 @@ static void dbsc_regset_post(void) } -/******************************************************************************* - * DFI_INIT_START - ******************************************************************************/ +/* DFI_INIT_START */ static uint32_t dfi_init_start(void) { uint32_t ch; @@ -2534,17 +2464,13 @@ static uint32_t dfi_init_start(void) const uint32_t RETRY_MAX = 0x10000; if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - /*********************************************************************** - PLL3 Disable - ***********************************************************************/ + /* PLL3 Disable */ /* protect register interface */ ddrphy_regif_idle(); pll3_control(0); - /*********************************************************************** - init start - ***********************************************************************/ + /* init start */ /* dbdficnt0: * dfi_dram_clk_disable=1 * dfi_frequency = 0 @@ -2576,9 +2502,7 @@ static uint32_t dfi_init_start(void) mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01); dsb_sev(); - /*********************************************************************** - wait init_complete - ***********************************************************************/ + /* wait init_complete */ phytrainingok = 0; retry = 0; while (retry++ < RETRY_MAX) { @@ -2594,12 +2518,10 @@ static uint32_t dfi_init_start(void) ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); } - /*********************************************************************** - all ch ok? - ***********************************************************************/ - if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) { - return (0xff); - } + /* all ch ok? */ + if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) + return 0xff; + /* dbdficnt0: * dfi_dram_clk_disable=0 * dfi_frequency = 0 @@ -2613,9 +2535,7 @@ static uint32_t dfi_init_start(void) return 0; } -/******************************************************************************* - * drivablity setting : CMOS MODE ON/OFF - ******************************************************************************/ +/* drivablity setting : CMOS MODE ON/OFF */ static void change_lpddr4_en(uint32_t mode) { uint32_t ch; @@ -2640,9 +2560,7 @@ static void change_lpddr4_en(uint32_t mode) } } -/******************************************************************************* - * drivablity setting - ******************************************************************************/ +/* drivablity setting */ static uint32_t set_term_code(void) { int32_t i; @@ -2666,8 +2584,8 @@ static uint32_t set_term_code(void) if (termcode_by_sample[index][0] == 0xffffffff) { break; } - if ((termcode_by_sample[index][0] == chip_id[0]) - && (termcode_by_sample[index][1] == chip_id[1])) { + if ((termcode_by_sample[index][0] == chip_id[0]) && + (termcode_by_sample[index][1] == chip_id[1])) { term_code = termcode_by_sample[index][2]; override = 1; break; @@ -2683,8 +2601,8 @@ static uint32_t set_term_code(void) data_l = (data_l & 0xfffe0000) | term_code; ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l); } - } else if ((prr_product == PRR_PRODUCT_M3) - && (prr_cut == PRR_PRODUCT_10)) { + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut == PRR_PRODUCT_10)) { /* non */ } else { ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], @@ -2699,8 +2617,8 @@ static uint32_t set_term_code(void) ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); } while (!(data_l & 0x00800000)); } - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); pvtr = (data_l >> 12) & 0x1f; @@ -2743,17 +2661,17 @@ static uint32_t set_term_code(void) } } } + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - /* non */ + /* non */ } else { ddr_padcal_tcompensate_getinit(override); } + return 0; } -/******************************************************************************* - * DDR mode register setting - ******************************************************************************/ +/* DDR mode register setting */ static void ddr_register_set(void) { int32_t fspwp; @@ -2797,9 +2715,7 @@ static void ddr_register_set(void) } } -/******************************************************************************* - * Training handshake functions - ******************************************************************************/ +/* Training handshake functions */ static inline uint32_t wait_freqchgreq(uint32_t assert) { uint32_t data_l; @@ -2871,7 +2787,7 @@ static uint32_t pll3_freq(uint32_t on) timeout = wait_freqchgreq(1); if (timeout) { - return (1); + return 1; } pll3_control(on); @@ -2883,23 +2799,19 @@ static uint32_t pll3_freq(uint32_t on) if (timeout) { FATAL_MSG("BL2: Time out[2]\n"); - return (1); + return 1; } - return (0); + return 0; } -/******************************************************************************* - * update dly - ******************************************************************************/ +/* update dly */ static void update_dly(void) { ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01); ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01); } -/******************************************************************************* - * training by pi - ******************************************************************************/ +/* training by pi */ static uint32_t pi_training_go(void) { uint32_t flag; @@ -2913,11 +2825,7 @@ static uint32_t pi_training_go(void) uint32_t complete; uint32_t frqchg_req; - /* ********************************************************************* */ - - /*********************************************************************** - pi_start - ***********************************************************************/ + /* pi_start */ ddr_setval_ach(_reg_PI_START, 0x01); foreach_vch(ch) ddr_getval(ch, _reg_PI_INT_STATUS); @@ -2926,9 +2834,7 @@ static uint32_t pi_training_go(void) mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001); dsb_sev(); - /*********************************************************************** - wait pi_int_status[0] - ***********************************************************************/ + /* wait pi_int_status[0] */ mst_ch = 0; flag = 0; complete = 0; @@ -2938,8 +2844,8 @@ static uint32_t pi_training_go(void) frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; /* H3 Ver.1.x cannot see frqchg_req */ - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { if ((retry % 4096) == 1) { frqchg_req = 1; } else { @@ -2982,14 +2888,12 @@ static uint32_t pi_training_go(void) ddr_setval(ch, _reg_PI_INT_ACK, data_l); } if (ddrphy_regif_chk()) { - return (0xfd); + return 0xfd; } return complete; } -/******************************************************************************* - * Initialize ddr - ******************************************************************************/ +/* Initialize DDR */ static uint32_t init_ddr(void) { int32_t i; @@ -3005,68 +2909,51 @@ static uint32_t init_ddr(void) rcar_dram_get_boot_status(&ddr_backup); #endif - /*********************************************************************** - unlock phy - ***********************************************************************/ + /* unlock phy */ /* Unlock DDRPHY register(AGAIN) */ foreach_vch(ch) mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); dsb_sev(); - if ((((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) && (board_cnf->dbi_en)) + if ((((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en) reg_ddrphy_write_a(0x00001010, 0x01000001); else reg_ddrphy_write_a(0x00001010, 0x00000001); - /*********************************************************************** - dbsc register pre-setting - ***********************************************************************/ + /* DBSC register pre-setting */ dbsc_regset_pre(); - /*********************************************************************** - load ddrphy registers - ***********************************************************************/ + /* load ddrphy registers */ ddrtbl_load(); - /*********************************************************************** - configure ddrphy registers - ***********************************************************************/ + /* configure ddrphy registers */ ddr_config(); - /*********************************************************************** - dfi_reset assert - ***********************************************************************/ + /* dfi_reset assert */ foreach_vch(ch) mmio_write_32(DBSC_DBPDCNT0(ch), 0x01); dsb_sev(); - /*********************************************************************** - dbsc register set - ***********************************************************************/ + /* dbsc register set */ dbsc_regset(); MSG_LF("init_ddr:1\n"); - /*********************************************************************** - dfi_reset negate - ***********************************************************************/ + /* dfi_reset negate */ foreach_vch(ch) mmio_write_32(DBSC_DBPDCNT0(ch), 0x00); dsb_sev(); - /*********************************************************************** - dfi_init_start (start ddrphy) - ***********************************************************************/ + /* dfi_init_start (start ddrphy) */ err = dfi_init_start(); if (err) { return INITDRAM_ERR_I; } MSG_LF("init_ddr:2\n"); - /*********************************************************************** - ddr backupmode end - ***********************************************************************/ + /* ddr backupmode end */ #ifdef DDR_BACKUPMODE if (ddr_backup) { NOTICE("BL2: [WARM_BOOT]\n"); @@ -3081,47 +2968,37 @@ static uint32_t init_ddr(void) #endif MSG_LF("init_ddr:3\n"); - /*********************************************************************** - override term code after dfi_init_complete - ***********************************************************************/ + /* override term code after dfi_init_complete */ err = set_term_code(); if (err) { return INITDRAM_ERR_I; } MSG_LF("init_ddr:4\n"); - /*********************************************************************** - rx offset calibration - ***********************************************************************/ - if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + /* rx offset calibration */ + if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { err = rx_offset_cal_hw(); } else { err = rx_offset_cal(); } if (err) - return (INITDRAM_ERR_O); + return INITDRAM_ERR_O; MSG_LF("init_ddr:5\n"); /* PDX */ send_dbcmd(0x08840001); - /*********************************************************************** - check register i/f is alive - ***********************************************************************/ + /* check register i/f is alive */ err = ddrphy_regif_chk(); if (err) { - return (INITDRAM_ERR_O); + return INITDRAM_ERR_O; } MSG_LF("init_ddr:6\n"); - /*********************************************************************** - phy initialize end - ***********************************************************************/ + /* phy initialize end */ - /*********************************************************************** - setup DDR mode registers - ***********************************************************************/ + /* setup DDR mode registers */ /* CMOS MODE */ change_lpddr4_en(0); @@ -3134,9 +3011,7 @@ static uint32_t init_ddr(void) /* ZQLAT */ send_dbcmd(0x0d840051); - /*********************************************************************** - Thermal sensor setting - ***********************************************************************/ + /* Thermal sensor setting */ /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; mmio_write_32(THS1_THCTR, data_l); @@ -3146,9 +3021,7 @@ static uint32_t init_ddr(void) MSG_LF("init_ddr:7\n"); - /*********************************************************************** - mask CS_MAP if RANKx is not found - ***********************************************************************/ + /* mask CS_MAP if RANKx is not found */ foreach_vch(ch) { data_l = ddr_getval(ch, _reg_PI_CS_MAP); if (!(ch_have_this_cs[1] & (1U << ch))) @@ -3156,9 +3029,7 @@ static uint32_t init_ddr(void) ddr_setval(ch, _reg_PI_CS_MAP, data_l); } - /*********************************************************************** - exec pi_training - ***********************************************************************/ + /* exec pi_training */ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); @@ -3179,14 +3050,12 @@ static uint32_t init_ddr(void) phytrainingok = pi_training_go(); if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) { - return (INITDRAM_ERR_T | phytrainingok); + return INITDRAM_ERR_T | phytrainingok; } MSG_LF("init_ddr:8\n"); - /*********************************************************************** - CACS DLY ADJUST - ***********************************************************************/ + /* CACS DLY ADJUST */ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); foreach_vch(ch) { for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { @@ -3208,23 +3077,17 @@ static uint32_t init_ddr(void) update_dly(); MSG_LF("init_ddr:9\n"); - /*********************************************************************** - H3 fix rd latency to avoid bug in elasitic buffe - ***********************************************************************/ + /* H3 fix rd latency to avoid bug in elasitic buffer */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { adjust_rddqs_latency(); } - /*********************************************************************** - Adjust Write path latency - ***********************************************************************/ + /* Adjust Write path latency */ if (ddrtbl_getval (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) adjust_wpath_latency(); - /*********************************************************************** - RDQLVL Training - ***********************************************************************/ + /* RDQLVL Training */ if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) { ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); } @@ -3236,27 +3099,23 @@ static uint32_t init_ddr(void) } if (err) { - return (INITDRAM_ERR_T); + return INITDRAM_ERR_T; } update_dly(); MSG_LF("init_ddr:10\n"); - /*********************************************************************** - WDQLVL Training - ***********************************************************************/ + /* WDQLVL Training */ err = wdqdm_man(); if (err) { - return (INITDRAM_ERR_T); + return INITDRAM_ERR_T; } update_dly(); MSG_LF("init_ddr:11\n"); - /*********************************************************************** - training complete, setup dbsc - ***********************************************************************/ - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + /* training complete, setup DBSC */ + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); } @@ -3267,9 +3126,7 @@ static uint32_t init_ddr(void) return phytrainingok; } -/******************************************************************************* - * SW LEVELING COMMON - ******************************************************************************/ +/* SW LEVELING COMMON */ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) { uint32_t ch; @@ -3320,9 +3177,7 @@ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) return err; } -/******************************************************************************* - * WDQ TRAINING - ******************************************************************************/ +/* WDQ TRAINING */ #ifndef DDR_FAST_INIT static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) { @@ -3330,9 +3185,7 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) uint32_t cs, slice; uint32_t data_l; - /*********************************************************************** - clr of training results buffer - ***********************************************************************/ + /* clr of training results buffer */ cs = ddr_csn % 2; data_l = board_cnf->dqdm_dly_w; for (slice = 0; slice < SLICE_CNT; slice++) { @@ -3368,9 +3221,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) int16_t adj; uint32_t dq; - /*********************************************************************** - analysis of training results - ***********************************************************************/ + /* analysis of training results */ err = 0; for (slice = 0; slice < SLICE_CNT; slice += 1) { k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; @@ -3437,9 +3288,7 @@ static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) uint32_t tgt_cs, src_cs; uint32_t tmp_r; - /*********************************************************************** - copy of training results - ***********************************************************************/ + /* copy of training results */ foreach_vch(ch) { for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -3481,9 +3330,7 @@ static uint32_t wdqdm_man1(void) uint32_t err_flg; #endif/* DDR_FAST_INIT */ - /*********************************************************************** - manual execution of training - ***********************************************************************/ + /* manual execution of training */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { high_dq[ch] = 0; @@ -3499,10 +3346,10 @@ static uint32_t wdqdm_man1(void) /* CLEAR PREV RESULT */ for (cs = 0; cs < CS_CNT; cs++) { ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); - if (((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01); } else { @@ -3516,8 +3363,8 @@ static uint32_t wdqdm_man1(void) err_flg = 0; #endif/* DDR_FAST_INIT */ for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { foreach_vch(ch) { data_l = mmio_read_32(DBSC_DBDFICNT(ch)); data_l &= ~(0x00ffU << 16); @@ -3531,10 +3378,10 @@ static uint32_t wdqdm_man1(void) ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); } } - if (((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) - && (prr_cut == PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut == PRR_PRODUCT_10))) { wdqdm_cp(ddr_csn, 0); } @@ -3585,7 +3432,7 @@ err_exit: ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); } } - return (err); + return err; } static uint32_t wdqdm_man(void) @@ -3595,9 +3442,9 @@ static uint32_t wdqdm_man(void) uint32_t ch, ddr_csn, mr14_bkup[4][4]; ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12); - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, (DBSC_DBTR(12) & 0xFF) + 1); } else { @@ -3609,15 +3456,15 @@ static uint32_t wdqdm_man(void) retry_cnt = 0; err = 0; do { - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { err = wdqdm_man1(); } else { ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x01); - if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x0C); } else { @@ -3635,8 +3482,8 @@ static uint32_t wdqdm_man(void) } } - if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x04); } else { @@ -3660,8 +3507,8 @@ static uint32_t wdqdm_man(void) ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x00); - if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x00); ddr_setval_ach @@ -3688,17 +3535,15 @@ static uint32_t wdqdm_man(void) } } while (err && (++retry_cnt < retry_max)); - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) { wdqdm_cp(0, 1); } return (retry_cnt >= retry_max); } -/******************************************************************************* - * RDQ TRAINING - ******************************************************************************/ +/* RDQ TRAINING */ #ifndef DDR_FAST_INIT static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) { @@ -3706,9 +3551,7 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) uint32_t cs, slice; uint32_t data_l; - /*********************************************************************** - clr of training results buffer - ***********************************************************************/ + /* clr of training results buffer */ cs = ddr_csn % 2; data_l = board_cnf->dqdm_dly_r; for (slice = 0; slice < SLICE_CNT; slice++) { @@ -3753,9 +3596,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) int32_t win; uint32_t rdq_status_obs_select; - /*********************************************************************** - analysis of training results - ***********************************************************************/ + /* analysis of training results */ err = 0; for (slice = 0; slice < SLICE_CNT; slice++) { k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; @@ -3847,7 +3688,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) err = 2; } } - return (err); + return err; } #endif/* DDR_FAST_INIT */ @@ -3861,9 +3702,7 @@ static uint32_t rdqdm_man1(void) #endif/* DDR_FAST_INIT */ uint32_t err; - /*********************************************************************** - manual execution of training - ***********************************************************************/ + /* manual execution of training */ err = 0; for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { @@ -3896,10 +3735,10 @@ static uint32_t rdqdm_man1(void) } } } - if (((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) - && (prr_cut <= PRR_PRODUCT_10))) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && + (prr_cut <= PRR_PRODUCT_10))) { for (slice = 0; slice < SLICE_CNT; slice++) { for (i = 0; i <= 8; i++) { if (i == 8) @@ -3926,7 +3765,7 @@ static uint32_t rdqdm_man1(void) } err_exit: - return (err); + return err; } static uint32_t rdqdm_man(void) @@ -3968,9 +3807,7 @@ static uint32_t rdqdm_man(void) return (retry_cnt >= retry_max); } -/******************************************************************************* - * rx offset calibration - ******************************************************************************/ +/* rx offset calibration */ static int32_t _find_change(uint64_t val, uint32_t dir) { int32_t i; @@ -3983,17 +3820,17 @@ static int32_t _find_change(uint64_t val, uint32_t dir) for (i = 1; i <= VAL_END; i++) { curval = (val >> i) & 0x01; if (curval != startval) - return (i); + return i; } - return (VAL_END); + return VAL_END; } else { startval = (val >> dir) & 0x01; for (i = dir - 1; i >= 0; i--) { curval = (val >> i) & 0x01; if (curval != startval) - return (i); + return i; } - return (0); + return 0; } } @@ -4116,10 +3953,10 @@ static uint32_t rx_offset_cal_hw(void) for (slice = 0; slice < SLICE_CNT; slice++) { tmp = tmp_ach_as[ch][slice]; tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); - if (((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_11)) - || (prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + if (((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_11)) || + (prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { if (tmp != 0x3E) complete = 0; } else { @@ -4137,9 +3974,7 @@ static uint32_t rx_offset_cal_hw(void) return (complete == 0); } -/******************************************************************************* - * adjust rddqs latency - ******************************************************************************/ +/* adjust rddqs latency */ static void adjust_rddqs_latency(void) { uint32_t ch, slice; @@ -4180,9 +4015,7 @@ static void adjust_rddqs_latency(void) } } -/******************************************************************************* - * adjust wpath latency - ******************************************************************************/ +/* adjust wpath latency */ static void adjust_wpath_latency(void) { uint32_t ch, cs, slice; @@ -4215,9 +4048,7 @@ static void adjust_wpath_latency(void) } } -/******************************************************************************* - * DDR Initialize entry - ******************************************************************************/ +/* DDR Initialize entry */ int32_t rcar_dram_init(void) { uint32_t ch, cs; @@ -4227,23 +4058,20 @@ int32_t rcar_dram_init(void) uint32_t failcount; uint32_t cnf_boardtype; - /*********************************************************************** - Thermal sensor setting - ***********************************************************************/ + /* Thermal sensor setting */ data_l = mmio_read_32(CPG_MSTPSR5); if (data_l & BIT(22)) { /* case THS/TSC Standby */ - data_l &= ~(BIT(22)); + data_l &= ~BIT(22); cpg_write_32(CPG_SMSTPCR5, data_l); - while ((BIT(22)) & mmio_read_32(CPG_MSTPSR5)); /* wait bit=0 */ + while (mmio_read_32(CPG_MSTPSR5) & BIT(22)) + ; /* wait bit=0 */ } /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; mmio_write_32(THS1_THCTR, data_l); - /*********************************************************************** - Judge product and cut - ***********************************************************************/ + /* Judge product and cut */ #ifdef RCAR_DDR_FIXED_LSI_TYPE #if (RCAR_LSI == RCAR_AUTO) prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; @@ -4266,24 +4094,22 @@ int32_t rcar_dram_init(void) } } else if (prr_product == PRR_PRODUCT_M3) { p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[1][0]; - } else if ((prr_product == PRR_PRODUCT_M3N) - || (prr_product == PRR_PRODUCT_V3H)) { + } else if ((prr_product == PRR_PRODUCT_M3N) || + (prr_product == PRR_PRODUCT_V3H)) { p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[3][0]; } else { FATAL_MSG("BL2: DDR:Unknown Product\n"); return 0xff; } - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); } - /*********************************************************************** - Judge board type - ***********************************************************************/ + /* Judge board type */ cnf_boardtype = boardcnf_get_brd_type(); if (cnf_boardtype >= BOARDNUM) { FATAL_MSG("BL2: DDR:Unknown Board\n"); @@ -4293,9 +4119,7 @@ int32_t rcar_dram_init(void) /* RCAR_DRAM_SPLIT_2CH (2U) */ #if RCAR_DRAM_SPLIT == 2 - /*********************************************************************** - H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split - ***********************************************************************/ + /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */ if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) { mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); ddr_phyvalid = 0x03; @@ -4325,16 +4149,14 @@ int32_t rcar_dram_init(void) continue; if (data_l > max_density) max_density = data_l; - if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) + if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) continue; ch_have_this_cs[cs] |= (1U << ch); } } - /*********************************************************************** - Judge board clock frequency (in MHz) - ***********************************************************************/ + /* Judge board clock frequency (in MHz) */ boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv); if ((brd_clk / brd_clkdiv) > 25) { brd_clkdiva = 1; @@ -4342,9 +4164,7 @@ int32_t rcar_dram_init(void) brd_clkdiva = 0; } - /*********************************************************************** - Judge ddr operating frequency clock(in Mbps) - ***********************************************************************/ + /* Judge ddr operating frequency clock(in Mbps) */ boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv); ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); @@ -4352,9 +4172,7 @@ int32_t rcar_dram_init(void) ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); - /*********************************************************************** - Adjust tccd - ***********************************************************************/ + /* Adjust tccd */ data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; bus_mbps = 0; bus_mbpsdiv = 0; @@ -4393,14 +4211,10 @@ int32_t rcar_dram_init(void) MSG_LF("Start\n"); - /*********************************************************************** - PLL Setting - ***********************************************************************/ + /* PLL Setting */ pll3_control(1); - /*********************************************************************** - initialize DDR - ***********************************************************************/ + /* initialize DDR */ data_l = init_ddr(); if (data_l == ddr_phyvalid) { failcount = 0; @@ -4410,8 +4224,8 @@ int32_t rcar_dram_init(void) foreach_vch(ch) mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); - if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) - || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { + if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) || + ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) { /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ } else { mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); @@ -4453,8 +4267,8 @@ void pvtcode_update(void) pvtn_init) / (pvtn_tmp) + 6 * pvtp_tmp + pvtp_init; } - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { data_l = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), @@ -4556,8 +4370,8 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) else pvtn = 0; - if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { tcal.init_cal[ch] = (tcal. init_cal[ch] & 0xfffff000) | (pvtn << 6) | @@ -4578,7 +4392,3 @@ uint8_t get_boardcnf_phyvalid(void) return ddr_phyvalid; } #endif /* ddr_qos_init_setting */ - -/******************************************************************************* - * END - ******************************************************************************/ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index cb3a482e..52dbac32 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -17,7 +17,7 @@ static uint32_t boardcnf_get_brd_type(void) #else static uint32_t boardcnf_get_brd_type(void) { - return (1); + return 1; } #endif @@ -1630,7 +1630,8 @@ static void pfc_write_and_poll(uint32_t a, uint32_t v) mmio_write_32(PFC_PMMR, ~v); v = ~mmio_read_32(PFC_PMMR); mmio_write_32(a, v); - while (v != mmio_read_32(a)); + while (v != mmio_read_32(a)) + ; dsb_sev(); } #endif @@ -1688,10 +1689,10 @@ static uint32_t opencheck_SSI_WS6(void) if (down == up) { /* Same = Connect */ return 0; - } else { - /* Diff = Open */ - return 1; } + + /* Diff = Open */ + return 1; } #endif @@ -1737,12 +1738,12 @@ static uint32_t _board_judge(void) } else if (prr_product == PRR_PRODUCT_M3) { /* RENESAS Kriek board with M3-W */ brd = 1; - } else if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut <= PRR_PRODUCT_11)) { + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { /* RENESAS Kriek board with PM3 */ brd = 13; - } else if ((prr_product == PRR_PRODUCT_H3) - && (prr_cut > PRR_PRODUCT_20)) { + } else if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut > PRR_PRODUCT_20)) { /* RENESAS Kriek board with H3N */ brd = 15; } -- cgit v1.2.3 From 4ca57bae2749cfffee64899358a9f7f62772bc68 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Aug 2019 16:34:22 +0200 Subject: rcar_gen3: drivers: ddr_b: Fix line-over-80s Fix as many line-over-80s as possible. There are still a few remaining, which would need further refactoring. Signed-off-by: Marek Vasut Change-Id: I7225d9fab658d05e3315d8c3fa3c9f3bbb1ab40d --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 229 ++++++++++++--------- .../renesas/rcar/ddr/ddr_b/boot_init_dram_config.c | 22 +- 2 files changed, 152 insertions(+), 99 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index d1068729..9c7f9c8a 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -155,7 +156,8 @@ static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { }; #define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 -static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY + [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, @@ -169,7 +171,8 @@ static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_ }; #define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 -static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY + [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, @@ -182,7 +185,8 @@ static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SL }; #define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 -static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { +static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY + [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, @@ -207,7 +211,8 @@ static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { }; #define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 -static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { +static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X + [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, @@ -755,8 +760,8 @@ static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) pp = p; foreach_vch(ch) - for (slice = 0; slice < SLICE_CNT; slice++) - *pp++ = ddr_getval_s(ch, slice, regdef); + for (slice = 0; slice < SLICE_CNT; slice++) + *pp++ = ddr_getval_s(ch, slice, regdef); return p[0]; } @@ -873,14 +878,22 @@ struct _jedec_spec1 { #define JS1_MR1(f) (0x04 | ((f) << 4)) #define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { - { 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 }, /* 533.333Mbps */ - { 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 }, /* 1066.666Mbps */ - { 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 }, /* 1600.000Mbps */ - { 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) }, /* 2133.333Mbps */ - { 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) }, /* 2666.666Mbps */ - { 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) }, /* 3200.000Mbps */ - { 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) }, /* 3733.333Mbps */ - { 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) } /* 4266.666Mbps */ + /* 533.333Mbps */ + { 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 }, + /* 1066.666Mbps */ + { 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 }, + /* 1600.000Mbps */ + { 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 }, + /* 2133.333Mbps */ + { 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) }, + /* 2666.666Mbps */ + { 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) }, + /* 3200.000Mbps */ + { 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) }, + /* 3733.333Mbps */ + { 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) }, + /* 4266.666Mbps */ + { 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) } }; struct _jedec_spec2 { @@ -1494,7 +1507,7 @@ static void ddrtbl_load(void) /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); /* SET DATA SLICE TABLE */ @@ -1523,7 +1536,8 @@ static void ddrtbl_load(void) reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); } - ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_ADR_DISABLE, 0x02); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, + _reg_PHY_ADR_DISABLE, 0x02); DDR_PHY_ADR_I_NUM -= 1; ddr_phycaslice = 1; @@ -1639,19 +1653,30 @@ static void ddr_config_sub(void) /* --- ADR_CALVL_SWIZZLE --- */ if (prr_product == PRR_PRODUCT_M3) { - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0, + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE0_0, + data_l); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1, + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE0_1, + data_l); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP, + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); } else { - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1, + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE0, + data_l); + ddr_setval_s(ch, 2, + _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP, + ddr_setval_s(ch, 2, + _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); } @@ -1739,7 +1764,8 @@ static void ddr_config_sub_h3v1x(void) /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */ csmap = 0; for (slice = 0; slice < SLICE_CNT; slice++) { - tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & + 0x0f; high_byte[slice] = tmp % 2; if (tmp == 1 && (slice >= 2)) csmap |= 0x05; @@ -1821,8 +1847,8 @@ static void ddr_config(void) /* configure ddrphy registers */ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { ddr_config_sub_h3v1x(); - } else { - ddr_config_sub(); /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ + } else { /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ + ddr_config_sub(); } /* WDQ_USER_PATT */ @@ -1849,9 +1875,10 @@ static void ddr_config(void) /* CACS DLY */ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), + 0x00U); foreach_vch(ch) { - for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) { + for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) { adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]); ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], @@ -1887,7 +1914,8 @@ static void ddr_config(void) [i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, - _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], + _reg_PHY_CLK_CACS_SLAVE_DELAY_X + [i], data_l + adj); reg_ddrphy_write(ch, ddr_regdef_adr @@ -1902,7 +1930,7 @@ static void ddr_config(void) } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); /* WDQDM DLY */ data_l = board_cnf->dqdm_dly_w; @@ -1966,9 +1994,12 @@ static void dbsc_regset_pre(void) /* DRAM SIZE REGISTER: * set all ranks as density=0(4Gb) for PHY initialization */ - foreach_vch(ch) - for (csab = 0; csab < 4; csab++) - mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0)); + foreach_vch(ch) { + for (csab = 0; csab < 4; csab++) { + mmio_write_32(DBSC_DBMEMCONF(ch, csab), + DBMEMCONF_REGD(0)); + } + } if (prr_product == PRR_PRODUCT_M3) { data_l = 0xe4e4e4e4; @@ -2203,11 +2234,13 @@ static void dbsc_regset(void) if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { mmio_write_32(DBSC_DBSCHRW1, tmp[0] + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3); + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / + ddr_mbps - 3); } else { mmio_write_32(DBSC_DBSCHRW1, tmp[0] + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps); + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / + ddr_mbps); } /* QOS and CAM */ @@ -2296,9 +2329,8 @@ static void dbsc_regset_post(void) ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); - data_l = - ddr_getval_s(ch, slice, - _reg_PHY_RDDQS_LATENCY_ADJUST); + data_l = ddr_getval_s(ch, slice, + _reg_PHY_RDDQS_LATENCY_ADJUST); if (data_l > rdlat_max) rdlat_max = data_l; if (data_l < rdlat_min) @@ -2424,7 +2456,8 @@ static void dbsc_regset_post(void) ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01); /* DFI_PHYMSTR_ACK , WTmode setting */ - mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); /* DFI_PHYMSTR_ACK: WTmode =b'01 */ + /* DFI_PHYMSTR_ACK: WTmode =b'01 */ + mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); } #endif /* RCAR_REWT_TRAINING */ /* periodic dram zqcal and phy ctrl update enable */ @@ -2450,8 +2483,7 @@ static void dbsc_regset_post(void) /* dram access enable */ mmio_write_32(DBSC_DBACEN, 0x00000001); - MSG_LF("dbsc_regset_post(done)"); - + MSG_LF(__func__ "(done)"); } /* DFI_INIT_START */ @@ -2645,7 +2677,8 @@ static uint32_t set_term_code(void) data_l); } } - } else { /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ + } else { + /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ foreach_vch(ch) { for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { @@ -2903,7 +2936,7 @@ static uint32_t init_ddr(void) uint32_t err; int16_t adj; - MSG_LF("init_ddr:0\n"); + MSG_LF(__func__ ":0\n"); #ifdef DDR_BACKUPMODE rcar_dram_get_boot_status(&ddr_backup); @@ -2939,7 +2972,7 @@ static uint32_t init_ddr(void) /* dbsc register set */ dbsc_regset(); - MSG_LF("init_ddr:1\n"); + MSG_LF(__func__ ":1\n"); /* dfi_reset negate */ foreach_vch(ch) @@ -2951,7 +2984,7 @@ static uint32_t init_ddr(void) if (err) { return INITDRAM_ERR_I; } - MSG_LF("init_ddr:2\n"); + MSG_LF(__func__ ":2\n"); /* ddr backupmode end */ #ifdef DDR_BACKUPMODE @@ -2966,14 +2999,14 @@ static uint32_t init_ddr(void) return INITDRAM_ERR_I; } #endif - MSG_LF("init_ddr:3\n"); + MSG_LF(__func__ ":3\n"); /* override term code after dfi_init_complete */ err = set_term_code(); if (err) { return INITDRAM_ERR_I; } - MSG_LF("init_ddr:4\n"); + MSG_LF(__func__ ":4\n"); /* rx offset calibration */ if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) || @@ -2984,7 +3017,7 @@ static uint32_t init_ddr(void) } if (err) return INITDRAM_ERR_O; - MSG_LF("init_ddr:5\n"); + MSG_LF(__func__ ":5\n"); /* PDX */ send_dbcmd(0x08840001); @@ -2994,7 +3027,7 @@ static uint32_t init_ddr(void) if (err) { return INITDRAM_ERR_O; } - MSG_LF("init_ddr:6\n"); + MSG_LF(__func__ ":6\n"); /* phy initialize end */ @@ -3019,7 +3052,7 @@ static uint32_t init_ddr(void) /* LPDDR4 MODE */ change_lpddr4_en(1); - MSG_LF("init_ddr:7\n"); + MSG_LF(__func__ ":7\n"); /* mask CS_MAP if RANKx is not found */ foreach_vch(ch) { @@ -3035,7 +3068,7 @@ static uint32_t init_ddr(void) ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); } else { foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { @@ -3053,7 +3086,7 @@ static uint32_t init_ddr(void) return INITDRAM_ERR_T | phytrainingok; } - MSG_LF("init_ddr:8\n"); + MSG_LF(__func__ ":8\n"); /* CACS DLY ADJUST */ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj); @@ -3066,8 +3099,12 @@ static uint32_t init_ddr(void) if (ddr_phycaslice == 1) { for (i = 0; i < 6; i++) { - adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); - ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], + adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj + [i + + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); + ddr_setval_s(ch, 2, + _reg_PHY_CLK_CACS_SLAVE_DELAY_X + [i], data_l + adj ); } @@ -3075,12 +3112,11 @@ static uint32_t init_ddr(void) } update_dly(); - MSG_LF("init_ddr:9\n"); + MSG_LF(__func__ ":9\n"); /* H3 fix rd latency to avoid bug in elasitic buffer */ - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { + if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) adjust_rddqs_latency(); - } /* Adjust Write path latency */ if (ddrtbl_getval @@ -3088,21 +3124,19 @@ static uint32_t init_ddr(void) adjust_wpath_latency(); /* RDQLVL Training */ - if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) { + if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); - } err = rdqdm_man(); - if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) { + if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE)) ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00); - } if (err) { return INITDRAM_ERR_T; } update_dly(); - MSG_LF("init_ddr:10\n"); + MSG_LF(__func__ ":10\n"); /* WDQLVL Training */ err = wdqdm_man(); @@ -3110,7 +3144,7 @@ static uint32_t init_ddr(void) return INITDRAM_ERR_T; } update_dly(); - MSG_LF("init_ddr:11\n"); + MSG_LF(__func__ ":11\n"); /* training complete, setup DBSC */ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || @@ -3121,7 +3155,7 @@ static uint32_t init_ddr(void) } dbsc_regset_post(); - MSG_LF("init_ddr:12\n"); + MSG_LF(__func__ ":12\n"); return phytrainingok; } @@ -3270,8 +3304,10 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) err = 2; } wdqdm_win[ch][cs][slice] = min_win; - if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01); + if ((prr_product == PRR_PRODUCT_H3) && + (prr_cut <= PRR_PRODUCT_11)) { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, + 0x01); } else { ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, ((ch_have_this_cs[1]) >> ch) & 0x01); @@ -3335,7 +3371,8 @@ static uint32_t wdqdm_man1(void) foreach_vch(ch) { high_dq[ch] = 0; for (slice = 0; slice < SLICE_CNT; slice++) { - k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + k = (board_cnf->ch[ch].dqs_swap >> + (4 * slice)) & 0x0f; if (k >= 2) high_dq[ch] |= (1U << slice); } @@ -3569,7 +3606,8 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) [i]; } else { rdqdm_dly[ch][cs][slice][i] = data_l; - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l; + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = + data_l; } rdqdm_le[ch][cs][slice][i] = 0; rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; @@ -3674,8 +3712,8 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) win = (int32_t)rdqdm_te[ch][cs][slice + - SLICE_CNT * - k][i] - + SLICE_CNT * + k][i] - rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; if (i != 8) { if (min_win > win) @@ -3823,15 +3861,15 @@ static int32_t _find_change(uint64_t val, uint32_t dir) return i; } return VAL_END; - } else { - startval = (val >> dir) & 0x01; - for (i = dir - 1; i >= 0; i--) { - curval = (val >> i) & 0x01; - if (curval != startval) - return i; - } - return 0; } + + startval = (val >> dir) & 0x01; + for (i = dir - 1; i >= 0; i--) { + curval = (val >> i) & 0x01; + if (curval != startval) + return i; + } + return 0; } static uint32_t _rx_offset_cal_updn(uint32_t code) @@ -3875,9 +3913,8 @@ static uint32_t rx_offset_cal(void) ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01); foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) val[ch][slice][index] = 0; - } } } @@ -3907,7 +3944,8 @@ static uint32_t rx_offset_cal(void) } foreach_vch(ch) { for (slice = 0; slice < SLICE_CNT; slice++) { - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; + index++) { tmpval = val[ch][slice][index]; lsb = _find_change(tmpval, 0); msb = @@ -4088,15 +4126,19 @@ int32_t rcar_dram_init(void) if (prr_product == PRR_PRODUCT_H3) { if (prr_cut <= PRR_PRODUCT_11) { - p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[0][0]; + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[0][0]; } else { - p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[2][0]; + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[2][0]; } } else if (prr_product == PRR_PRODUCT_M3) { - p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[1][0]; + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[1][0]; } else if ((prr_product == PRR_PRODUCT_M3N) || (prr_product == PRR_PRODUCT_V3H)) { - p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[3][0]; + p_ddr_regdef_tbl = + (const uint32_t *)&DDR_REGDEF_TBL[3][0]; } else { FATAL_MSG("BL2: DDR:Unknown Product\n"); return 0xff; @@ -4269,7 +4311,8 @@ void pvtcode_update(void) } if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { - data_l = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000); + data_l = pvtp[ch] | (pvtn[ch] << 6) | + (tcal.tcomp_cal[ch] & 0xfffff000); reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), data_l | 0x00020000); @@ -4373,12 +4416,12 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) { tcal.init_cal[ch] = - (tcal. - init_cal[ch] & 0xfffff000) | (pvtn << 6) | - (pvtp); + (tcal.init_cal[ch] & 0xfffff000) | + (pvtn << 6) | + pvtp; } else { tcal.init_cal[ch] = - 0x00015000 | (pvtn << 6) | (pvtp); + 0x00015000 | (pvtn << 6) | pvtp; } } tcal.init_temp = 125; @@ -4386,7 +4429,7 @@ void ddr_padcal_tcompensate_getinit(uint32_t override) } #ifndef ddr_qos_init_setting -/* for QoS init */ +/* For QoS init */ uint8_t get_boardcnf_phyvalid(void) { return ddr_phyvalid; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index 52dbac32..f8caade2 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -544,7 +545,10 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { } } }, -/* boardcnf[7] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 1rank) */ +/* + * boardcnf[7] RENESAS SALVATOR-X board with + * H3 Ver.2.0 or later/SIP(8Gbit 1rank) + */ { 0x0f, 0x01, @@ -635,7 +639,10 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { } } }, -/* boardcnf[8] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 2rank) */ +/* + * boardcnf[8] RENESAS SALVATOR-X board with + * H3 Ver.2.0 or later/SIP(8Gbit 2rank) + */ { #if RCAR_DRAM_CHANNEL == 5 0x05, @@ -1766,13 +1773,16 @@ static uint32_t _board_judge(void) } else if (prr_product == PRR_PRODUCT_M3N) { /* RENESAS SALVATOR-X (M3-N/SIP) */ brd = 11; - } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_20)) { + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut <= PRR_PRODUCT_20)) { /* RENESAS SALVATOR-X (M3-W/SIP) */ brd = 0; - } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) { + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut < PRR_PRODUCT_30)) { /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */ brd = 19; - } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut >= PRR_PRODUCT_30)) { + } else if ((prr_product == PRR_PRODUCT_M3) && + (prr_cut >= PRR_PRODUCT_30)) { /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */ brd = 18; } -- cgit v1.2.3 From f3f5aba6e886b95923ac500e8e71c19551143d28 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Aug 2019 17:13:03 +0200 Subject: rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers Clean up the DDR B header files and remove checkpatch errors. Signed-off-by: Marek Vasut Change-Id: I9648ef5511df299688fd5284513812d32a1f8064 --- .../renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h | 26 +- .../staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h | 3 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h | 807 +++++++------- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h | 1003 +++++++++--------- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h | 861 +++++++-------- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h | 1099 ++++++++++---------- 6 files changed, 1903 insertions(+), 1896 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h index 0bc2bc16..8eb3859a 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h @@ -1,13 +1,14 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #define RCAR_DDR_VERSION "rev.0.36" -#define DRAM_CH_CNT (0x04) -#define SLICE_CNT (0x04) -#define CS_CNT (0x02) +#define DRAM_CH_CNT 0x04 +#define SLICE_CNT 0x04 +#define CS_CNT 0x02 /* order : CS0A, CS0B, CS1A, CS1B */ #define CSAB_CNT (CS_CNT * 2) @@ -16,15 +17,16 @@ #define CHAB_CNT (DRAM_CH_CNT * 2) /* pll setting */ -#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) /((b) * (diva))) +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) #define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) /* for ddr deisity setting */ -#define DBMEMCONF_REG(d3, row, bank, col, dw) \ +#define DBMEMCONF_REG(d3, row, bank, col, dw) \ ((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw)) -#define DBMEMCONF_REGD(density) \ -(DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29-3-10-2), 3, 10, 2)) +#define DBMEMCONF_REGD(density) \ + (DBMEMCONF_REG((density) % 2, ((density) + 1) / \ + 2 + (29 - 3 - 10 - 2), 3, 10, 2)) #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) @@ -44,10 +46,10 @@ #define CPG_CPGWPR (CPG_BASE + 0x0900U) #define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) -#define CPG_FRQCRB_KICK_BIT (1U<<31) -#define CPG_PLLECR_PLL3E_BIT (1U<<3) -#define CPG_PLLECR_PLL3ST_BIT (1U<<11) -#define CPG_ZB3CKCR_ZB3ST_BIT (1U<<11) +#define CPG_FRQCRB_KICK_BIT BIT(31) +#define CPG_PLLECR_PLL3E_BIT BIT(3) +#define CPG_PLLECR_PLL3ST_BIT BIT(11) +#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11) #define RST_BASE (0xE6160000U) #define RST_MODEMR (RST_BASE + 0x0060U) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h index 7f27b398..adf8dab1 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h index 6fa9ab99..69db2a73 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,418 +24,418 @@ #define DDR_PI_REGSET_NUM_H3 181 static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = { -/*0400*/ 0x000004f0, -/*0401*/ 0x00000000, -/*0402*/ 0x00000000, -/*0403*/ 0x00000100, -/*0404*/ 0x01003c0c, -/*0405*/ 0x02003c0c, -/*0406*/ 0x00010300, -/*0407*/ 0x04000100, -/*0408*/ 0x00000300, -/*0409*/ 0x000700c0, -/*040a*/ 0x00b00201, -/*040b*/ 0x00000020, -/*040c*/ 0x00000000, -/*040d*/ 0x00000000, -/*040e*/ 0x00000000, -/*040f*/ 0x00000000, -/*0410*/ 0x00000000, -/*0411*/ 0x00000000, -/*0412*/ 0x00000000, -/*0413*/ 0x09000000, -/*0414*/ 0x04080000, -/*0415*/ 0x04080400, -/*0416*/ 0x00000000, -/*0417*/ 0x32103210, -/*0418*/ 0x00800708, -/*0419*/ 0x000f000c, -/*041a*/ 0x00000100, -/*041b*/ 0x55aa55aa, -/*041c*/ 0x33cc33cc, -/*041d*/ 0x0ff00ff0, -/*041e*/ 0x0f0ff0f0, -/*041f*/ 0x00008e38, -/*0420*/ 0x76543210, -/*0421*/ 0x00000001, -/*0422*/ 0x00000000, -/*0423*/ 0x00000000, -/*0424*/ 0x00000000, -/*0425*/ 0x00000000, -/*0426*/ 0x00000000, -/*0427*/ 0x00000000, -/*0428*/ 0x00000000, -/*0429*/ 0x00000000, -/*042a*/ 0x00000000, -/*042b*/ 0x00000000, -/*042c*/ 0x00000000, -/*042d*/ 0x00000000, -/*042e*/ 0x00000000, -/*042f*/ 0x00000000, -/*0430*/ 0x00000000, -/*0431*/ 0x00000000, -/*0432*/ 0x00000000, -/*0433*/ 0x00200000, -/*0434*/ 0x08200820, -/*0435*/ 0x08200820, -/*0436*/ 0x08200820, -/*0437*/ 0x08200820, -/*0438*/ 0x08200820, -/*0439*/ 0x00000820, -/*043a*/ 0x03000300, -/*043b*/ 0x03000300, -/*043c*/ 0x03000300, -/*043d*/ 0x03000300, -/*043e*/ 0x00000300, -/*043f*/ 0x00000000, -/*0440*/ 0x00000000, -/*0441*/ 0x00000000, -/*0442*/ 0x00000000, -/*0443*/ 0x00a000a0, -/*0444*/ 0x00a000a0, -/*0445*/ 0x00a000a0, -/*0446*/ 0x00a000a0, -/*0447*/ 0x00a000a0, -/*0448*/ 0x00a000a0, -/*0449*/ 0x00a000a0, -/*044a*/ 0x00a000a0, -/*044b*/ 0x00a000a0, -/*044c*/ 0x01040109, -/*044d*/ 0x00000200, -/*044e*/ 0x01000000, -/*044f*/ 0x00000200, -/*0450*/ 0x4041a141, -/*0451*/ 0xc00141a0, -/*0452*/ 0x0e0100c0, -/*0453*/ 0x0010000c, -/*0454*/ 0x0c064208, -/*0455*/ 0x000f0c18, -/*0456*/ 0x00e00140, -/*0457*/ 0x00000c20 + /*0400*/ 0x000004f0, + /*0401*/ 0x00000000, + /*0402*/ 0x00000000, + /*0403*/ 0x00000100, + /*0404*/ 0x01003c0c, + /*0405*/ 0x02003c0c, + /*0406*/ 0x00010300, + /*0407*/ 0x04000100, + /*0408*/ 0x00000300, + /*0409*/ 0x000700c0, + /*040a*/ 0x00b00201, + /*040b*/ 0x00000020, + /*040c*/ 0x00000000, + /*040d*/ 0x00000000, + /*040e*/ 0x00000000, + /*040f*/ 0x00000000, + /*0410*/ 0x00000000, + /*0411*/ 0x00000000, + /*0412*/ 0x00000000, + /*0413*/ 0x09000000, + /*0414*/ 0x04080000, + /*0415*/ 0x04080400, + /*0416*/ 0x00000000, + /*0417*/ 0x32103210, + /*0418*/ 0x00800708, + /*0419*/ 0x000f000c, + /*041a*/ 0x00000100, + /*041b*/ 0x55aa55aa, + /*041c*/ 0x33cc33cc, + /*041d*/ 0x0ff00ff0, + /*041e*/ 0x0f0ff0f0, + /*041f*/ 0x00008e38, + /*0420*/ 0x76543210, + /*0421*/ 0x00000001, + /*0422*/ 0x00000000, + /*0423*/ 0x00000000, + /*0424*/ 0x00000000, + /*0425*/ 0x00000000, + /*0426*/ 0x00000000, + /*0427*/ 0x00000000, + /*0428*/ 0x00000000, + /*0429*/ 0x00000000, + /*042a*/ 0x00000000, + /*042b*/ 0x00000000, + /*042c*/ 0x00000000, + /*042d*/ 0x00000000, + /*042e*/ 0x00000000, + /*042f*/ 0x00000000, + /*0430*/ 0x00000000, + /*0431*/ 0x00000000, + /*0432*/ 0x00000000, + /*0433*/ 0x00200000, + /*0434*/ 0x08200820, + /*0435*/ 0x08200820, + /*0436*/ 0x08200820, + /*0437*/ 0x08200820, + /*0438*/ 0x08200820, + /*0439*/ 0x00000820, + /*043a*/ 0x03000300, + /*043b*/ 0x03000300, + /*043c*/ 0x03000300, + /*043d*/ 0x03000300, + /*043e*/ 0x00000300, + /*043f*/ 0x00000000, + /*0440*/ 0x00000000, + /*0441*/ 0x00000000, + /*0442*/ 0x00000000, + /*0443*/ 0x00a000a0, + /*0444*/ 0x00a000a0, + /*0445*/ 0x00a000a0, + /*0446*/ 0x00a000a0, + /*0447*/ 0x00a000a0, + /*0448*/ 0x00a000a0, + /*0449*/ 0x00a000a0, + /*044a*/ 0x00a000a0, + /*044b*/ 0x00a000a0, + /*044c*/ 0x01040109, + /*044d*/ 0x00000200, + /*044e*/ 0x01000000, + /*044f*/ 0x00000200, + /*0450*/ 0x4041a141, + /*0451*/ 0xc00141a0, + /*0452*/ 0x0e0100c0, + /*0453*/ 0x0010000c, + /*0454*/ 0x0c064208, + /*0455*/ 0x000f0c18, + /*0456*/ 0x00e00140, + /*0457*/ 0x00000c20 }; static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = { -/*0600*/ 0x00000000, -/*0601*/ 0x00000000, -/*0602*/ 0x00000000, -/*0603*/ 0x00000000, -/*0604*/ 0x00000000, -/*0605*/ 0x00000000, -/*0606*/ 0x00000002, -/*0607*/ 0x00000000, -/*0608*/ 0x00000000, -/*0609*/ 0x00000000, -/*060a*/ 0x00400320, -/*060b*/ 0x00000040, -/*060c*/ 0x00dcba98, -/*060d*/ 0x00000000, -/*060e*/ 0x00dcba98, -/*060f*/ 0x01000000, -/*0610*/ 0x00020003, -/*0611*/ 0x00000000, -/*0612*/ 0x00000000, -/*0613*/ 0x00000000, -/*0614*/ 0x00002a01, -/*0615*/ 0x00000015, -/*0616*/ 0x00000015, -/*0617*/ 0x0000002a, -/*0618*/ 0x00000033, -/*0619*/ 0x0000000c, -/*061a*/ 0x0000000c, -/*061b*/ 0x00000033, -/*061c*/ 0x00418820, -/*061d*/ 0x003f0000, -/*061e*/ 0x0000003f, -/*061f*/ 0x0002006e, -/*0620*/ 0x02000200, -/*0621*/ 0x02000200, -/*0622*/ 0x00000200, -/*0623*/ 0x42080010, -/*0624*/ 0x00000003 + /*0600*/ 0x00000000, + /*0601*/ 0x00000000, + /*0602*/ 0x00000000, + /*0603*/ 0x00000000, + /*0604*/ 0x00000000, + /*0605*/ 0x00000000, + /*0606*/ 0x00000002, + /*0607*/ 0x00000000, + /*0608*/ 0x00000000, + /*0609*/ 0x00000000, + /*060a*/ 0x00400320, + /*060b*/ 0x00000040, + /*060c*/ 0x00dcba98, + /*060d*/ 0x00000000, + /*060e*/ 0x00dcba98, + /*060f*/ 0x01000000, + /*0610*/ 0x00020003, + /*0611*/ 0x00000000, + /*0612*/ 0x00000000, + /*0613*/ 0x00000000, + /*0614*/ 0x00002a01, + /*0615*/ 0x00000015, + /*0616*/ 0x00000015, + /*0617*/ 0x0000002a, + /*0618*/ 0x00000033, + /*0619*/ 0x0000000c, + /*061a*/ 0x0000000c, + /*061b*/ 0x00000033, + /*061c*/ 0x00418820, + /*061d*/ 0x003f0000, + /*061e*/ 0x0000003f, + /*061f*/ 0x0002006e, + /*0620*/ 0x02000200, + /*0621*/ 0x02000200, + /*0622*/ 0x00000200, + /*0623*/ 0x42080010, + /*0624*/ 0x00000003 }; static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = { -/*0680*/ 0x04040404, -/*0681*/ 0x00000404, -/*0682*/ 0x00000000, -/*0683*/ 0x00000000, -/*0684*/ 0x00000000, -/*0685*/ 0x00000000, -/*0686*/ 0x00000002, -/*0687*/ 0x00000000, -/*0688*/ 0x00000000, -/*0689*/ 0x00000000, -/*068a*/ 0x00400320, -/*068b*/ 0x00000040, -/*068c*/ 0x00000000, -/*068d*/ 0x00000000, -/*068e*/ 0x00000000, -/*068f*/ 0x01000000, -/*0690*/ 0x00020003, -/*0691*/ 0x00000000, -/*0692*/ 0x00000000, -/*0693*/ 0x00000000, -/*0694*/ 0x00002a01, -/*0695*/ 0x00000015, -/*0696*/ 0x00000015, -/*0697*/ 0x0000002a, -/*0698*/ 0x00000033, -/*0699*/ 0x0000000c, -/*069a*/ 0x0000000c, -/*069b*/ 0x00000033, -/*069c*/ 0x00000000, -/*069d*/ 0x00000000, -/*069e*/ 0x00000000, -/*069f*/ 0x0002006e, -/*06a0*/ 0x02000200, -/*06a1*/ 0x02000200, -/*06a2*/ 0x00000200, -/*06a3*/ 0x42080010, -/*06a4*/ 0x00000003 + /*0680*/ 0x04040404, + /*0681*/ 0x00000404, + /*0682*/ 0x00000000, + /*0683*/ 0x00000000, + /*0684*/ 0x00000000, + /*0685*/ 0x00000000, + /*0686*/ 0x00000002, + /*0687*/ 0x00000000, + /*0688*/ 0x00000000, + /*0689*/ 0x00000000, + /*068a*/ 0x00400320, + /*068b*/ 0x00000040, + /*068c*/ 0x00000000, + /*068d*/ 0x00000000, + /*068e*/ 0x00000000, + /*068f*/ 0x01000000, + /*0690*/ 0x00020003, + /*0691*/ 0x00000000, + /*0692*/ 0x00000000, + /*0693*/ 0x00000000, + /*0694*/ 0x00002a01, + /*0695*/ 0x00000015, + /*0696*/ 0x00000015, + /*0697*/ 0x0000002a, + /*0698*/ 0x00000033, + /*0699*/ 0x0000000c, + /*069a*/ 0x0000000c, + /*069b*/ 0x00000033, + /*069c*/ 0x00000000, + /*069d*/ 0x00000000, + /*069e*/ 0x00000000, + /*069f*/ 0x0002006e, + /*06a0*/ 0x02000200, + /*06a1*/ 0x02000200, + /*06a2*/ 0x00000200, + /*06a3*/ 0x42080010, + /*06a4*/ 0x00000003 }; static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = { -/*0700*/ 0x00000001, -/*0701*/ 0x00000000, -/*0702*/ 0x00000005, -/*0703*/ 0x04000f00, -/*0704*/ 0x00020080, -/*0705*/ 0x00020055, -/*0706*/ 0x00000000, -/*0707*/ 0x00000000, -/*0708*/ 0x00000000, -/*0709*/ 0x00000050, -/*070a*/ 0x00000000, -/*070b*/ 0x01010100, -/*070c*/ 0x00000200, -/*070d*/ 0x00001102, -/*070e*/ 0x00000000, -/*070f*/ 0x000f1f00, -/*0710*/ 0x0f1f0f1f, -/*0711*/ 0x0f1f0f1f, -/*0712*/ 0x00020003, -/*0713*/ 0x02000200, -/*0714*/ 0x00000200, -/*0715*/ 0x00001102, -/*0716*/ 0x00000064, -/*0717*/ 0x00000000, -/*0718*/ 0x00000000, -/*0719*/ 0x00000502, -/*071a*/ 0x027f6e00, -/*071b*/ 0x007f007f, -/*071c*/ 0x00007f3c, -/*071d*/ 0x00047f6e, -/*071e*/ 0x0003154f, -/*071f*/ 0x0001154f, -/*0720*/ 0x0001154f, -/*0721*/ 0x0001154f, -/*0722*/ 0x0001154f, -/*0723*/ 0x00003fee, -/*0724*/ 0x0001154f, -/*0725*/ 0x00003fee, -/*0726*/ 0x0001154f, -/*0727*/ 0x00007f3c, -/*0728*/ 0x0001154f, -/*0729*/ 0x00000000, -/*072a*/ 0x00000000, -/*072b*/ 0x00000000, -/*072c*/ 0x65000000, -/*072d*/ 0x00000000, -/*072e*/ 0x00000000, -/*072f*/ 0x00000201, -/*0730*/ 0x00000000, -/*0731*/ 0x00000000, -/*0732*/ 0x00000000, -/*0733*/ 0x00000000, -/*0734*/ 0x00000000, -/*0735*/ 0x00000000, -/*0736*/ 0x00000000, -/*0737*/ 0x00000000, -/*0738*/ 0x00000000, -/*0739*/ 0x00000000, -/*073a*/ 0x00000000 + /*0700*/ 0x00000001, + /*0701*/ 0x00000000, + /*0702*/ 0x00000005, + /*0703*/ 0x04000f00, + /*0704*/ 0x00020080, + /*0705*/ 0x00020055, + /*0706*/ 0x00000000, + /*0707*/ 0x00000000, + /*0708*/ 0x00000000, + /*0709*/ 0x00000050, + /*070a*/ 0x00000000, + /*070b*/ 0x01010100, + /*070c*/ 0x00000200, + /*070d*/ 0x00001102, + /*070e*/ 0x00000000, + /*070f*/ 0x000f1f00, + /*0710*/ 0x0f1f0f1f, + /*0711*/ 0x0f1f0f1f, + /*0712*/ 0x00020003, + /*0713*/ 0x02000200, + /*0714*/ 0x00000200, + /*0715*/ 0x00001102, + /*0716*/ 0x00000064, + /*0717*/ 0x00000000, + /*0718*/ 0x00000000, + /*0719*/ 0x00000502, + /*071a*/ 0x027f6e00, + /*071b*/ 0x007f007f, + /*071c*/ 0x00007f3c, + /*071d*/ 0x00047f6e, + /*071e*/ 0x0003154f, + /*071f*/ 0x0001154f, + /*0720*/ 0x0001154f, + /*0721*/ 0x0001154f, + /*0722*/ 0x0001154f, + /*0723*/ 0x00003fee, + /*0724*/ 0x0001154f, + /*0725*/ 0x00003fee, + /*0726*/ 0x0001154f, + /*0727*/ 0x00007f3c, + /*0728*/ 0x0001154f, + /*0729*/ 0x00000000, + /*072a*/ 0x00000000, + /*072b*/ 0x00000000, + /*072c*/ 0x65000000, + /*072d*/ 0x00000000, + /*072e*/ 0x00000000, + /*072f*/ 0x00000201, + /*0730*/ 0x00000000, + /*0731*/ 0x00000000, + /*0732*/ 0x00000000, + /*0733*/ 0x00000000, + /*0734*/ 0x00000000, + /*0735*/ 0x00000000, + /*0736*/ 0x00000000, + /*0737*/ 0x00000000, + /*0738*/ 0x00000000, + /*0739*/ 0x00000000, + /*073a*/ 0x00000000 }; static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000100, -/*0202*/ 0x00000000, -/*0203*/ 0x0000ffff, -/*0204*/ 0x00000000, -/*0205*/ 0x0000ffff, -/*0206*/ 0x00000000, -/*0207*/ 0x304cffff, -/*0208*/ 0x00000200, -/*0209*/ 0x00000200, -/*020a*/ 0x00000200, -/*020b*/ 0x00000200, -/*020c*/ 0x0000304c, -/*020d*/ 0x00000200, -/*020e*/ 0x00000200, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x0000304c, -/*0212*/ 0x00000200, -/*0213*/ 0x00000200, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00010000, -/*0217*/ 0x00000003, -/*0218*/ 0x01000001, -/*0219*/ 0x00000000, -/*021a*/ 0x00000000, -/*021b*/ 0x00000000, -/*021c*/ 0x00000000, -/*021d*/ 0x00000000, -/*021e*/ 0x00000000, -/*021f*/ 0x00000000, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x0f000101, -/*022a*/ 0x08492d25, -/*022b*/ 0x500e0c04, -/*022c*/ 0x0002500e, -/*022d*/ 0x00460003, -/*022e*/ 0x182600cf, -/*022f*/ 0x182600cf, -/*0230*/ 0x00000005, -/*0231*/ 0x00000000, -/*0232*/ 0x00000000, -/*0233*/ 0x00000000, -/*0234*/ 0x00000000, -/*0235*/ 0x00000000, -/*0236*/ 0x00000000, -/*0237*/ 0x00000000, -/*0238*/ 0x01000000, -/*0239*/ 0x00040404, -/*023a*/ 0x01280a00, -/*023b*/ 0x00000000, -/*023c*/ 0x000f0000, -/*023d*/ 0x00001803, -/*023e*/ 0x00000000, -/*023f*/ 0x00000000, -/*0240*/ 0x00060002, -/*0241*/ 0x00010001, -/*0242*/ 0x01000101, -/*0243*/ 0x04020201, -/*0244*/ 0x00080804, -/*0245*/ 0x00000000, -/*0246*/ 0x08030000, -/*0247*/ 0x15150408, -/*0248*/ 0x00000000, -/*0249*/ 0x00000000, -/*024a*/ 0x00000000, -/*024b*/ 0x001e0f0f, -/*024c*/ 0x00000000, -/*024d*/ 0x01000300, -/*024e*/ 0x00000000, -/*024f*/ 0x00000000, -/*0250*/ 0x01000000, -/*0251*/ 0x00010101, -/*0252*/ 0x000e0e0e, -/*0253*/ 0x000c0c0c, -/*0254*/ 0x02060601, -/*0255*/ 0x00000000, -/*0256*/ 0x00000003, -/*0257*/ 0x00181703, -/*0258*/ 0x00280006, -/*0259*/ 0x00280016, -/*025a*/ 0x00000016, -/*025b*/ 0x00000000, -/*025c*/ 0x00000000, -/*025d*/ 0x00000000, -/*025e*/ 0x140a0000, -/*025f*/ 0x0005010a, -/*0260*/ 0x03018d03, -/*0261*/ 0x000a018d, -/*0262*/ 0x00060100, -/*0263*/ 0x01000006, -/*0264*/ 0x018e018e, -/*0265*/ 0x018e0100, -/*0266*/ 0x1111018e, -/*0267*/ 0x10010204, -/*0268*/ 0x09090650, -/*0269*/ 0x20110202, -/*026a*/ 0x00201000, -/*026b*/ 0x00201000, -/*026c*/ 0x04041000, -/*026d*/ 0x18020100, -/*026e*/ 0x00010118, -/*026f*/ 0x004b004a, -/*0270*/ 0x050f0000, -/*0271*/ 0x0c01021e, -/*0272*/ 0x34000000, -/*0273*/ 0x00000000, -/*0274*/ 0x00000000, -/*0275*/ 0x00000000, -/*0276*/ 0x312ed400, -/*0277*/ 0xd4111132, -/*0278*/ 0x1132312e, -/*0279*/ 0x312ed411, -/*027a*/ 0x00111132, -/*027b*/ 0x32312ed4, -/*027c*/ 0x2ed41111, -/*027d*/ 0x11113231, -/*027e*/ 0x32312ed4, -/*027f*/ 0xd4001111, -/*0280*/ 0x1132312e, -/*0281*/ 0x312ed411, -/*0282*/ 0xd4111132, -/*0283*/ 0x1132312e, -/*0284*/ 0x2ed40011, -/*0285*/ 0x11113231, -/*0286*/ 0x32312ed4, -/*0287*/ 0x2ed41111, -/*0288*/ 0x11113231, -/*0289*/ 0x00020000, -/*028a*/ 0x018d018d, -/*028b*/ 0x0c08018d, -/*028c*/ 0x1f121d22, -/*028d*/ 0x4301b344, -/*028e*/ 0x10172006, -/*028f*/ 0x121d220c, -/*0290*/ 0x01b3441f, -/*0291*/ 0x17200643, -/*0292*/ 0x1d220c10, -/*0293*/ 0x00001f12, -/*0294*/ 0x4301b344, -/*0295*/ 0x10172006, -/*0296*/ 0x00020002, -/*0297*/ 0x00020002, -/*0298*/ 0x00020002, -/*0299*/ 0x00020002, -/*029a*/ 0x00020002, -/*029b*/ 0x00000000, -/*029c*/ 0x00000000, -/*029d*/ 0x00000000, -/*029e*/ 0x00000000, -/*029f*/ 0x00000000, -/*02a0*/ 0x00000000, -/*02a1*/ 0x00000000, -/*02a2*/ 0x00000000, -/*02a3*/ 0x00000000, -/*02a4*/ 0x00000000, -/*02a5*/ 0x00000000, -/*02a6*/ 0x00000000, -/*02a7*/ 0x01000400, -/*02a8*/ 0x00304c00, -/*02a9*/ 0x0001e2f8, -/*02aa*/ 0x0000304c, -/*02ab*/ 0x0001e2f8, -/*02ac*/ 0x0000304c, -/*02ad*/ 0x0001e2f8, -/*02ae*/ 0x08000000, -/*02af*/ 0x00000100, -/*02b0*/ 0x00000000, -/*02b1*/ 0x00000000, -/*02b2*/ 0x00000000, -/*02b3*/ 0x00000000, -/*02b4*/ 0x00000002 + /*0200*/ 0x00000b00, + /*0201*/ 0x00000100, + /*0202*/ 0x00000000, + /*0203*/ 0x0000ffff, + /*0204*/ 0x00000000, + /*0205*/ 0x0000ffff, + /*0206*/ 0x00000000, + /*0207*/ 0x304cffff, + /*0208*/ 0x00000200, + /*0209*/ 0x00000200, + /*020a*/ 0x00000200, + /*020b*/ 0x00000200, + /*020c*/ 0x0000304c, + /*020d*/ 0x00000200, + /*020e*/ 0x00000200, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x0000304c, + /*0212*/ 0x00000200, + /*0213*/ 0x00000200, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00010000, + /*0217*/ 0x00000003, + /*0218*/ 0x01000001, + /*0219*/ 0x00000000, + /*021a*/ 0x00000000, + /*021b*/ 0x00000000, + /*021c*/ 0x00000000, + /*021d*/ 0x00000000, + /*021e*/ 0x00000000, + /*021f*/ 0x00000000, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x0f000101, + /*022a*/ 0x08492d25, + /*022b*/ 0x500e0c04, + /*022c*/ 0x0002500e, + /*022d*/ 0x00460003, + /*022e*/ 0x182600cf, + /*022f*/ 0x182600cf, + /*0230*/ 0x00000005, + /*0231*/ 0x00000000, + /*0232*/ 0x00000000, + /*0233*/ 0x00000000, + /*0234*/ 0x00000000, + /*0235*/ 0x00000000, + /*0236*/ 0x00000000, + /*0237*/ 0x00000000, + /*0238*/ 0x01000000, + /*0239*/ 0x00040404, + /*023a*/ 0x01280a00, + /*023b*/ 0x00000000, + /*023c*/ 0x000f0000, + /*023d*/ 0x00001803, + /*023e*/ 0x00000000, + /*023f*/ 0x00000000, + /*0240*/ 0x00060002, + /*0241*/ 0x00010001, + /*0242*/ 0x01000101, + /*0243*/ 0x04020201, + /*0244*/ 0x00080804, + /*0245*/ 0x00000000, + /*0246*/ 0x08030000, + /*0247*/ 0x15150408, + /*0248*/ 0x00000000, + /*0249*/ 0x00000000, + /*024a*/ 0x00000000, + /*024b*/ 0x001e0f0f, + /*024c*/ 0x00000000, + /*024d*/ 0x01000300, + /*024e*/ 0x00000000, + /*024f*/ 0x00000000, + /*0250*/ 0x01000000, + /*0251*/ 0x00010101, + /*0252*/ 0x000e0e0e, + /*0253*/ 0x000c0c0c, + /*0254*/ 0x02060601, + /*0255*/ 0x00000000, + /*0256*/ 0x00000003, + /*0257*/ 0x00181703, + /*0258*/ 0x00280006, + /*0259*/ 0x00280016, + /*025a*/ 0x00000016, + /*025b*/ 0x00000000, + /*025c*/ 0x00000000, + /*025d*/ 0x00000000, + /*025e*/ 0x140a0000, + /*025f*/ 0x0005010a, + /*0260*/ 0x03018d03, + /*0261*/ 0x000a018d, + /*0262*/ 0x00060100, + /*0263*/ 0x01000006, + /*0264*/ 0x018e018e, + /*0265*/ 0x018e0100, + /*0266*/ 0x1111018e, + /*0267*/ 0x10010204, + /*0268*/ 0x09090650, + /*0269*/ 0x20110202, + /*026a*/ 0x00201000, + /*026b*/ 0x00201000, + /*026c*/ 0x04041000, + /*026d*/ 0x18020100, + /*026e*/ 0x00010118, + /*026f*/ 0x004b004a, + /*0270*/ 0x050f0000, + /*0271*/ 0x0c01021e, + /*0272*/ 0x34000000, + /*0273*/ 0x00000000, + /*0274*/ 0x00000000, + /*0275*/ 0x00000000, + /*0276*/ 0x312ed400, + /*0277*/ 0xd4111132, + /*0278*/ 0x1132312e, + /*0279*/ 0x312ed411, + /*027a*/ 0x00111132, + /*027b*/ 0x32312ed4, + /*027c*/ 0x2ed41111, + /*027d*/ 0x11113231, + /*027e*/ 0x32312ed4, + /*027f*/ 0xd4001111, + /*0280*/ 0x1132312e, + /*0281*/ 0x312ed411, + /*0282*/ 0xd4111132, + /*0283*/ 0x1132312e, + /*0284*/ 0x2ed40011, + /*0285*/ 0x11113231, + /*0286*/ 0x32312ed4, + /*0287*/ 0x2ed41111, + /*0288*/ 0x11113231, + /*0289*/ 0x00020000, + /*028a*/ 0x018d018d, + /*028b*/ 0x0c08018d, + /*028c*/ 0x1f121d22, + /*028d*/ 0x4301b344, + /*028e*/ 0x10172006, + /*028f*/ 0x121d220c, + /*0290*/ 0x01b3441f, + /*0291*/ 0x17200643, + /*0292*/ 0x1d220c10, + /*0293*/ 0x00001f12, + /*0294*/ 0x4301b344, + /*0295*/ 0x10172006, + /*0296*/ 0x00020002, + /*0297*/ 0x00020002, + /*0298*/ 0x00020002, + /*0299*/ 0x00020002, + /*029a*/ 0x00020002, + /*029b*/ 0x00000000, + /*029c*/ 0x00000000, + /*029d*/ 0x00000000, + /*029e*/ 0x00000000, + /*029f*/ 0x00000000, + /*02a0*/ 0x00000000, + /*02a1*/ 0x00000000, + /*02a2*/ 0x00000000, + /*02a3*/ 0x00000000, + /*02a4*/ 0x00000000, + /*02a5*/ 0x00000000, + /*02a6*/ 0x00000000, + /*02a7*/ 0x01000400, + /*02a8*/ 0x00304c00, + /*02a9*/ 0x0001e2f8, + /*02aa*/ 0x0000304c, + /*02ab*/ 0x0001e2f8, + /*02ac*/ 0x0000304c, + /*02ad*/ 0x0001e2f8, + /*02ae*/ 0x08000000, + /*02af*/ 0x00000100, + /*02b0*/ 0x00000000, + /*02b1*/ 0x00000000, + /*02b2*/ 0x00000000, + /*02b3*/ 0x00000000, + /*02b4*/ 0x00000002 }; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h index 6e4c30eb..b94f308f 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,516 +23,516 @@ #define DDR_PHY_ADR_G_REGSET_NUM_H3VER2 79 #define DDR_PI_REGSET_NUM_H3VER2 245 -static const uint32_t - DDR_PHY_SLICE_REGSET_H3VER2[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = { -/*0400*/ 0x76543210, -/*0401*/ 0x0004f008, -/*0402*/ 0x00020133, -/*0403*/ 0x00000000, -/*0404*/ 0x00000000, -/*0405*/ 0x00010000, -/*0406*/ 0x016e6e0e, -/*0407*/ 0x026e6e0e, -/*0408*/ 0x00010300, -/*0409*/ 0x04000100, -/*040a*/ 0x01000000, -/*040b*/ 0x00000000, -/*040c*/ 0x00000000, -/*040d*/ 0x00000100, -/*040e*/ 0x001700c0, -/*040f*/ 0x020100b0, -/*0410*/ 0x00030020, -/*0411*/ 0x00000000, -/*0412*/ 0x00000000, -/*0413*/ 0x00000000, -/*0414*/ 0x00000000, -/*0415*/ 0x00000000, -/*0416*/ 0x00000000, -/*0417*/ 0x00000000, -/*0418*/ 0x09000000, -/*0419*/ 0x04080000, -/*041a*/ 0x04080400, -/*041b*/ 0x08000000, -/*041c*/ 0x0c008007, -/*041d*/ 0x00000f00, -/*041e*/ 0x00000100, -/*041f*/ 0x55aa55aa, -/*0420*/ 0x33cc33cc, -/*0421*/ 0x0ff00ff0, -/*0422*/ 0x0f0ff0f0, -/*0423*/ 0x00018e38, -/*0424*/ 0x00000000, -/*0425*/ 0x00000000, -/*0426*/ 0x00000000, -/*0427*/ 0x00000000, -/*0428*/ 0x00000000, -/*0429*/ 0x00000000, -/*042a*/ 0x00000000, -/*042b*/ 0x00000000, -/*042c*/ 0x00000000, -/*042d*/ 0x00000000, -/*042e*/ 0x00000000, -/*042f*/ 0x00000000, -/*0430*/ 0x00000000, -/*0431*/ 0x00000000, -/*0432*/ 0x00000000, -/*0433*/ 0x00000000, -/*0434*/ 0x00000000, -/*0435*/ 0x00000000, -/*0436*/ 0x00000000, -/*0437*/ 0x00000000, -/*0438*/ 0x00000104, -/*0439*/ 0x00082020, -/*043a*/ 0x08200820, -/*043b*/ 0x08200820, -/*043c*/ 0x08200820, -/*043d*/ 0x08200820, -/*043e*/ 0x08200820, -/*043f*/ 0x00000000, -/*0440*/ 0x00000000, -/*0441*/ 0x03000300, -/*0442*/ 0x03000300, -/*0443*/ 0x03000300, -/*0444*/ 0x03000300, -/*0445*/ 0x00000300, -/*0446*/ 0x00000000, -/*0447*/ 0x00000000, -/*0448*/ 0x00000000, -/*0449*/ 0x00000000, -/*044a*/ 0x00000000, -/*044b*/ 0x00a000a0, -/*044c*/ 0x00a000a0, -/*044d*/ 0x00a000a0, -/*044e*/ 0x00a000a0, -/*044f*/ 0x00a000a0, -/*0450*/ 0x00a000a0, -/*0451*/ 0x00a000a0, -/*0452*/ 0x00a000a0, -/*0453*/ 0x00a000a0, -/*0454*/ 0x01040109, -/*0455*/ 0x00000200, -/*0456*/ 0x01000000, -/*0457*/ 0x00000200, -/*0458*/ 0x00000004, -/*0459*/ 0x4041a141, -/*045a*/ 0xc00141a0, -/*045b*/ 0x0e0000c0, -/*045c*/ 0x0010000c, -/*045d*/ 0x063e4208, -/*045e*/ 0x0f0c180c, -/*045f*/ 0x00e00140, -/*0460*/ 0x00000c20 +static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2 + [DDR_PHY_SLICE_REGSET_NUM_H3VER2] = { + /*0400*/ 0x76543210, + /*0401*/ 0x0004f008, + /*0402*/ 0x00020133, + /*0403*/ 0x00000000, + /*0404*/ 0x00000000, + /*0405*/ 0x00010000, + /*0406*/ 0x016e6e0e, + /*0407*/ 0x026e6e0e, + /*0408*/ 0x00010300, + /*0409*/ 0x04000100, + /*040a*/ 0x01000000, + /*040b*/ 0x00000000, + /*040c*/ 0x00000000, + /*040d*/ 0x00000100, + /*040e*/ 0x001700c0, + /*040f*/ 0x020100b0, + /*0410*/ 0x00030020, + /*0411*/ 0x00000000, + /*0412*/ 0x00000000, + /*0413*/ 0x00000000, + /*0414*/ 0x00000000, + /*0415*/ 0x00000000, + /*0416*/ 0x00000000, + /*0417*/ 0x00000000, + /*0418*/ 0x09000000, + /*0419*/ 0x04080000, + /*041a*/ 0x04080400, + /*041b*/ 0x08000000, + /*041c*/ 0x0c008007, + /*041d*/ 0x00000f00, + /*041e*/ 0x00000100, + /*041f*/ 0x55aa55aa, + /*0420*/ 0x33cc33cc, + /*0421*/ 0x0ff00ff0, + /*0422*/ 0x0f0ff0f0, + /*0423*/ 0x00018e38, + /*0424*/ 0x00000000, + /*0425*/ 0x00000000, + /*0426*/ 0x00000000, + /*0427*/ 0x00000000, + /*0428*/ 0x00000000, + /*0429*/ 0x00000000, + /*042a*/ 0x00000000, + /*042b*/ 0x00000000, + /*042c*/ 0x00000000, + /*042d*/ 0x00000000, + /*042e*/ 0x00000000, + /*042f*/ 0x00000000, + /*0430*/ 0x00000000, + /*0431*/ 0x00000000, + /*0432*/ 0x00000000, + /*0433*/ 0x00000000, + /*0434*/ 0x00000000, + /*0435*/ 0x00000000, + /*0436*/ 0x00000000, + /*0437*/ 0x00000000, + /*0438*/ 0x00000104, + /*0439*/ 0x00082020, + /*043a*/ 0x08200820, + /*043b*/ 0x08200820, + /*043c*/ 0x08200820, + /*043d*/ 0x08200820, + /*043e*/ 0x08200820, + /*043f*/ 0x00000000, + /*0440*/ 0x00000000, + /*0441*/ 0x03000300, + /*0442*/ 0x03000300, + /*0443*/ 0x03000300, + /*0444*/ 0x03000300, + /*0445*/ 0x00000300, + /*0446*/ 0x00000000, + /*0447*/ 0x00000000, + /*0448*/ 0x00000000, + /*0449*/ 0x00000000, + /*044a*/ 0x00000000, + /*044b*/ 0x00a000a0, + /*044c*/ 0x00a000a0, + /*044d*/ 0x00a000a0, + /*044e*/ 0x00a000a0, + /*044f*/ 0x00a000a0, + /*0450*/ 0x00a000a0, + /*0451*/ 0x00a000a0, + /*0452*/ 0x00a000a0, + /*0453*/ 0x00a000a0, + /*0454*/ 0x01040109, + /*0455*/ 0x00000200, + /*0456*/ 0x01000000, + /*0457*/ 0x00000200, + /*0458*/ 0x00000004, + /*0459*/ 0x4041a141, + /*045a*/ 0xc00141a0, + /*045b*/ 0x0e0000c0, + /*045c*/ 0x0010000c, + /*045d*/ 0x063e4208, + /*045e*/ 0x0f0c180c, + /*045f*/ 0x00e00140, + /*0460*/ 0x00000c20 }; static const uint32_t - DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = { -/*0600*/ 0x00000000, -/*0601*/ 0x00000000, -/*0602*/ 0x00000000, -/*0603*/ 0x00000000, -/*0604*/ 0x00000000, -/*0605*/ 0x00000000, -/*0606*/ 0x00000000, -/*0607*/ 0x00010000, -/*0608*/ 0x00000200, -/*0609*/ 0x00000000, -/*060a*/ 0x00000000, -/*060b*/ 0x00000000, -/*060c*/ 0x00400320, -/*060d*/ 0x00000040, -/*060e*/ 0x00dcba98, -/*060f*/ 0x03000000, -/*0610*/ 0x00000200, -/*0611*/ 0x00000000, -/*0612*/ 0x00000000, -/*0613*/ 0x00000000, -/*0614*/ 0x0000002a, -/*0615*/ 0x00000015, -/*0616*/ 0x00000015, -/*0617*/ 0x0000002a, -/*0618*/ 0x00000033, -/*0619*/ 0x0000000c, -/*061a*/ 0x0000000c, -/*061b*/ 0x00000033, -/*061c*/ 0x00418820, -/*061d*/ 0x003f0000, -/*061e*/ 0x0000003f, -/*061f*/ 0x0002c06e, -/*0620*/ 0x02c002c0, -/*0621*/ 0x02c002c0, -/*0622*/ 0x000002c0, -/*0623*/ 0x42080010, -/*0624*/ 0x0000033e + DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = { + /*0600*/ 0x00000000, + /*0601*/ 0x00000000, + /*0602*/ 0x00000000, + /*0603*/ 0x00000000, + /*0604*/ 0x00000000, + /*0605*/ 0x00000000, + /*0606*/ 0x00000000, + /*0607*/ 0x00010000, + /*0608*/ 0x00000200, + /*0609*/ 0x00000000, + /*060a*/ 0x00000000, + /*060b*/ 0x00000000, + /*060c*/ 0x00400320, + /*060d*/ 0x00000040, + /*060e*/ 0x00dcba98, + /*060f*/ 0x03000000, + /*0610*/ 0x00000200, + /*0611*/ 0x00000000, + /*0612*/ 0x00000000, + /*0613*/ 0x00000000, + /*0614*/ 0x0000002a, + /*0615*/ 0x00000015, + /*0616*/ 0x00000015, + /*0617*/ 0x0000002a, + /*0618*/ 0x00000033, + /*0619*/ 0x0000000c, + /*061a*/ 0x0000000c, + /*061b*/ 0x00000033, + /*061c*/ 0x00418820, + /*061d*/ 0x003f0000, + /*061e*/ 0x0000003f, + /*061f*/ 0x0002c06e, + /*0620*/ 0x02c002c0, + /*0621*/ 0x02c002c0, + /*0622*/ 0x000002c0, + /*0623*/ 0x42080010, + /*0624*/ 0x0000033e }; static const uint32_t - DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = { -/*0640*/ 0x00000000, -/*0641*/ 0x00000000, -/*0642*/ 0x00000000, -/*0643*/ 0x00000000, -/*0644*/ 0x00000000, -/*0645*/ 0x00000000, -/*0646*/ 0x00000000, -/*0647*/ 0x00000000, -/*0648*/ 0x00000000, -/*0649*/ 0x00000000, -/*064a*/ 0x00000000, -/*064b*/ 0x00000000, -/*064c*/ 0x00000000, -/*064d*/ 0x00000000, -/*064e*/ 0x00000000, -/*064f*/ 0x00000000, -/*0650*/ 0x00000000, -/*0651*/ 0x00000000, -/*0652*/ 0x00000000, -/*0653*/ 0x00000000, -/*0654*/ 0x00000000, -/*0655*/ 0x00000000, -/*0656*/ 0x00000000, -/*0657*/ 0x00000000, -/*0658*/ 0x00000000, -/*0659*/ 0x00000000, -/*065a*/ 0x00000000, -/*065b*/ 0x00000000, -/*065c*/ 0x00000000, -/*065d*/ 0x00000000, -/*065e*/ 0x00000000, -/*065f*/ 0x00000000, -/*0660*/ 0x00000000, -/*0661*/ 0x00000000, -/*0662*/ 0x00000000, -/*0663*/ 0x00000000, -/*0664*/ 0x00000000 + DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = { + /*0640*/ 0x00000000, + /*0641*/ 0x00000000, + /*0642*/ 0x00000000, + /*0643*/ 0x00000000, + /*0644*/ 0x00000000, + /*0645*/ 0x00000000, + /*0646*/ 0x00000000, + /*0647*/ 0x00000000, + /*0648*/ 0x00000000, + /*0649*/ 0x00000000, + /*064a*/ 0x00000000, + /*064b*/ 0x00000000, + /*064c*/ 0x00000000, + /*064d*/ 0x00000000, + /*064e*/ 0x00000000, + /*064f*/ 0x00000000, + /*0650*/ 0x00000000, + /*0651*/ 0x00000000, + /*0652*/ 0x00000000, + /*0653*/ 0x00000000, + /*0654*/ 0x00000000, + /*0655*/ 0x00000000, + /*0656*/ 0x00000000, + /*0657*/ 0x00000000, + /*0658*/ 0x00000000, + /*0659*/ 0x00000000, + /*065a*/ 0x00000000, + /*065b*/ 0x00000000, + /*065c*/ 0x00000000, + /*065d*/ 0x00000000, + /*065e*/ 0x00000000, + /*065f*/ 0x00000000, + /*0660*/ 0x00000000, + /*0661*/ 0x00000000, + /*0662*/ 0x00000000, + /*0663*/ 0x00000000, + /*0664*/ 0x00000000 }; static const uint32_t - DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = { -/*0680*/ 0x00000000, -/*0681*/ 0x00000100, -/*0682*/ 0x00000000, -/*0683*/ 0x00050000, -/*0684*/ 0x0f000000, -/*0685*/ 0x00800400, -/*0686*/ 0x00020032, -/*0687*/ 0x00020055, -/*0688*/ 0x00000000, -/*0689*/ 0x00000000, -/*068a*/ 0x00000000, -/*068b*/ 0x00000050, -/*068c*/ 0x00000000, -/*068d*/ 0x01010100, -/*068e*/ 0x01000200, -/*068f*/ 0x00000000, -/*0690*/ 0x00010100, -/*0691*/ 0x00000000, -/*0692*/ 0x00000000, -/*0693*/ 0x00000000, -/*0694*/ 0x00000000, -/*0695*/ 0x00005064, -/*0696*/ 0x01421142, -/*0697*/ 0x00000142, -/*0698*/ 0x00000000, -/*0699*/ 0x000f1100, -/*069a*/ 0x0f110f11, -/*069b*/ 0x09000f11, -/*069c*/ 0x00000003, -/*069d*/ 0x0002c000, -/*069e*/ 0x02c002c0, -/*069f*/ 0x000002c0, -/*06a0*/ 0x03421342, -/*06a1*/ 0x00000342, -/*06a2*/ 0x00000000, -/*06a3*/ 0x00000000, -/*06a4*/ 0x05020000, -/*06a5*/ 0x14000000, -/*06a6*/ 0x027f6e00, -/*06a7*/ 0x047f027f, -/*06a8*/ 0x00027f6e, -/*06a9*/ 0x00047f6e, -/*06aa*/ 0x0003554f, -/*06ab*/ 0x0001554f, -/*06ac*/ 0x0001554f, -/*06ad*/ 0x0001554f, -/*06ae*/ 0x0001554f, -/*06af*/ 0x00003fee, -/*06b0*/ 0x0001554f, -/*06b1*/ 0x00003fee, -/*06b2*/ 0x0001554f, -/*06b3*/ 0x00027f6e, -/*06b4*/ 0x0001554f, -/*06b5*/ 0x00004011, -/*06b6*/ 0x00004410, -/*06b7*/ 0x00000000, -/*06b8*/ 0x00000000, -/*06b9*/ 0x00000000, -/*06ba*/ 0x00000065, -/*06bb*/ 0x00000000, -/*06bc*/ 0x00020201, -/*06bd*/ 0x00000000, -/*06be*/ 0x03000000, -/*06bf*/ 0x00000008, -/*06c0*/ 0x00000000, -/*06c1*/ 0x00000000, -/*06c2*/ 0x00000000, -/*06c3*/ 0x00000000, -/*06c4*/ 0x00000001, -/*06c5*/ 0x00000000, -/*06c6*/ 0x00000000, -/*06c7*/ 0x00000000, -/*06c8*/ 0x000000e4, -/*06c9*/ 0x00010198, -/*06ca*/ 0x00000000, -/*06cb*/ 0x00000000, -/*06cc*/ 0x07010000, -/*06cd*/ 0x00000104, -/*06ce*/ 0x00000000 + DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = { + /*0680*/ 0x00000000, + /*0681*/ 0x00000100, + /*0682*/ 0x00000000, + /*0683*/ 0x00050000, + /*0684*/ 0x0f000000, + /*0685*/ 0x00800400, + /*0686*/ 0x00020032, + /*0687*/ 0x00020055, + /*0688*/ 0x00000000, + /*0689*/ 0x00000000, + /*068a*/ 0x00000000, + /*068b*/ 0x00000050, + /*068c*/ 0x00000000, + /*068d*/ 0x01010100, + /*068e*/ 0x01000200, + /*068f*/ 0x00000000, + /*0690*/ 0x00010100, + /*0691*/ 0x00000000, + /*0692*/ 0x00000000, + /*0693*/ 0x00000000, + /*0694*/ 0x00000000, + /*0695*/ 0x00005064, + /*0696*/ 0x01421142, + /*0697*/ 0x00000142, + /*0698*/ 0x00000000, + /*0699*/ 0x000f1100, + /*069a*/ 0x0f110f11, + /*069b*/ 0x09000f11, + /*069c*/ 0x00000003, + /*069d*/ 0x0002c000, + /*069e*/ 0x02c002c0, + /*069f*/ 0x000002c0, + /*06a0*/ 0x03421342, + /*06a1*/ 0x00000342, + /*06a2*/ 0x00000000, + /*06a3*/ 0x00000000, + /*06a4*/ 0x05020000, + /*06a5*/ 0x14000000, + /*06a6*/ 0x027f6e00, + /*06a7*/ 0x047f027f, + /*06a8*/ 0x00027f6e, + /*06a9*/ 0x00047f6e, + /*06aa*/ 0x0003554f, + /*06ab*/ 0x0001554f, + /*06ac*/ 0x0001554f, + /*06ad*/ 0x0001554f, + /*06ae*/ 0x0001554f, + /*06af*/ 0x00003fee, + /*06b0*/ 0x0001554f, + /*06b1*/ 0x00003fee, + /*06b2*/ 0x0001554f, + /*06b3*/ 0x00027f6e, + /*06b4*/ 0x0001554f, + /*06b5*/ 0x00004011, + /*06b6*/ 0x00004410, + /*06b7*/ 0x00000000, + /*06b8*/ 0x00000000, + /*06b9*/ 0x00000000, + /*06ba*/ 0x00000065, + /*06bb*/ 0x00000000, + /*06bc*/ 0x00020201, + /*06bd*/ 0x00000000, + /*06be*/ 0x03000000, + /*06bf*/ 0x00000008, + /*06c0*/ 0x00000000, + /*06c1*/ 0x00000000, + /*06c2*/ 0x00000000, + /*06c3*/ 0x00000000, + /*06c4*/ 0x00000001, + /*06c5*/ 0x00000000, + /*06c6*/ 0x00000000, + /*06c7*/ 0x00000000, + /*06c8*/ 0x000000e4, + /*06c9*/ 0x00010198, + /*06ca*/ 0x00000000, + /*06cb*/ 0x00000000, + /*06cc*/ 0x07010000, + /*06cd*/ 0x00000104, + /*06ce*/ 0x00000000 }; static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000100, -/*0202*/ 0x00640000, -/*0203*/ 0x00000000, -/*0204*/ 0x0000ffff, -/*0205*/ 0x00000000, -/*0206*/ 0x0000ffff, -/*0207*/ 0x00000000, -/*0208*/ 0x0000ffff, -/*0209*/ 0x0000304c, -/*020a*/ 0x00000200, -/*020b*/ 0x00000200, -/*020c*/ 0x00000200, -/*020d*/ 0x00000200, -/*020e*/ 0x0000304c, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x00000200, -/*0212*/ 0x00000200, -/*0213*/ 0x0000304c, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00000200, -/*0217*/ 0x00000200, -/*0218*/ 0x00010000, -/*0219*/ 0x00000003, -/*021a*/ 0x01000001, -/*021b*/ 0x00000000, -/*021c*/ 0x00000000, -/*021d*/ 0x00000000, -/*021e*/ 0x00000000, -/*021f*/ 0x00000000, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x00000000, -/*022a*/ 0x00000000, -/*022b*/ 0x0f000101, -/*022c*/ 0x08492d25, -/*022d*/ 0x500e0c04, -/*022e*/ 0x0002500e, -/*022f*/ 0x00000301, -/*0230*/ 0x00000046, -/*0231*/ 0x000000cf, -/*0232*/ 0x00001826, -/*0233*/ 0x000000cf, -/*0234*/ 0x00001826, -/*0235*/ 0x00000005, -/*0236*/ 0x00000000, -/*0237*/ 0x00000000, -/*0238*/ 0x00000000, -/*0239*/ 0x00000000, -/*023a*/ 0x00000000, -/*023b*/ 0x00000000, -/*023c*/ 0x00000000, -/*023d*/ 0x00000000, -/*023e*/ 0x04010000, -/*023f*/ 0x00000404, -/*0240*/ 0x0101280a, -/*0241*/ 0x00000000, -/*0242*/ 0x00000000, -/*0243*/ 0x0003000f, -/*0244*/ 0x00000018, -/*0245*/ 0x00000000, -/*0246*/ 0x00000000, -/*0247*/ 0x00060002, -/*0248*/ 0x00010001, -/*0249*/ 0x01000101, -/*024a*/ 0x04020201, -/*024b*/ 0x00080804, -/*024c*/ 0x00000000, -/*024d*/ 0x08030000, -/*024e*/ 0x15150408, -/*024f*/ 0x00000000, -/*0250*/ 0x00000000, -/*0251*/ 0x00000000, -/*0252*/ 0x0f0f0000, -/*0253*/ 0x0000001e, -/*0254*/ 0x00000000, -/*0255*/ 0x01000300, -/*0256*/ 0x00000100, -/*0257*/ 0x00000000, -/*0258*/ 0x00000000, -/*0259*/ 0x01000000, -/*025a*/ 0x00000101, -/*025b*/ 0x55555a5a, -/*025c*/ 0x55555a5a, -/*025d*/ 0x55555a5a, -/*025e*/ 0x55555a5a, -/*025f*/ 0x0e0e0001, -/*0260*/ 0x0c0c000e, -/*0261*/ 0x0601000c, -/*0262*/ 0x17170106, -/*0263*/ 0x00020202, -/*0264*/ 0x03000000, -/*0265*/ 0x00000000, -/*0266*/ 0x00181703, -/*0267*/ 0x00280006, -/*0268*/ 0x00280016, -/*0269*/ 0x00000016, -/*026a*/ 0x00000000, -/*026b*/ 0x00000000, -/*026c*/ 0x00000000, -/*026d*/ 0x0a000000, -/*026e*/ 0x00010a14, -/*026f*/ 0x00030005, -/*0270*/ 0x0003018d, -/*0271*/ 0x000a018d, -/*0272*/ 0x00060100, -/*0273*/ 0x01000006, -/*0274*/ 0x018e018e, -/*0275*/ 0x018e0100, -/*0276*/ 0x1111018e, -/*0277*/ 0x10010204, -/*0278*/ 0x09090650, -/*0279*/ 0xff110202, -/*027a*/ 0x00ff1000, -/*027b*/ 0x00ff1000, -/*027c*/ 0x04041000, -/*027d*/ 0x18020100, -/*027e*/ 0x01010018, -/*027f*/ 0x004a004a, -/*0280*/ 0x004b004a, -/*0281*/ 0x050f0000, -/*0282*/ 0x0c01021e, -/*0283*/ 0x34000000, -/*0284*/ 0x00000000, -/*0285*/ 0x00000000, -/*0286*/ 0x00000000, -/*0287*/ 0x00000000, -/*0288*/ 0x36312ed4, -/*0289*/ 0x2ed41111, -/*028a*/ 0x11113631, -/*028b*/ 0x36312ed4, -/*028c*/ 0xd4001111, -/*028d*/ 0x1136312e, -/*028e*/ 0x312ed411, -/*028f*/ 0xd4111136, -/*0290*/ 0x1136312e, -/*0291*/ 0x2ed40011, -/*0292*/ 0x11113631, -/*0293*/ 0x36312ed4, -/*0294*/ 0x2ed41111, -/*0295*/ 0x11113631, -/*0296*/ 0x312ed400, -/*0297*/ 0xd4111136, -/*0298*/ 0x1136312e, -/*0299*/ 0x312ed411, -/*029a*/ 0x00111136, -/*029b*/ 0x018d0200, -/*029c*/ 0x018d018d, -/*029d*/ 0x1d220c08, -/*029e*/ 0x00001f12, -/*029f*/ 0x4301b344, -/*02a0*/ 0x10172006, -/*02a1*/ 0x121d220c, -/*02a2*/ 0x01b3441f, -/*02a3*/ 0x17200643, -/*02a4*/ 0x1d220c10, -/*02a5*/ 0x00001f12, -/*02a6*/ 0x4301b344, -/*02a7*/ 0x10172006, -/*02a8*/ 0x00020002, -/*02a9*/ 0x00020002, -/*02aa*/ 0x00020002, -/*02ab*/ 0x00020002, -/*02ac*/ 0x00020002, -/*02ad*/ 0x00000000, -/*02ae*/ 0x00000000, -/*02af*/ 0x00000000, -/*02b0*/ 0x00000000, -/*02b1*/ 0x00000000, -/*02b2*/ 0x00000000, -/*02b3*/ 0x00000000, -/*02b4*/ 0x00000000, -/*02b5*/ 0x00000000, -/*02b6*/ 0x00000000, -/*02b7*/ 0x00000000, -/*02b8*/ 0x00000000, -/*02b9*/ 0x00000400, -/*02ba*/ 0x05040302, -/*02bb*/ 0x01000f0e, -/*02bc*/ 0x07060504, -/*02bd*/ 0x03020100, -/*02be*/ 0x02010000, -/*02bf*/ 0x00000103, -/*02c0*/ 0x0000304c, -/*02c1*/ 0x0001e2f8, -/*02c2*/ 0x0000304c, -/*02c3*/ 0x0001e2f8, -/*02c4*/ 0x0000304c, -/*02c5*/ 0x0001e2f8, -/*02c6*/ 0x08000000, -/*02c7*/ 0x00000100, -/*02c8*/ 0x00000000, -/*02c9*/ 0x00000000, -/*02ca*/ 0x00000000, -/*02cb*/ 0x00000000, -/*02cc*/ 0x00010000, -/*02cd*/ 0x00000000, -/*02ce*/ 0x00000000, -/*02cf*/ 0x00000000, -/*02d0*/ 0x00000000, -/*02d1*/ 0x00000000, -/*02d2*/ 0x00000000, -/*02d3*/ 0x00000000, -/*02d4*/ 0x00000000, -/*02d5*/ 0x00000000, -/*02d6*/ 0x00000000, -/*02d7*/ 0x00000000, -/*02d8*/ 0x00000000, -/*02d9*/ 0x00000000, -/*02da*/ 0x00000000, -/*02db*/ 0x00000000, -/*02dc*/ 0x00000000, -/*02dd*/ 0x00000000, -/*02de*/ 0x00000000, -/*02df*/ 0x00000000, -/*02e0*/ 0x00000000, -/*02e1*/ 0x00000000, -/*02e2*/ 0x00000000, -/*02e3*/ 0x00000000, -/*02e4*/ 0x00000000, -/*02e5*/ 0x00000000, -/*02e6*/ 0x00000000, -/*02e7*/ 0x00000000, -/*02e8*/ 0x00000000, -/*02e9*/ 0x00000000, -/*02ea*/ 0x00000000, -/*02eb*/ 0x00000000, -/*02ec*/ 0x00000000, -/*02ed*/ 0x00000000, -/*02ee*/ 0x00000002, -/*02ef*/ 0x00000000, -/*02f0*/ 0x00000000, -/*02f1*/ 0x00000000, -/*02f2*/ 0x00000000, -/*02f3*/ 0x00000000, -/*02f4*/ 0x00000000 + /*0200*/ 0x00000b00, + /*0201*/ 0x00000100, + /*0202*/ 0x00640000, + /*0203*/ 0x00000000, + /*0204*/ 0x0000ffff, + /*0205*/ 0x00000000, + /*0206*/ 0x0000ffff, + /*0207*/ 0x00000000, + /*0208*/ 0x0000ffff, + /*0209*/ 0x0000304c, + /*020a*/ 0x00000200, + /*020b*/ 0x00000200, + /*020c*/ 0x00000200, + /*020d*/ 0x00000200, + /*020e*/ 0x0000304c, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x00000200, + /*0212*/ 0x00000200, + /*0213*/ 0x0000304c, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00000200, + /*0217*/ 0x00000200, + /*0218*/ 0x00010000, + /*0219*/ 0x00000003, + /*021a*/ 0x01000001, + /*021b*/ 0x00000000, + /*021c*/ 0x00000000, + /*021d*/ 0x00000000, + /*021e*/ 0x00000000, + /*021f*/ 0x00000000, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x00000000, + /*022a*/ 0x00000000, + /*022b*/ 0x0f000101, + /*022c*/ 0x08492d25, + /*022d*/ 0x500e0c04, + /*022e*/ 0x0002500e, + /*022f*/ 0x00000301, + /*0230*/ 0x00000046, + /*0231*/ 0x000000cf, + /*0232*/ 0x00001826, + /*0233*/ 0x000000cf, + /*0234*/ 0x00001826, + /*0235*/ 0x00000005, + /*0236*/ 0x00000000, + /*0237*/ 0x00000000, + /*0238*/ 0x00000000, + /*0239*/ 0x00000000, + /*023a*/ 0x00000000, + /*023b*/ 0x00000000, + /*023c*/ 0x00000000, + /*023d*/ 0x00000000, + /*023e*/ 0x04010000, + /*023f*/ 0x00000404, + /*0240*/ 0x0101280a, + /*0241*/ 0x00000000, + /*0242*/ 0x00000000, + /*0243*/ 0x0003000f, + /*0244*/ 0x00000018, + /*0245*/ 0x00000000, + /*0246*/ 0x00000000, + /*0247*/ 0x00060002, + /*0248*/ 0x00010001, + /*0249*/ 0x01000101, + /*024a*/ 0x04020201, + /*024b*/ 0x00080804, + /*024c*/ 0x00000000, + /*024d*/ 0x08030000, + /*024e*/ 0x15150408, + /*024f*/ 0x00000000, + /*0250*/ 0x00000000, + /*0251*/ 0x00000000, + /*0252*/ 0x0f0f0000, + /*0253*/ 0x0000001e, + /*0254*/ 0x00000000, + /*0255*/ 0x01000300, + /*0256*/ 0x00000100, + /*0257*/ 0x00000000, + /*0258*/ 0x00000000, + /*0259*/ 0x01000000, + /*025a*/ 0x00000101, + /*025b*/ 0x55555a5a, + /*025c*/ 0x55555a5a, + /*025d*/ 0x55555a5a, + /*025e*/ 0x55555a5a, + /*025f*/ 0x0e0e0001, + /*0260*/ 0x0c0c000e, + /*0261*/ 0x0601000c, + /*0262*/ 0x17170106, + /*0263*/ 0x00020202, + /*0264*/ 0x03000000, + /*0265*/ 0x00000000, + /*0266*/ 0x00181703, + /*0267*/ 0x00280006, + /*0268*/ 0x00280016, + /*0269*/ 0x00000016, + /*026a*/ 0x00000000, + /*026b*/ 0x00000000, + /*026c*/ 0x00000000, + /*026d*/ 0x0a000000, + /*026e*/ 0x00010a14, + /*026f*/ 0x00030005, + /*0270*/ 0x0003018d, + /*0271*/ 0x000a018d, + /*0272*/ 0x00060100, + /*0273*/ 0x01000006, + /*0274*/ 0x018e018e, + /*0275*/ 0x018e0100, + /*0276*/ 0x1111018e, + /*0277*/ 0x10010204, + /*0278*/ 0x09090650, + /*0279*/ 0xff110202, + /*027a*/ 0x00ff1000, + /*027b*/ 0x00ff1000, + /*027c*/ 0x04041000, + /*027d*/ 0x18020100, + /*027e*/ 0x01010018, + /*027f*/ 0x004a004a, + /*0280*/ 0x004b004a, + /*0281*/ 0x050f0000, + /*0282*/ 0x0c01021e, + /*0283*/ 0x34000000, + /*0284*/ 0x00000000, + /*0285*/ 0x00000000, + /*0286*/ 0x00000000, + /*0287*/ 0x00000000, + /*0288*/ 0x36312ed4, + /*0289*/ 0x2ed41111, + /*028a*/ 0x11113631, + /*028b*/ 0x36312ed4, + /*028c*/ 0xd4001111, + /*028d*/ 0x1136312e, + /*028e*/ 0x312ed411, + /*028f*/ 0xd4111136, + /*0290*/ 0x1136312e, + /*0291*/ 0x2ed40011, + /*0292*/ 0x11113631, + /*0293*/ 0x36312ed4, + /*0294*/ 0x2ed41111, + /*0295*/ 0x11113631, + /*0296*/ 0x312ed400, + /*0297*/ 0xd4111136, + /*0298*/ 0x1136312e, + /*0299*/ 0x312ed411, + /*029a*/ 0x00111136, + /*029b*/ 0x018d0200, + /*029c*/ 0x018d018d, + /*029d*/ 0x1d220c08, + /*029e*/ 0x00001f12, + /*029f*/ 0x4301b344, + /*02a0*/ 0x10172006, + /*02a1*/ 0x121d220c, + /*02a2*/ 0x01b3441f, + /*02a3*/ 0x17200643, + /*02a4*/ 0x1d220c10, + /*02a5*/ 0x00001f12, + /*02a6*/ 0x4301b344, + /*02a7*/ 0x10172006, + /*02a8*/ 0x00020002, + /*02a9*/ 0x00020002, + /*02aa*/ 0x00020002, + /*02ab*/ 0x00020002, + /*02ac*/ 0x00020002, + /*02ad*/ 0x00000000, + /*02ae*/ 0x00000000, + /*02af*/ 0x00000000, + /*02b0*/ 0x00000000, + /*02b1*/ 0x00000000, + /*02b2*/ 0x00000000, + /*02b3*/ 0x00000000, + /*02b4*/ 0x00000000, + /*02b5*/ 0x00000000, + /*02b6*/ 0x00000000, + /*02b7*/ 0x00000000, + /*02b8*/ 0x00000000, + /*02b9*/ 0x00000400, + /*02ba*/ 0x05040302, + /*02bb*/ 0x01000f0e, + /*02bc*/ 0x07060504, + /*02bd*/ 0x03020100, + /*02be*/ 0x02010000, + /*02bf*/ 0x00000103, + /*02c0*/ 0x0000304c, + /*02c1*/ 0x0001e2f8, + /*02c2*/ 0x0000304c, + /*02c3*/ 0x0001e2f8, + /*02c4*/ 0x0000304c, + /*02c5*/ 0x0001e2f8, + /*02c6*/ 0x08000000, + /*02c7*/ 0x00000100, + /*02c8*/ 0x00000000, + /*02c9*/ 0x00000000, + /*02ca*/ 0x00000000, + /*02cb*/ 0x00000000, + /*02cc*/ 0x00010000, + /*02cd*/ 0x00000000, + /*02ce*/ 0x00000000, + /*02cf*/ 0x00000000, + /*02d0*/ 0x00000000, + /*02d1*/ 0x00000000, + /*02d2*/ 0x00000000, + /*02d3*/ 0x00000000, + /*02d4*/ 0x00000000, + /*02d5*/ 0x00000000, + /*02d6*/ 0x00000000, + /*02d7*/ 0x00000000, + /*02d8*/ 0x00000000, + /*02d9*/ 0x00000000, + /*02da*/ 0x00000000, + /*02db*/ 0x00000000, + /*02dc*/ 0x00000000, + /*02dd*/ 0x00000000, + /*02de*/ 0x00000000, + /*02df*/ 0x00000000, + /*02e0*/ 0x00000000, + /*02e1*/ 0x00000000, + /*02e2*/ 0x00000000, + /*02e3*/ 0x00000000, + /*02e4*/ 0x00000000, + /*02e5*/ 0x00000000, + /*02e6*/ 0x00000000, + /*02e7*/ 0x00000000, + /*02e8*/ 0x00000000, + /*02e9*/ 0x00000000, + /*02ea*/ 0x00000000, + /*02eb*/ 0x00000000, + /*02ec*/ 0x00000000, + /*02ed*/ 0x00000000, + /*02ee*/ 0x00000002, + /*02ef*/ 0x00000000, + /*02f0*/ 0x00000000, + /*02f1*/ 0x00000000, + /*02f2*/ 0x00000000, + /*02f3*/ 0x00000000, + /*02f4*/ 0x00000000 }; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h index 3c62107e..a09b0041 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,445 +24,445 @@ #define DDR_PI_REGSET_NUM_M3 202 static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = { -/*0800*/ 0x76543210, -/*0801*/ 0x0004f008, -/*0802*/ 0x00000000, -/*0803*/ 0x00000000, -/*0804*/ 0x00010000, -/*0805*/ 0x036e6e0e, -/*0806*/ 0x026e6e0e, -/*0807*/ 0x00010300, -/*0808*/ 0x04000100, -/*0809*/ 0x00000300, -/*080a*/ 0x001700c0, -/*080b*/ 0x00b00201, -/*080c*/ 0x00030020, -/*080d*/ 0x00000000, -/*080e*/ 0x00000000, -/*080f*/ 0x00000000, -/*0810*/ 0x00000000, -/*0811*/ 0x00000000, -/*0812*/ 0x00000000, -/*0813*/ 0x00000000, -/*0814*/ 0x09000000, -/*0815*/ 0x04080000, -/*0816*/ 0x04080400, -/*0817*/ 0x00000000, -/*0818*/ 0x32103210, -/*0819*/ 0x00800708, -/*081a*/ 0x000f000c, -/*081b*/ 0x00000100, -/*081c*/ 0x55aa55aa, -/*081d*/ 0x33cc33cc, -/*081e*/ 0x0ff00ff0, -/*081f*/ 0x0f0ff0f0, -/*0820*/ 0x00018e38, -/*0821*/ 0x00000000, -/*0822*/ 0x00000000, -/*0823*/ 0x00000000, -/*0824*/ 0x00000000, -/*0825*/ 0x00000000, -/*0826*/ 0x00000000, -/*0827*/ 0x00000000, -/*0828*/ 0x00000000, -/*0829*/ 0x00000000, -/*082a*/ 0x00000000, -/*082b*/ 0x00000000, -/*082c*/ 0x00000000, -/*082d*/ 0x00000000, -/*082e*/ 0x00000000, -/*082f*/ 0x00000000, -/*0830*/ 0x00000000, -/*0831*/ 0x00000000, -/*0832*/ 0x00000000, -/*0833*/ 0x00200000, -/*0834*/ 0x08200820, -/*0835*/ 0x08200820, -/*0836*/ 0x08200820, -/*0837*/ 0x08200820, -/*0838*/ 0x08200820, -/*0839*/ 0x00000820, -/*083a*/ 0x03000300, -/*083b*/ 0x03000300, -/*083c*/ 0x03000300, -/*083d*/ 0x03000300, -/*083e*/ 0x00000300, -/*083f*/ 0x00000000, -/*0840*/ 0x00000000, -/*0841*/ 0x00000000, -/*0842*/ 0x00000000, -/*0843*/ 0x00a00000, -/*0844*/ 0x00a000a0, -/*0845*/ 0x00a000a0, -/*0846*/ 0x00a000a0, -/*0847*/ 0x00a000a0, -/*0848*/ 0x00a000a0, -/*0849*/ 0x00a000a0, -/*084a*/ 0x00a000a0, -/*084b*/ 0x00a000a0, -/*084c*/ 0x010900a0, -/*084d*/ 0x02000104, -/*084e*/ 0x00000000, -/*084f*/ 0x00010000, -/*0850*/ 0x00000200, -/*0851*/ 0x4041a141, -/*0852*/ 0xc00141a0, -/*0853*/ 0x0e0100c0, -/*0854*/ 0x0010000c, -/*0855*/ 0x0c064208, -/*0856*/ 0x000f0c18, -/*0857*/ 0x00e00140, -/*0858*/ 0x00000c20 + /*0800*/ 0x76543210, + /*0801*/ 0x0004f008, + /*0802*/ 0x00000000, + /*0803*/ 0x00000000, + /*0804*/ 0x00010000, + /*0805*/ 0x036e6e0e, + /*0806*/ 0x026e6e0e, + /*0807*/ 0x00010300, + /*0808*/ 0x04000100, + /*0809*/ 0x00000300, + /*080a*/ 0x001700c0, + /*080b*/ 0x00b00201, + /*080c*/ 0x00030020, + /*080d*/ 0x00000000, + /*080e*/ 0x00000000, + /*080f*/ 0x00000000, + /*0810*/ 0x00000000, + /*0811*/ 0x00000000, + /*0812*/ 0x00000000, + /*0813*/ 0x00000000, + /*0814*/ 0x09000000, + /*0815*/ 0x04080000, + /*0816*/ 0x04080400, + /*0817*/ 0x00000000, + /*0818*/ 0x32103210, + /*0819*/ 0x00800708, + /*081a*/ 0x000f000c, + /*081b*/ 0x00000100, + /*081c*/ 0x55aa55aa, + /*081d*/ 0x33cc33cc, + /*081e*/ 0x0ff00ff0, + /*081f*/ 0x0f0ff0f0, + /*0820*/ 0x00018e38, + /*0821*/ 0x00000000, + /*0822*/ 0x00000000, + /*0823*/ 0x00000000, + /*0824*/ 0x00000000, + /*0825*/ 0x00000000, + /*0826*/ 0x00000000, + /*0827*/ 0x00000000, + /*0828*/ 0x00000000, + /*0829*/ 0x00000000, + /*082a*/ 0x00000000, + /*082b*/ 0x00000000, + /*082c*/ 0x00000000, + /*082d*/ 0x00000000, + /*082e*/ 0x00000000, + /*082f*/ 0x00000000, + /*0830*/ 0x00000000, + /*0831*/ 0x00000000, + /*0832*/ 0x00000000, + /*0833*/ 0x00200000, + /*0834*/ 0x08200820, + /*0835*/ 0x08200820, + /*0836*/ 0x08200820, + /*0837*/ 0x08200820, + /*0838*/ 0x08200820, + /*0839*/ 0x00000820, + /*083a*/ 0x03000300, + /*083b*/ 0x03000300, + /*083c*/ 0x03000300, + /*083d*/ 0x03000300, + /*083e*/ 0x00000300, + /*083f*/ 0x00000000, + /*0840*/ 0x00000000, + /*0841*/ 0x00000000, + /*0842*/ 0x00000000, + /*0843*/ 0x00a00000, + /*0844*/ 0x00a000a0, + /*0845*/ 0x00a000a0, + /*0846*/ 0x00a000a0, + /*0847*/ 0x00a000a0, + /*0848*/ 0x00a000a0, + /*0849*/ 0x00a000a0, + /*084a*/ 0x00a000a0, + /*084b*/ 0x00a000a0, + /*084c*/ 0x010900a0, + /*084d*/ 0x02000104, + /*084e*/ 0x00000000, + /*084f*/ 0x00010000, + /*0850*/ 0x00000200, + /*0851*/ 0x4041a141, + /*0852*/ 0xc00141a0, + /*0853*/ 0x0e0100c0, + /*0854*/ 0x0010000c, + /*0855*/ 0x0c064208, + /*0856*/ 0x000f0c18, + /*0857*/ 0x00e00140, + /*0858*/ 0x00000c20 }; static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = { -/*0a00*/ 0x00000000, -/*0a01*/ 0x00000000, -/*0a02*/ 0x00000000, -/*0a03*/ 0x00000000, -/*0a04*/ 0x00000000, -/*0a05*/ 0x00000000, -/*0a06*/ 0x00000002, -/*0a07*/ 0x00000000, -/*0a08*/ 0x00000000, -/*0a09*/ 0x00000000, -/*0a0a*/ 0x00400320, -/*0a0b*/ 0x00000040, -/*0a0c*/ 0x00dcba98, -/*0a0d*/ 0x00000000, -/*0a0e*/ 0x00dcba98, -/*0a0f*/ 0x01000000, -/*0a10*/ 0x00020003, -/*0a11*/ 0x00000000, -/*0a12*/ 0x00000000, -/*0a13*/ 0x00000000, -/*0a14*/ 0x0000002a, -/*0a15*/ 0x00000015, -/*0a16*/ 0x00000015, -/*0a17*/ 0x0000002a, -/*0a18*/ 0x00000033, -/*0a19*/ 0x0000000c, -/*0a1a*/ 0x0000000c, -/*0a1b*/ 0x00000033, -/*0a1c*/ 0x0a418820, -/*0a1d*/ 0x003f0000, -/*0a1e*/ 0x0000003f, -/*0a1f*/ 0x0002c06e, -/*0a20*/ 0x02c002c0, -/*0a21*/ 0x02c002c0, -/*0a22*/ 0x000002c0, -/*0a23*/ 0x42080010, -/*0a24*/ 0x00000003 + /*0a00*/ 0x00000000, + /*0a01*/ 0x00000000, + /*0a02*/ 0x00000000, + /*0a03*/ 0x00000000, + /*0a04*/ 0x00000000, + /*0a05*/ 0x00000000, + /*0a06*/ 0x00000002, + /*0a07*/ 0x00000000, + /*0a08*/ 0x00000000, + /*0a09*/ 0x00000000, + /*0a0a*/ 0x00400320, + /*0a0b*/ 0x00000040, + /*0a0c*/ 0x00dcba98, + /*0a0d*/ 0x00000000, + /*0a0e*/ 0x00dcba98, + /*0a0f*/ 0x01000000, + /*0a10*/ 0x00020003, + /*0a11*/ 0x00000000, + /*0a12*/ 0x00000000, + /*0a13*/ 0x00000000, + /*0a14*/ 0x0000002a, + /*0a15*/ 0x00000015, + /*0a16*/ 0x00000015, + /*0a17*/ 0x0000002a, + /*0a18*/ 0x00000033, + /*0a19*/ 0x0000000c, + /*0a1a*/ 0x0000000c, + /*0a1b*/ 0x00000033, + /*0a1c*/ 0x0a418820, + /*0a1d*/ 0x003f0000, + /*0a1e*/ 0x0000003f, + /*0a1f*/ 0x0002c06e, + /*0a20*/ 0x02c002c0, + /*0a21*/ 0x02c002c0, + /*0a22*/ 0x000002c0, + /*0a23*/ 0x42080010, + /*0a24*/ 0x00000003 }; static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = { -/*0a80*/ 0x04040404, -/*0a81*/ 0x00000404, -/*0a82*/ 0x00000000, -/*0a83*/ 0x00000000, -/*0a84*/ 0x00000000, -/*0a85*/ 0x00000000, -/*0a86*/ 0x00000002, -/*0a87*/ 0x00000000, -/*0a88*/ 0x00000000, -/*0a89*/ 0x00000000, -/*0a8a*/ 0x00400320, -/*0a8b*/ 0x00000040, -/*0a8c*/ 0x00000000, -/*0a8d*/ 0x00000000, -/*0a8e*/ 0x00000000, -/*0a8f*/ 0x01000000, -/*0a90*/ 0x00020003, -/*0a91*/ 0x00000000, -/*0a92*/ 0x00000000, -/*0a93*/ 0x00000000, -/*0a94*/ 0x0000002a, -/*0a95*/ 0x00000015, -/*0a96*/ 0x00000015, -/*0a97*/ 0x0000002a, -/*0a98*/ 0x00000033, -/*0a99*/ 0x0000000c, -/*0a9a*/ 0x0000000c, -/*0a9b*/ 0x00000033, -/*0a9c*/ 0x00000000, -/*0a9d*/ 0x00000000, -/*0a9e*/ 0x00000000, -/*0a9f*/ 0x0002c06e, -/*0aa0*/ 0x02c002c0, -/*0aa1*/ 0x02c002c0, -/*0aa2*/ 0x000002c0, -/*0aa3*/ 0x42080010, -/*0aa4*/ 0x00000003 + /*0a80*/ 0x04040404, + /*0a81*/ 0x00000404, + /*0a82*/ 0x00000000, + /*0a83*/ 0x00000000, + /*0a84*/ 0x00000000, + /*0a85*/ 0x00000000, + /*0a86*/ 0x00000002, + /*0a87*/ 0x00000000, + /*0a88*/ 0x00000000, + /*0a89*/ 0x00000000, + /*0a8a*/ 0x00400320, + /*0a8b*/ 0x00000040, + /*0a8c*/ 0x00000000, + /*0a8d*/ 0x00000000, + /*0a8e*/ 0x00000000, + /*0a8f*/ 0x01000000, + /*0a90*/ 0x00020003, + /*0a91*/ 0x00000000, + /*0a92*/ 0x00000000, + /*0a93*/ 0x00000000, + /*0a94*/ 0x0000002a, + /*0a95*/ 0x00000015, + /*0a96*/ 0x00000015, + /*0a97*/ 0x0000002a, + /*0a98*/ 0x00000033, + /*0a99*/ 0x0000000c, + /*0a9a*/ 0x0000000c, + /*0a9b*/ 0x00000033, + /*0a9c*/ 0x00000000, + /*0a9d*/ 0x00000000, + /*0a9e*/ 0x00000000, + /*0a9f*/ 0x0002c06e, + /*0aa0*/ 0x02c002c0, + /*0aa1*/ 0x02c002c0, + /*0aa2*/ 0x000002c0, + /*0aa3*/ 0x42080010, + /*0aa4*/ 0x00000003 }; static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = { -/*0b80*/ 0x00000001, -/*0b81*/ 0x00000000, -/*0b82*/ 0x00000005, -/*0b83*/ 0x04000f00, -/*0b84*/ 0x00020080, -/*0b85*/ 0x00020055, -/*0b86*/ 0x00000000, -/*0b87*/ 0x00000000, -/*0b88*/ 0x00000000, -/*0b89*/ 0x00000050, -/*0b8a*/ 0x00000000, -/*0b8b*/ 0x01010100, -/*0b8c*/ 0x00000600, -/*0b8d*/ 0x50640000, -/*0b8e*/ 0x01421142, -/*0b8f*/ 0x00000142, -/*0b90*/ 0x00000000, -/*0b91*/ 0x000f1600, -/*0b92*/ 0x0f160f16, -/*0b93*/ 0x0f160f16, -/*0b94*/ 0x00000003, -/*0b95*/ 0x0002c000, -/*0b96*/ 0x02c002c0, -/*0b97*/ 0x000002c0, -/*0b98*/ 0x03421342, -/*0b99*/ 0x00000342, -/*0b9a*/ 0x00000000, -/*0b9b*/ 0x00000000, -/*0b9c*/ 0x05020000, -/*0b9d*/ 0x00000000, -/*0b9e*/ 0x00027f6e, -/*0b9f*/ 0x047f027f, -/*0ba0*/ 0x00027f6e, -/*0ba1*/ 0x00047f6e, -/*0ba2*/ 0x0003554f, -/*0ba3*/ 0x0001554f, -/*0ba4*/ 0x0001554f, -/*0ba5*/ 0x0001554f, -/*0ba6*/ 0x0001554f, -/*0ba7*/ 0x00003fee, -/*0ba8*/ 0x0001554f, -/*0ba9*/ 0x00003fee, -/*0baa*/ 0x0001554f, -/*0bab*/ 0x00027f6e, -/*0bac*/ 0x0001554f, -/*0bad*/ 0x00000000, -/*0bae*/ 0x00000000, -/*0baf*/ 0x00000000, -/*0bb0*/ 0x65000000, -/*0bb1*/ 0x00000000, -/*0bb2*/ 0x00000000, -/*0bb3*/ 0x00000201, -/*0bb4*/ 0x00000000, -/*0bb5*/ 0x00000000, -/*0bb6*/ 0x00000000, -/*0bb7*/ 0x00000000, -/*0bb8*/ 0x00000000, -/*0bb9*/ 0x00000000, -/*0bba*/ 0x00000000, -/*0bbb*/ 0x00000000, -/*0bbc*/ 0x06e40000, -/*0bbd*/ 0x00000000, -/*0bbe*/ 0x00000000, -/*0bbf*/ 0x00010000 + /*0b80*/ 0x00000001, + /*0b81*/ 0x00000000, + /*0b82*/ 0x00000005, + /*0b83*/ 0x04000f00, + /*0b84*/ 0x00020080, + /*0b85*/ 0x00020055, + /*0b86*/ 0x00000000, + /*0b87*/ 0x00000000, + /*0b88*/ 0x00000000, + /*0b89*/ 0x00000050, + /*0b8a*/ 0x00000000, + /*0b8b*/ 0x01010100, + /*0b8c*/ 0x00000600, + /*0b8d*/ 0x50640000, + /*0b8e*/ 0x01421142, + /*0b8f*/ 0x00000142, + /*0b90*/ 0x00000000, + /*0b91*/ 0x000f1600, + /*0b92*/ 0x0f160f16, + /*0b93*/ 0x0f160f16, + /*0b94*/ 0x00000003, + /*0b95*/ 0x0002c000, + /*0b96*/ 0x02c002c0, + /*0b97*/ 0x000002c0, + /*0b98*/ 0x03421342, + /*0b99*/ 0x00000342, + /*0b9a*/ 0x00000000, + /*0b9b*/ 0x00000000, + /*0b9c*/ 0x05020000, + /*0b9d*/ 0x00000000, + /*0b9e*/ 0x00027f6e, + /*0b9f*/ 0x047f027f, + /*0ba0*/ 0x00027f6e, + /*0ba1*/ 0x00047f6e, + /*0ba2*/ 0x0003554f, + /*0ba3*/ 0x0001554f, + /*0ba4*/ 0x0001554f, + /*0ba5*/ 0x0001554f, + /*0ba6*/ 0x0001554f, + /*0ba7*/ 0x00003fee, + /*0ba8*/ 0x0001554f, + /*0ba9*/ 0x00003fee, + /*0baa*/ 0x0001554f, + /*0bab*/ 0x00027f6e, + /*0bac*/ 0x0001554f, + /*0bad*/ 0x00000000, + /*0bae*/ 0x00000000, + /*0baf*/ 0x00000000, + /*0bb0*/ 0x65000000, + /*0bb1*/ 0x00000000, + /*0bb2*/ 0x00000000, + /*0bb3*/ 0x00000201, + /*0bb4*/ 0x00000000, + /*0bb5*/ 0x00000000, + /*0bb6*/ 0x00000000, + /*0bb7*/ 0x00000000, + /*0bb8*/ 0x00000000, + /*0bb9*/ 0x00000000, + /*0bba*/ 0x00000000, + /*0bbb*/ 0x00000000, + /*0bbc*/ 0x06e40000, + /*0bbd*/ 0x00000000, + /*0bbe*/ 0x00000000, + /*0bbf*/ 0x00010000 }; static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000100, -/*0202*/ 0x00000000, -/*0203*/ 0x0000ffff, -/*0204*/ 0x00000000, -/*0205*/ 0x0000ffff, -/*0206*/ 0x00000000, -/*0207*/ 0x304cffff, -/*0208*/ 0x00000200, -/*0209*/ 0x00000200, -/*020a*/ 0x00000200, -/*020b*/ 0x00000200, -/*020c*/ 0x0000304c, -/*020d*/ 0x00000200, -/*020e*/ 0x00000200, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x0000304c, -/*0212*/ 0x00000200, -/*0213*/ 0x00000200, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00010000, -/*0217*/ 0x00000003, -/*0218*/ 0x01000001, -/*0219*/ 0x00000000, -/*021a*/ 0x00000000, -/*021b*/ 0x00000000, -/*021c*/ 0x00000000, -/*021d*/ 0x00000000, -/*021e*/ 0x00000000, -/*021f*/ 0x00000000, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x0f000101, -/*022a*/ 0x08492d25, -/*022b*/ 0x0e0c0004, -/*022c*/ 0x000e5000, -/*022d*/ 0x00000250, -/*022e*/ 0x00460003, -/*022f*/ 0x182600cf, -/*0230*/ 0x182600cf, -/*0231*/ 0x00000005, -/*0232*/ 0x00000000, -/*0233*/ 0x00000000, -/*0234*/ 0x00000000, -/*0235*/ 0x00000000, -/*0236*/ 0x00000000, -/*0237*/ 0x00000000, -/*0238*/ 0x00000000, -/*0239*/ 0x01000000, -/*023a*/ 0x00040404, -/*023b*/ 0x01280a00, -/*023c*/ 0x00000000, -/*023d*/ 0x000f0000, -/*023e*/ 0x00001803, -/*023f*/ 0x00000000, -/*0240*/ 0x00000000, -/*0241*/ 0x00060002, -/*0242*/ 0x00010001, -/*0243*/ 0x01000101, -/*0244*/ 0x04020201, -/*0245*/ 0x00080804, -/*0246*/ 0x00000000, -/*0247*/ 0x08030000, -/*0248*/ 0x15150408, -/*0249*/ 0x00000000, -/*024a*/ 0x00000000, -/*024b*/ 0x00000000, -/*024c*/ 0x000f0f00, -/*024d*/ 0x0000001e, -/*024e*/ 0x00000000, -/*024f*/ 0x01000300, -/*0250*/ 0x00000000, -/*0251*/ 0x00000000, -/*0252*/ 0x01000000, -/*0253*/ 0x00010101, -/*0254*/ 0x000e0e0e, -/*0255*/ 0x000c0c0c, -/*0256*/ 0x02060601, -/*0257*/ 0x00000000, -/*0258*/ 0x00000003, -/*0259*/ 0x00181703, -/*025a*/ 0x00280006, -/*025b*/ 0x00280016, -/*025c*/ 0x00000016, -/*025d*/ 0x00000000, -/*025e*/ 0x00000000, -/*025f*/ 0x00000000, -/*0260*/ 0x140a0000, -/*0261*/ 0x0005010a, -/*0262*/ 0x03018d03, -/*0263*/ 0x000a018d, -/*0264*/ 0x00060100, -/*0265*/ 0x01000006, -/*0266*/ 0x018e018e, -/*0267*/ 0x018e0100, -/*0268*/ 0x1111018e, -/*0269*/ 0x10010204, -/*026a*/ 0x09090650, -/*026b*/ 0x20110202, -/*026c*/ 0x00201000, -/*026d*/ 0x00201000, -/*026e*/ 0x04041000, -/*026f*/ 0x18020100, -/*0270*/ 0x00010118, -/*0271*/ 0x004b004a, -/*0272*/ 0x050f0000, -/*0273*/ 0x0c01021e, -/*0274*/ 0x34000000, -/*0275*/ 0x00000000, -/*0276*/ 0x00000000, -/*0277*/ 0x00000000, -/*0278*/ 0x0000d400, -/*0279*/ 0x0031002e, -/*027a*/ 0x00111136, -/*027b*/ 0x002e00d4, -/*027c*/ 0x11360031, -/*027d*/ 0x0000d411, -/*027e*/ 0x0031002e, -/*027f*/ 0x00111136, -/*0280*/ 0x002e00d4, -/*0281*/ 0x11360031, -/*0282*/ 0x0000d411, -/*0283*/ 0x0031002e, -/*0284*/ 0x00111136, -/*0285*/ 0x002e00d4, -/*0286*/ 0x11360031, -/*0287*/ 0x00d40011, -/*0288*/ 0x0031002e, -/*0289*/ 0x00111136, -/*028a*/ 0x002e00d4, -/*028b*/ 0x11360031, -/*028c*/ 0x0000d411, -/*028d*/ 0x0031002e, -/*028e*/ 0x00111136, -/*028f*/ 0x002e00d4, -/*0290*/ 0x11360031, -/*0291*/ 0x0000d411, -/*0292*/ 0x0031002e, -/*0293*/ 0x00111136, -/*0294*/ 0x002e00d4, -/*0295*/ 0x11360031, -/*0296*/ 0x02000011, -/*0297*/ 0x018d018d, -/*0298*/ 0x0c08018d, -/*0299*/ 0x1f121d22, -/*029a*/ 0x4301b344, -/*029b*/ 0x10172006, -/*029c*/ 0x1d220c10, -/*029d*/ 0x00001f12, -/*029e*/ 0x4301b344, -/*029f*/ 0x10172006, -/*02a0*/ 0x1d220c10, -/*02a1*/ 0x00001f12, -/*02a2*/ 0x4301b344, -/*02a3*/ 0x10172006, -/*02a4*/ 0x02000210, -/*02a5*/ 0x02000200, -/*02a6*/ 0x02000200, -/*02a7*/ 0x02000200, -/*02a8*/ 0x02000200, -/*02a9*/ 0x00000000, -/*02aa*/ 0x00000000, -/*02ab*/ 0x00000000, -/*02ac*/ 0x00000000, -/*02ad*/ 0x00000000, -/*02ae*/ 0x00000000, -/*02af*/ 0x00000000, -/*02b0*/ 0x00000000, -/*02b1*/ 0x00000000, -/*02b2*/ 0x00000000, -/*02b3*/ 0x00000000, -/*02b4*/ 0x00000000, -/*02b5*/ 0x00000400, -/*02b6*/ 0x15141312, -/*02b7*/ 0x11100f0e, -/*02b8*/ 0x080b0c0d, -/*02b9*/ 0x05040a09, -/*02ba*/ 0x01000706, -/*02bb*/ 0x00000302, -/*02bc*/ 0x01030201, -/*02bd*/ 0x00304c00, -/*02be*/ 0x0001e2f8, -/*02bf*/ 0x0000304c, -/*02c0*/ 0x0001e2f8, -/*02c1*/ 0x0000304c, -/*02c2*/ 0x0001e2f8, -/*02c3*/ 0x08000000, -/*02c4*/ 0x00000100, -/*02c5*/ 0x00000000, -/*02c6*/ 0x00000000, -/*02c7*/ 0x00000000, -/*02c8*/ 0x00000000, -/*02c9*/ 0x00000002 + /*0200*/ 0x00000b00, + /*0201*/ 0x00000100, + /*0202*/ 0x00000000, + /*0203*/ 0x0000ffff, + /*0204*/ 0x00000000, + /*0205*/ 0x0000ffff, + /*0206*/ 0x00000000, + /*0207*/ 0x304cffff, + /*0208*/ 0x00000200, + /*0209*/ 0x00000200, + /*020a*/ 0x00000200, + /*020b*/ 0x00000200, + /*020c*/ 0x0000304c, + /*020d*/ 0x00000200, + /*020e*/ 0x00000200, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x0000304c, + /*0212*/ 0x00000200, + /*0213*/ 0x00000200, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00010000, + /*0217*/ 0x00000003, + /*0218*/ 0x01000001, + /*0219*/ 0x00000000, + /*021a*/ 0x00000000, + /*021b*/ 0x00000000, + /*021c*/ 0x00000000, + /*021d*/ 0x00000000, + /*021e*/ 0x00000000, + /*021f*/ 0x00000000, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x0f000101, + /*022a*/ 0x08492d25, + /*022b*/ 0x0e0c0004, + /*022c*/ 0x000e5000, + /*022d*/ 0x00000250, + /*022e*/ 0x00460003, + /*022f*/ 0x182600cf, + /*0230*/ 0x182600cf, + /*0231*/ 0x00000005, + /*0232*/ 0x00000000, + /*0233*/ 0x00000000, + /*0234*/ 0x00000000, + /*0235*/ 0x00000000, + /*0236*/ 0x00000000, + /*0237*/ 0x00000000, + /*0238*/ 0x00000000, + /*0239*/ 0x01000000, + /*023a*/ 0x00040404, + /*023b*/ 0x01280a00, + /*023c*/ 0x00000000, + /*023d*/ 0x000f0000, + /*023e*/ 0x00001803, + /*023f*/ 0x00000000, + /*0240*/ 0x00000000, + /*0241*/ 0x00060002, + /*0242*/ 0x00010001, + /*0243*/ 0x01000101, + /*0244*/ 0x04020201, + /*0245*/ 0x00080804, + /*0246*/ 0x00000000, + /*0247*/ 0x08030000, + /*0248*/ 0x15150408, + /*0249*/ 0x00000000, + /*024a*/ 0x00000000, + /*024b*/ 0x00000000, + /*024c*/ 0x000f0f00, + /*024d*/ 0x0000001e, + /*024e*/ 0x00000000, + /*024f*/ 0x01000300, + /*0250*/ 0x00000000, + /*0251*/ 0x00000000, + /*0252*/ 0x01000000, + /*0253*/ 0x00010101, + /*0254*/ 0x000e0e0e, + /*0255*/ 0x000c0c0c, + /*0256*/ 0x02060601, + /*0257*/ 0x00000000, + /*0258*/ 0x00000003, + /*0259*/ 0x00181703, + /*025a*/ 0x00280006, + /*025b*/ 0x00280016, + /*025c*/ 0x00000016, + /*025d*/ 0x00000000, + /*025e*/ 0x00000000, + /*025f*/ 0x00000000, + /*0260*/ 0x140a0000, + /*0261*/ 0x0005010a, + /*0262*/ 0x03018d03, + /*0263*/ 0x000a018d, + /*0264*/ 0x00060100, + /*0265*/ 0x01000006, + /*0266*/ 0x018e018e, + /*0267*/ 0x018e0100, + /*0268*/ 0x1111018e, + /*0269*/ 0x10010204, + /*026a*/ 0x09090650, + /*026b*/ 0x20110202, + /*026c*/ 0x00201000, + /*026d*/ 0x00201000, + /*026e*/ 0x04041000, + /*026f*/ 0x18020100, + /*0270*/ 0x00010118, + /*0271*/ 0x004b004a, + /*0272*/ 0x050f0000, + /*0273*/ 0x0c01021e, + /*0274*/ 0x34000000, + /*0275*/ 0x00000000, + /*0276*/ 0x00000000, + /*0277*/ 0x00000000, + /*0278*/ 0x0000d400, + /*0279*/ 0x0031002e, + /*027a*/ 0x00111136, + /*027b*/ 0x002e00d4, + /*027c*/ 0x11360031, + /*027d*/ 0x0000d411, + /*027e*/ 0x0031002e, + /*027f*/ 0x00111136, + /*0280*/ 0x002e00d4, + /*0281*/ 0x11360031, + /*0282*/ 0x0000d411, + /*0283*/ 0x0031002e, + /*0284*/ 0x00111136, + /*0285*/ 0x002e00d4, + /*0286*/ 0x11360031, + /*0287*/ 0x00d40011, + /*0288*/ 0x0031002e, + /*0289*/ 0x00111136, + /*028a*/ 0x002e00d4, + /*028b*/ 0x11360031, + /*028c*/ 0x0000d411, + /*028d*/ 0x0031002e, + /*028e*/ 0x00111136, + /*028f*/ 0x002e00d4, + /*0290*/ 0x11360031, + /*0291*/ 0x0000d411, + /*0292*/ 0x0031002e, + /*0293*/ 0x00111136, + /*0294*/ 0x002e00d4, + /*0295*/ 0x11360031, + /*0296*/ 0x02000011, + /*0297*/ 0x018d018d, + /*0298*/ 0x0c08018d, + /*0299*/ 0x1f121d22, + /*029a*/ 0x4301b344, + /*029b*/ 0x10172006, + /*029c*/ 0x1d220c10, + /*029d*/ 0x00001f12, + /*029e*/ 0x4301b344, + /*029f*/ 0x10172006, + /*02a0*/ 0x1d220c10, + /*02a1*/ 0x00001f12, + /*02a2*/ 0x4301b344, + /*02a3*/ 0x10172006, + /*02a4*/ 0x02000210, + /*02a5*/ 0x02000200, + /*02a6*/ 0x02000200, + /*02a7*/ 0x02000200, + /*02a8*/ 0x02000200, + /*02a9*/ 0x00000000, + /*02aa*/ 0x00000000, + /*02ab*/ 0x00000000, + /*02ac*/ 0x00000000, + /*02ad*/ 0x00000000, + /*02ae*/ 0x00000000, + /*02af*/ 0x00000000, + /*02b0*/ 0x00000000, + /*02b1*/ 0x00000000, + /*02b2*/ 0x00000000, + /*02b3*/ 0x00000000, + /*02b4*/ 0x00000000, + /*02b5*/ 0x00000400, + /*02b6*/ 0x15141312, + /*02b7*/ 0x11100f0e, + /*02b8*/ 0x080b0c0d, + /*02b9*/ 0x05040a09, + /*02ba*/ 0x01000706, + /*02bb*/ 0x00000302, + /*02bc*/ 0x01030201, + /*02bd*/ 0x00304c00, + /*02be*/ 0x0001e2f8, + /*02bf*/ 0x0000304c, + /*02c0*/ 0x0001e2f8, + /*02c1*/ 0x0000304c, + /*02c2*/ 0x0001e2f8, + /*02c3*/ 0x08000000, + /*02c4*/ 0x00000100, + /*02c5*/ 0x00000000, + /*02c6*/ 0x00000000, + /*02c7*/ 0x00000000, + /*02c8*/ 0x00000000, + /*02c9*/ 0x00000002 }; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h index 42c33519..996d9144 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,564 +24,564 @@ #define DDR_PI_REGSET_NUM_M3N 286 static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = { -/*0800*/ 0x76543210, -/*0801*/ 0x0004f008, -/*0802*/ 0x00020200, -/*0803*/ 0x00000000, -/*0804*/ 0x00000000, -/*0805*/ 0x00010000, -/*0806*/ 0x036e6e0e, -/*0807*/ 0x026e6e0e, -/*0808*/ 0x00000103, -/*0809*/ 0x00040001, -/*080a*/ 0x00000103, -/*080b*/ 0x00000001, -/*080c*/ 0x00000000, -/*080d*/ 0x00000000, -/*080e*/ 0x00000100, -/*080f*/ 0x001800c0, -/*0810*/ 0x020100b0, -/*0811*/ 0x00030020, -/*0812*/ 0x00000000, -/*0813*/ 0x00000000, -/*0814*/ 0x0000aaaa, -/*0815*/ 0x00005555, -/*0816*/ 0x0000b5b5, -/*0817*/ 0x00004a4a, -/*0818*/ 0x00000000, -/*0819*/ 0x09000000, -/*081a*/ 0x04080000, -/*081b*/ 0x08040000, -/*081c*/ 0x00000004, -/*081d*/ 0x00800710, -/*081e*/ 0x000f000c, -/*081f*/ 0x00000100, -/*0820*/ 0x55aa55aa, -/*0821*/ 0x33cc33cc, -/*0822*/ 0x0ff00ff0, -/*0823*/ 0x0f0ff0f0, -/*0824*/ 0x00018e38, -/*0825*/ 0x00000000, -/*0826*/ 0x00000000, -/*0827*/ 0x00000000, -/*0828*/ 0x00000000, -/*0829*/ 0x00000000, -/*082a*/ 0x00000000, -/*082b*/ 0x00000000, -/*082c*/ 0x00000000, -/*082d*/ 0x00000000, -/*082e*/ 0x00000000, -/*082f*/ 0x00000000, -/*0830*/ 0x00000000, -/*0831*/ 0x00000000, -/*0832*/ 0x00000000, -/*0833*/ 0x00000000, -/*0834*/ 0x00000000, -/*0835*/ 0x00000000, -/*0836*/ 0x00000000, -/*0837*/ 0x00000000, -/*0838*/ 0x00000000, -/*0839*/ 0x00000000, -/*083a*/ 0x00000104, -/*083b*/ 0x00082020, -/*083c*/ 0x08200820, -/*083d*/ 0x08200820, -/*083e*/ 0x08200820, -/*083f*/ 0x08200820, -/*0840*/ 0x08200820, -/*0841*/ 0x00000000, -/*0842*/ 0x00000000, -/*0843*/ 0x03000300, -/*0844*/ 0x03000300, -/*0845*/ 0x03000300, -/*0846*/ 0x03000300, -/*0847*/ 0x00000300, -/*0848*/ 0x00000000, -/*0849*/ 0x00000000, -/*084a*/ 0x00000000, -/*084b*/ 0x00000000, -/*084c*/ 0x00000000, -/*084d*/ 0x00a000a0, -/*084e*/ 0x00a000a0, -/*084f*/ 0x00a000a0, -/*0850*/ 0x00a000a0, -/*0851*/ 0x00a000a0, -/*0852*/ 0x00a000a0, -/*0853*/ 0x00a000a0, -/*0854*/ 0x00a000a0, -/*0855*/ 0x00a000a0, -/*0856*/ 0x01040119, -/*0857*/ 0x00000200, -/*0858*/ 0x01000000, -/*0859*/ 0x00000200, -/*085a*/ 0x00000004, -/*085b*/ 0x4041a141, -/*085c*/ 0x0141c0a0, -/*085d*/ 0x0000c0c0, -/*085e*/ 0x0e0c000e, -/*085f*/ 0x10001000, -/*0860*/ 0x0c073e42, -/*0861*/ 0x000f0c28, -/*0862*/ 0x00e00140, -/*0863*/ 0x000c0020, -/*0864*/ 0x00000203 + /*0800*/ 0x76543210, + /*0801*/ 0x0004f008, + /*0802*/ 0x00020200, + /*0803*/ 0x00000000, + /*0804*/ 0x00000000, + /*0805*/ 0x00010000, + /*0806*/ 0x036e6e0e, + /*0807*/ 0x026e6e0e, + /*0808*/ 0x00000103, + /*0809*/ 0x00040001, + /*080a*/ 0x00000103, + /*080b*/ 0x00000001, + /*080c*/ 0x00000000, + /*080d*/ 0x00000000, + /*080e*/ 0x00000100, + /*080f*/ 0x001800c0, + /*0810*/ 0x020100b0, + /*0811*/ 0x00030020, + /*0812*/ 0x00000000, + /*0813*/ 0x00000000, + /*0814*/ 0x0000aaaa, + /*0815*/ 0x00005555, + /*0816*/ 0x0000b5b5, + /*0817*/ 0x00004a4a, + /*0818*/ 0x00000000, + /*0819*/ 0x09000000, + /*081a*/ 0x04080000, + /*081b*/ 0x08040000, + /*081c*/ 0x00000004, + /*081d*/ 0x00800710, + /*081e*/ 0x000f000c, + /*081f*/ 0x00000100, + /*0820*/ 0x55aa55aa, + /*0821*/ 0x33cc33cc, + /*0822*/ 0x0ff00ff0, + /*0823*/ 0x0f0ff0f0, + /*0824*/ 0x00018e38, + /*0825*/ 0x00000000, + /*0826*/ 0x00000000, + /*0827*/ 0x00000000, + /*0828*/ 0x00000000, + /*0829*/ 0x00000000, + /*082a*/ 0x00000000, + /*082b*/ 0x00000000, + /*082c*/ 0x00000000, + /*082d*/ 0x00000000, + /*082e*/ 0x00000000, + /*082f*/ 0x00000000, + /*0830*/ 0x00000000, + /*0831*/ 0x00000000, + /*0832*/ 0x00000000, + /*0833*/ 0x00000000, + /*0834*/ 0x00000000, + /*0835*/ 0x00000000, + /*0836*/ 0x00000000, + /*0837*/ 0x00000000, + /*0838*/ 0x00000000, + /*0839*/ 0x00000000, + /*083a*/ 0x00000104, + /*083b*/ 0x00082020, + /*083c*/ 0x08200820, + /*083d*/ 0x08200820, + /*083e*/ 0x08200820, + /*083f*/ 0x08200820, + /*0840*/ 0x08200820, + /*0841*/ 0x00000000, + /*0842*/ 0x00000000, + /*0843*/ 0x03000300, + /*0844*/ 0x03000300, + /*0845*/ 0x03000300, + /*0846*/ 0x03000300, + /*0847*/ 0x00000300, + /*0848*/ 0x00000000, + /*0849*/ 0x00000000, + /*084a*/ 0x00000000, + /*084b*/ 0x00000000, + /*084c*/ 0x00000000, + /*084d*/ 0x00a000a0, + /*084e*/ 0x00a000a0, + /*084f*/ 0x00a000a0, + /*0850*/ 0x00a000a0, + /*0851*/ 0x00a000a0, + /*0852*/ 0x00a000a0, + /*0853*/ 0x00a000a0, + /*0854*/ 0x00a000a0, + /*0855*/ 0x00a000a0, + /*0856*/ 0x01040119, + /*0857*/ 0x00000200, + /*0858*/ 0x01000000, + /*0859*/ 0x00000200, + /*085a*/ 0x00000004, + /*085b*/ 0x4041a141, + /*085c*/ 0x0141c0a0, + /*085d*/ 0x0000c0c0, + /*085e*/ 0x0e0c000e, + /*085f*/ 0x10001000, + /*0860*/ 0x0c073e42, + /*0861*/ 0x000f0c28, + /*0862*/ 0x00e00140, + /*0863*/ 0x000c0020, + /*0864*/ 0x00000203 }; static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = { -/*0a00*/ 0x00000000, -/*0a01*/ 0x00000000, -/*0a02*/ 0x00000000, -/*0a03*/ 0x00000000, -/*0a04*/ 0x00000000, -/*0a05*/ 0x00000000, -/*0a06*/ 0x00000000, -/*0a07*/ 0x01000000, -/*0a08*/ 0x00020000, -/*0a09*/ 0x00000000, -/*0a0a*/ 0x00000000, -/*0a0b*/ 0x00000000, -/*0a0c*/ 0x00400000, -/*0a0d*/ 0x00000080, -/*0a0e*/ 0x00dcba98, -/*0a0f*/ 0x03000000, -/*0a10*/ 0x00000200, -/*0a11*/ 0x00000000, -/*0a12*/ 0x00000000, -/*0a13*/ 0x00000000, -/*0a14*/ 0x0000002a, -/*0a15*/ 0x00000015, -/*0a16*/ 0x00000015, -/*0a17*/ 0x0000002a, -/*0a18*/ 0x00000033, -/*0a19*/ 0x0000000c, -/*0a1a*/ 0x0000000c, -/*0a1b*/ 0x00000033, -/*0a1c*/ 0x0a418820, -/*0a1d*/ 0x003f0000, -/*0a1e*/ 0x0000013f, -/*0a1f*/ 0x0002c06e, -/*0a20*/ 0x02c002c0, -/*0a21*/ 0x02c002c0, -/*0a22*/ 0x000002c0, -/*0a23*/ 0x42080010, -/*0a24*/ 0x0000033e + /*0a00*/ 0x00000000, + /*0a01*/ 0x00000000, + /*0a02*/ 0x00000000, + /*0a03*/ 0x00000000, + /*0a04*/ 0x00000000, + /*0a05*/ 0x00000000, + /*0a06*/ 0x00000000, + /*0a07*/ 0x01000000, + /*0a08*/ 0x00020000, + /*0a09*/ 0x00000000, + /*0a0a*/ 0x00000000, + /*0a0b*/ 0x00000000, + /*0a0c*/ 0x00400000, + /*0a0d*/ 0x00000080, + /*0a0e*/ 0x00dcba98, + /*0a0f*/ 0x03000000, + /*0a10*/ 0x00000200, + /*0a11*/ 0x00000000, + /*0a12*/ 0x00000000, + /*0a13*/ 0x00000000, + /*0a14*/ 0x0000002a, + /*0a15*/ 0x00000015, + /*0a16*/ 0x00000015, + /*0a17*/ 0x0000002a, + /*0a18*/ 0x00000033, + /*0a19*/ 0x0000000c, + /*0a1a*/ 0x0000000c, + /*0a1b*/ 0x00000033, + /*0a1c*/ 0x0a418820, + /*0a1d*/ 0x003f0000, + /*0a1e*/ 0x0000013f, + /*0a1f*/ 0x0002c06e, + /*0a20*/ 0x02c002c0, + /*0a21*/ 0x02c002c0, + /*0a22*/ 0x000002c0, + /*0a23*/ 0x42080010, + /*0a24*/ 0x0000033e }; static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = { -/*0a80*/ 0x00000000, -/*0a81*/ 0x00000000, -/*0a82*/ 0x00000000, -/*0a83*/ 0x00000000, -/*0a84*/ 0x00000000, -/*0a85*/ 0x00000000, -/*0a86*/ 0x00000000, -/*0a87*/ 0x01000000, -/*0a88*/ 0x00020000, -/*0a89*/ 0x00000000, -/*0a8a*/ 0x00000000, -/*0a8b*/ 0x00000000, -/*0a8c*/ 0x00400000, -/*0a8d*/ 0x00000080, -/*0a8e*/ 0x00000000, -/*0a8f*/ 0x03000000, -/*0a90*/ 0x00000200, -/*0a91*/ 0x00000000, -/*0a92*/ 0x00000000, -/*0a93*/ 0x00000000, -/*0a94*/ 0x0000002a, -/*0a95*/ 0x00000015, -/*0a96*/ 0x00000015, -/*0a97*/ 0x0000002a, -/*0a98*/ 0x00000033, -/*0a99*/ 0x0000000c, -/*0a9a*/ 0x0000000c, -/*0a9b*/ 0x00000033, -/*0a9c*/ 0x00000000, -/*0a9d*/ 0x00000000, -/*0a9e*/ 0x00000000, -/*0a9f*/ 0x0002c06e, -/*0aa0*/ 0x02c002c0, -/*0aa1*/ 0x02c002c0, -/*0aa2*/ 0x000002c0, -/*0aa3*/ 0x42080010, -/*0aa4*/ 0x0000033e + /*0a80*/ 0x00000000, + /*0a81*/ 0x00000000, + /*0a82*/ 0x00000000, + /*0a83*/ 0x00000000, + /*0a84*/ 0x00000000, + /*0a85*/ 0x00000000, + /*0a86*/ 0x00000000, + /*0a87*/ 0x01000000, + /*0a88*/ 0x00020000, + /*0a89*/ 0x00000000, + /*0a8a*/ 0x00000000, + /*0a8b*/ 0x00000000, + /*0a8c*/ 0x00400000, + /*0a8d*/ 0x00000080, + /*0a8e*/ 0x00000000, + /*0a8f*/ 0x03000000, + /*0a90*/ 0x00000200, + /*0a91*/ 0x00000000, + /*0a92*/ 0x00000000, + /*0a93*/ 0x00000000, + /*0a94*/ 0x0000002a, + /*0a95*/ 0x00000015, + /*0a96*/ 0x00000015, + /*0a97*/ 0x0000002a, + /*0a98*/ 0x00000033, + /*0a99*/ 0x0000000c, + /*0a9a*/ 0x0000000c, + /*0a9b*/ 0x00000033, + /*0a9c*/ 0x00000000, + /*0a9d*/ 0x00000000, + /*0a9e*/ 0x00000000, + /*0a9f*/ 0x0002c06e, + /*0aa0*/ 0x02c002c0, + /*0aa1*/ 0x02c002c0, + /*0aa2*/ 0x000002c0, + /*0aa3*/ 0x42080010, + /*0aa4*/ 0x0000033e }; static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = { -/*0b80*/ 0x00000000, -/*0b81*/ 0x00000100, -/*0b82*/ 0x00000000, -/*0b83*/ 0x00050000, -/*0b84*/ 0x00000000, -/*0b85*/ 0x0004000f, -/*0b86*/ 0x00280080, -/*0b87*/ 0x02005502, -/*0b88*/ 0x00000000, -/*0b89*/ 0x00000000, -/*0b8a*/ 0x00000000, -/*0b8b*/ 0x00000050, -/*0b8c*/ 0x00000000, -/*0b8d*/ 0x01010100, -/*0b8e*/ 0x00010000, -/*0b8f*/ 0x00000000, -/*0b90*/ 0x00000101, -/*0b91*/ 0x00000000, -/*0b92*/ 0x00000000, -/*0b93*/ 0x00000000, -/*0b94*/ 0x00000000, -/*0b95*/ 0x00005064, -/*0b96*/ 0x01421142, -/*0b97*/ 0x00000142, -/*0b98*/ 0x00000000, -/*0b99*/ 0x000f1600, -/*0b9a*/ 0x0f160f16, -/*0b9b*/ 0x0f160f16, -/*0b9c*/ 0x00000003, -/*0b9d*/ 0x0002c000, -/*0b9e*/ 0x02c002c0, -/*0b9f*/ 0x000002c0, -/*0ba0*/ 0x08040201, -/*0ba1*/ 0x03421342, -/*0ba2*/ 0x00000342, -/*0ba3*/ 0x00000000, -/*0ba4*/ 0x00000000, -/*0ba5*/ 0x05030000, -/*0ba6*/ 0x00010700, -/*0ba7*/ 0x00000014, -/*0ba8*/ 0x00027f6e, -/*0ba9*/ 0x047f027f, -/*0baa*/ 0x00027f6e, -/*0bab*/ 0x00047f6e, -/*0bac*/ 0x0003554f, -/*0bad*/ 0x0001554f, -/*0bae*/ 0x0001554f, -/*0baf*/ 0x0001554f, -/*0bb0*/ 0x0001554f, -/*0bb1*/ 0x00003fee, -/*0bb2*/ 0x0001554f, -/*0bb3*/ 0x00003fee, -/*0bb4*/ 0x0001554f, -/*0bb5*/ 0x00027f6e, -/*0bb6*/ 0x0001554f, -/*0bb7*/ 0x00004011, -/*0bb8*/ 0x00004410, -/*0bb9*/ 0x00000000, -/*0bba*/ 0x00000000, -/*0bbb*/ 0x00000000, -/*0bbc*/ 0x00000265, -/*0bbd*/ 0x00000000, -/*0bbe*/ 0x00040401, -/*0bbf*/ 0x00000000, -/*0bc0*/ 0x03000000, -/*0bc1*/ 0x00000020, -/*0bc2*/ 0x00000000, -/*0bc3*/ 0x00000000, -/*0bc4*/ 0x04102006, -/*0bc5*/ 0x00041020, -/*0bc6*/ 0x01c98c98, -/*0bc7*/ 0x00400000, -/*0bc8*/ 0x00000000, -/*0bc9*/ 0x0001ffff, -/*0bca*/ 0x00000000, -/*0bcb*/ 0x00000000, -/*0bcc*/ 0x00000001, -/*0bcd*/ 0x00000000, -/*0bce*/ 0x00000000, -/*0bcf*/ 0x00000000, -/*0bd0*/ 0x76543210, -/*0bd1*/ 0x06010198, -/*0bd2*/ 0x00000000, -/*0bd3*/ 0x00000000, -/*0bd4*/ 0x04070000, -/*0bd5*/ 0x00000001, -/*0bd6*/ 0x00000f00 + /*0b80*/ 0x00000000, + /*0b81*/ 0x00000100, + /*0b82*/ 0x00000000, + /*0b83*/ 0x00050000, + /*0b84*/ 0x00000000, + /*0b85*/ 0x0004000f, + /*0b86*/ 0x00280080, + /*0b87*/ 0x02005502, + /*0b88*/ 0x00000000, + /*0b89*/ 0x00000000, + /*0b8a*/ 0x00000000, + /*0b8b*/ 0x00000050, + /*0b8c*/ 0x00000000, + /*0b8d*/ 0x01010100, + /*0b8e*/ 0x00010000, + /*0b8f*/ 0x00000000, + /*0b90*/ 0x00000101, + /*0b91*/ 0x00000000, + /*0b92*/ 0x00000000, + /*0b93*/ 0x00000000, + /*0b94*/ 0x00000000, + /*0b95*/ 0x00005064, + /*0b96*/ 0x01421142, + /*0b97*/ 0x00000142, + /*0b98*/ 0x00000000, + /*0b99*/ 0x000f1600, + /*0b9a*/ 0x0f160f16, + /*0b9b*/ 0x0f160f16, + /*0b9c*/ 0x00000003, + /*0b9d*/ 0x0002c000, + /*0b9e*/ 0x02c002c0, + /*0b9f*/ 0x000002c0, + /*0ba0*/ 0x08040201, + /*0ba1*/ 0x03421342, + /*0ba2*/ 0x00000342, + /*0ba3*/ 0x00000000, + /*0ba4*/ 0x00000000, + /*0ba5*/ 0x05030000, + /*0ba6*/ 0x00010700, + /*0ba7*/ 0x00000014, + /*0ba8*/ 0x00027f6e, + /*0ba9*/ 0x047f027f, + /*0baa*/ 0x00027f6e, + /*0bab*/ 0x00047f6e, + /*0bac*/ 0x0003554f, + /*0bad*/ 0x0001554f, + /*0bae*/ 0x0001554f, + /*0baf*/ 0x0001554f, + /*0bb0*/ 0x0001554f, + /*0bb1*/ 0x00003fee, + /*0bb2*/ 0x0001554f, + /*0bb3*/ 0x00003fee, + /*0bb4*/ 0x0001554f, + /*0bb5*/ 0x00027f6e, + /*0bb6*/ 0x0001554f, + /*0bb7*/ 0x00004011, + /*0bb8*/ 0x00004410, + /*0bb9*/ 0x00000000, + /*0bba*/ 0x00000000, + /*0bbb*/ 0x00000000, + /*0bbc*/ 0x00000265, + /*0bbd*/ 0x00000000, + /*0bbe*/ 0x00040401, + /*0bbf*/ 0x00000000, + /*0bc0*/ 0x03000000, + /*0bc1*/ 0x00000020, + /*0bc2*/ 0x00000000, + /*0bc3*/ 0x00000000, + /*0bc4*/ 0x04102006, + /*0bc5*/ 0x00041020, + /*0bc6*/ 0x01c98c98, + /*0bc7*/ 0x00400000, + /*0bc8*/ 0x00000000, + /*0bc9*/ 0x0001ffff, + /*0bca*/ 0x00000000, + /*0bcb*/ 0x00000000, + /*0bcc*/ 0x00000001, + /*0bcd*/ 0x00000000, + /*0bce*/ 0x00000000, + /*0bcf*/ 0x00000000, + /*0bd0*/ 0x76543210, + /*0bd1*/ 0x06010198, + /*0bd2*/ 0x00000000, + /*0bd3*/ 0x00000000, + /*0bd4*/ 0x04070000, + /*0bd5*/ 0x00000001, + /*0bd6*/ 0x00000f00 }; static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000101, -/*0202*/ 0x01640000, -/*0203*/ 0x00000014, -/*0204*/ 0x00000014, -/*0205*/ 0x00000014, -/*0206*/ 0x00000014, -/*0207*/ 0x00000000, -/*0208*/ 0x00000000, -/*0209*/ 0x0000ffff, -/*020a*/ 0x00000000, -/*020b*/ 0x0000ffff, -/*020c*/ 0x00000000, -/*020d*/ 0x0000ffff, -/*020e*/ 0x0000304c, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x00000200, -/*0212*/ 0x00000200, -/*0213*/ 0x0000304c, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00000200, -/*0217*/ 0x00000200, -/*0218*/ 0x0000304c, -/*0219*/ 0x00000200, -/*021a*/ 0x00000200, -/*021b*/ 0x00000200, -/*021c*/ 0x00000200, -/*021d*/ 0x00010000, -/*021e*/ 0x00000003, -/*021f*/ 0x01000001, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x00000000, -/*022a*/ 0x00000000, -/*022b*/ 0x00000000, -/*022c*/ 0x00000000, -/*022d*/ 0x00000000, -/*022e*/ 0x00000000, -/*022f*/ 0x00000000, -/*0230*/ 0x0f000101, -/*0231*/ 0x084d3129, -/*0232*/ 0x0e0c0004, -/*0233*/ 0x000e5000, -/*0234*/ 0x01000250, -/*0235*/ 0x00000003, -/*0236*/ 0x00000046, -/*0237*/ 0x000000cf, -/*0238*/ 0x00001826, -/*0239*/ 0x000000cf, -/*023a*/ 0x00001826, -/*023b*/ 0x00000000, -/*023c*/ 0x00000000, -/*023d*/ 0x00000000, -/*023e*/ 0x00000000, -/*023f*/ 0x00000000, -/*0240*/ 0x00000000, -/*0241*/ 0x00000000, -/*0242*/ 0x00000000, -/*0243*/ 0x00000000, -/*0244*/ 0x00000000, -/*0245*/ 0x01000000, -/*0246*/ 0x00040404, -/*0247*/ 0x01280a00, -/*0248*/ 0x00000001, -/*0249*/ 0x00000000, -/*024a*/ 0x03000f00, -/*024b*/ 0x00200020, -/*024c*/ 0x00000020, -/*024d*/ 0x00000000, -/*024e*/ 0x00000000, -/*024f*/ 0x00010002, -/*0250*/ 0x01010001, -/*0251*/ 0x02010100, -/*0252*/ 0x08040402, -/*0253*/ 0x00000008, -/*0254*/ 0x00000000, -/*0255*/ 0x04080803, -/*0256*/ 0x00001515, -/*0257*/ 0x00000000, -/*0258*/ 0x000000aa, -/*0259*/ 0x00000055, -/*025a*/ 0x000000b5, -/*025b*/ 0x0000004a, -/*025c*/ 0x00000056, -/*025d*/ 0x000000a9, -/*025e*/ 0x000000a9, -/*025f*/ 0x000000b5, -/*0260*/ 0x00000000, -/*0261*/ 0x00000000, -/*0262*/ 0x0f000000, -/*0263*/ 0x00001e0f, -/*0264*/ 0x000007d0, -/*0265*/ 0x01000300, -/*0266*/ 0x00000100, -/*0267*/ 0x00000000, -/*0268*/ 0x00000000, -/*0269*/ 0x01000000, -/*026a*/ 0x00010101, -/*026b*/ 0x000e0e0e, -/*026c*/ 0x000c0c0c, -/*026d*/ 0x01060601, -/*026e*/ 0x04041717, -/*026f*/ 0x00000004, -/*0270*/ 0x00000300, -/*0271*/ 0x17030000, -/*0272*/ 0x00060018, -/*0273*/ 0x00160028, -/*0274*/ 0x00160028, -/*0275*/ 0x00000000, -/*0276*/ 0x00000000, -/*0277*/ 0x00000000, -/*0278*/ 0x0a000000, -/*0279*/ 0x00010a14, -/*027a*/ 0x00030005, -/*027b*/ 0x0003018d, -/*027c*/ 0x000a018d, -/*027d*/ 0x00060100, -/*027e*/ 0x01000006, -/*027f*/ 0x018e018e, -/*0280*/ 0x018e0100, -/*0281*/ 0x1e1a018e, -/*0282*/ 0x1e1a1e1a, -/*0283*/ 0x01010204, -/*0284*/ 0x06501001, -/*0285*/ 0x090d0a07, -/*0286*/ 0x090d0a07, -/*0287*/ 0x0811180f, -/*0288*/ 0x00ff1102, -/*0289*/ 0x00ff1000, -/*028a*/ 0x00ff1000, -/*028b*/ 0x04041000, -/*028c*/ 0x18020100, -/*028d*/ 0x01010018, -/*028e*/ 0x005f005f, -/*028f*/ 0x005f005f, -/*0290*/ 0x050f0000, -/*0291*/ 0x051e051e, -/*0292*/ 0x0c01021e, -/*0293*/ 0x00000c0c, -/*0294*/ 0x00003400, -/*0295*/ 0x00000000, -/*0296*/ 0x00000000, -/*0297*/ 0x00000000, -/*0298*/ 0x00000000, -/*0299*/ 0x002e00d4, -/*029a*/ 0x11360031, -/*029b*/ 0x00d41611, -/*029c*/ 0x0031002e, -/*029d*/ 0x16111136, -/*029e*/ 0x002e00d4, -/*029f*/ 0x11360031, -/*02a0*/ 0x00001611, -/*02a1*/ 0x002e00d4, -/*02a2*/ 0x11360031, -/*02a3*/ 0x00d41611, -/*02a4*/ 0x0031002e, -/*02a5*/ 0x16111136, -/*02a6*/ 0x002e00d4, -/*02a7*/ 0x11360031, -/*02a8*/ 0x00001611, -/*02a9*/ 0x002e00d4, -/*02aa*/ 0x11360031, -/*02ab*/ 0x00d41611, -/*02ac*/ 0x0031002e, -/*02ad*/ 0x16111136, -/*02ae*/ 0x002e00d4, -/*02af*/ 0x11360031, -/*02b0*/ 0x00001611, -/*02b1*/ 0x002e00d4, -/*02b2*/ 0x11360031, -/*02b3*/ 0x00d41611, -/*02b4*/ 0x0031002e, -/*02b5*/ 0x16111136, -/*02b6*/ 0x002e00d4, -/*02b7*/ 0x11360031, -/*02b8*/ 0x00001611, -/*02b9*/ 0x00018d00, -/*02ba*/ 0x018d018d, -/*02bb*/ 0x1d220c08, -/*02bc*/ 0x00001f12, -/*02bd*/ 0x4301b344, -/*02be*/ 0x17032006, -/*02bf*/ 0x220c1010, -/*02c0*/ 0x001f121d, -/*02c1*/ 0x4301b344, -/*02c2*/ 0x17062006, -/*02c3*/ 0x220c1010, -/*02c4*/ 0x001f121d, -/*02c5*/ 0x4301b344, -/*02c6*/ 0x17182006, -/*02c7*/ 0x00021010, -/*02c8*/ 0x00020002, -/*02c9*/ 0x00020002, -/*02ca*/ 0x00020002, -/*02cb*/ 0x00020002, -/*02cc*/ 0x00000002, -/*02cd*/ 0x00000000, -/*02ce*/ 0x00000000, -/*02cf*/ 0x00000000, -/*02d0*/ 0x00000000, -/*02d1*/ 0x00000000, -/*02d2*/ 0x00000000, -/*02d3*/ 0x00000000, -/*02d4*/ 0x00000000, -/*02d5*/ 0x00000000, -/*02d6*/ 0x00000000, -/*02d7*/ 0x00000000, -/*02d8*/ 0x00000000, -/*02d9*/ 0x00000400, -/*02da*/ 0x15141312, -/*02db*/ 0x11100f0e, -/*02dc*/ 0x080b0c0d, -/*02dd*/ 0x05040a09, -/*02de*/ 0x01000706, -/*02df*/ 0x00000302, -/*02e0*/ 0x01030201, -/*02e1*/ 0x00304c08, -/*02e2*/ 0x0001e2f8, -/*02e3*/ 0x0000304c, -/*02e4*/ 0x0001e2f8, -/*02e5*/ 0x0000304c, -/*02e6*/ 0x0001e2f8, -/*02e7*/ 0x08000000, -/*02e8*/ 0x00000100, -/*02e9*/ 0x00000000, -/*02ea*/ 0x00000000, -/*02eb*/ 0x00000000, -/*02ec*/ 0x00000000, -/*02ed*/ 0x00010000, -/*02ee*/ 0x00000000, -/*02ef*/ 0x00000000, -/*02f0*/ 0x00000000, -/*02f1*/ 0x00000000, -/*02f2*/ 0x00000000, -/*02f3*/ 0x00000000, -/*02f4*/ 0x00000000, -/*02f5*/ 0x00000000, -/*02f6*/ 0x00000000, -/*02f7*/ 0x00000000, -/*02f8*/ 0x00000000, -/*02f9*/ 0x00000000, -/*02fa*/ 0x00000000, -/*02fb*/ 0x00000000, -/*02fc*/ 0x00000000, -/*02fd*/ 0x00000000, -/*02fe*/ 0x00000000, -/*02ff*/ 0x00000000, -/*0300*/ 0x00000000, -/*0301*/ 0x00000000, -/*0302*/ 0x00000000, -/*0303*/ 0x00000000, -/*0304*/ 0x00000000, -/*0305*/ 0x00000000, -/*0306*/ 0x00000000, -/*0307*/ 0x00000000, -/*0308*/ 0x00000000, -/*0309*/ 0x00000000, -/*030a*/ 0x00000000, -/*030b*/ 0x00000000, -/*030c*/ 0x00000000, -/*030d*/ 0x00000000, -/*030e*/ 0x00000000, -/*030f*/ 0x00050002, -/*0310*/ 0x015c0057, -/*0311*/ 0x01000100, -/*0312*/ 0x01020001, -/*0313*/ 0x00010300, -/*0314*/ 0x05000104, -/*0315*/ 0x01060001, -/*0316*/ 0x00010700, -/*0317*/ 0x00000000, -/*0318*/ 0x00000000, -/*0319*/ 0x00000001, -/*031a*/ 0x00000000, -/*031b*/ 0x00000000, -/*031c*/ 0x00000000, -/*031d*/ 0x20080101 + /*0200*/ 0x00000b00, + /*0201*/ 0x00000101, + /*0202*/ 0x01640000, + /*0203*/ 0x00000014, + /*0204*/ 0x00000014, + /*0205*/ 0x00000014, + /*0206*/ 0x00000014, + /*0207*/ 0x00000000, + /*0208*/ 0x00000000, + /*0209*/ 0x0000ffff, + /*020a*/ 0x00000000, + /*020b*/ 0x0000ffff, + /*020c*/ 0x00000000, + /*020d*/ 0x0000ffff, + /*020e*/ 0x0000304c, + /*020f*/ 0x00000200, + /*0210*/ 0x00000200, + /*0211*/ 0x00000200, + /*0212*/ 0x00000200, + /*0213*/ 0x0000304c, + /*0214*/ 0x00000200, + /*0215*/ 0x00000200, + /*0216*/ 0x00000200, + /*0217*/ 0x00000200, + /*0218*/ 0x0000304c, + /*0219*/ 0x00000200, + /*021a*/ 0x00000200, + /*021b*/ 0x00000200, + /*021c*/ 0x00000200, + /*021d*/ 0x00010000, + /*021e*/ 0x00000003, + /*021f*/ 0x01000001, + /*0220*/ 0x00000000, + /*0221*/ 0x00000000, + /*0222*/ 0x00000000, + /*0223*/ 0x00000000, + /*0224*/ 0x00000000, + /*0225*/ 0x00000000, + /*0226*/ 0x00000000, + /*0227*/ 0x00000000, + /*0228*/ 0x00000000, + /*0229*/ 0x00000000, + /*022a*/ 0x00000000, + /*022b*/ 0x00000000, + /*022c*/ 0x00000000, + /*022d*/ 0x00000000, + /*022e*/ 0x00000000, + /*022f*/ 0x00000000, + /*0230*/ 0x0f000101, + /*0231*/ 0x084d3129, + /*0232*/ 0x0e0c0004, + /*0233*/ 0x000e5000, + /*0234*/ 0x01000250, + /*0235*/ 0x00000003, + /*0236*/ 0x00000046, + /*0237*/ 0x000000cf, + /*0238*/ 0x00001826, + /*0239*/ 0x000000cf, + /*023a*/ 0x00001826, + /*023b*/ 0x00000000, + /*023c*/ 0x00000000, + /*023d*/ 0x00000000, + /*023e*/ 0x00000000, + /*023f*/ 0x00000000, + /*0240*/ 0x00000000, + /*0241*/ 0x00000000, + /*0242*/ 0x00000000, + /*0243*/ 0x00000000, + /*0244*/ 0x00000000, + /*0245*/ 0x01000000, + /*0246*/ 0x00040404, + /*0247*/ 0x01280a00, + /*0248*/ 0x00000001, + /*0249*/ 0x00000000, + /*024a*/ 0x03000f00, + /*024b*/ 0x00200020, + /*024c*/ 0x00000020, + /*024d*/ 0x00000000, + /*024e*/ 0x00000000, + /*024f*/ 0x00010002, + /*0250*/ 0x01010001, + /*0251*/ 0x02010100, + /*0252*/ 0x08040402, + /*0253*/ 0x00000008, + /*0254*/ 0x00000000, + /*0255*/ 0x04080803, + /*0256*/ 0x00001515, + /*0257*/ 0x00000000, + /*0258*/ 0x000000aa, + /*0259*/ 0x00000055, + /*025a*/ 0x000000b5, + /*025b*/ 0x0000004a, + /*025c*/ 0x00000056, + /*025d*/ 0x000000a9, + /*025e*/ 0x000000a9, + /*025f*/ 0x000000b5, + /*0260*/ 0x00000000, + /*0261*/ 0x00000000, + /*0262*/ 0x0f000000, + /*0263*/ 0x00001e0f, + /*0264*/ 0x000007d0, + /*0265*/ 0x01000300, + /*0266*/ 0x00000100, + /*0267*/ 0x00000000, + /*0268*/ 0x00000000, + /*0269*/ 0x01000000, + /*026a*/ 0x00010101, + /*026b*/ 0x000e0e0e, + /*026c*/ 0x000c0c0c, + /*026d*/ 0x01060601, + /*026e*/ 0x04041717, + /*026f*/ 0x00000004, + /*0270*/ 0x00000300, + /*0271*/ 0x17030000, + /*0272*/ 0x00060018, + /*0273*/ 0x00160028, + /*0274*/ 0x00160028, + /*0275*/ 0x00000000, + /*0276*/ 0x00000000, + /*0277*/ 0x00000000, + /*0278*/ 0x0a000000, + /*0279*/ 0x00010a14, + /*027a*/ 0x00030005, + /*027b*/ 0x0003018d, + /*027c*/ 0x000a018d, + /*027d*/ 0x00060100, + /*027e*/ 0x01000006, + /*027f*/ 0x018e018e, + /*0280*/ 0x018e0100, + /*0281*/ 0x1e1a018e, + /*0282*/ 0x1e1a1e1a, + /*0283*/ 0x01010204, + /*0284*/ 0x06501001, + /*0285*/ 0x090d0a07, + /*0286*/ 0x090d0a07, + /*0287*/ 0x0811180f, + /*0288*/ 0x00ff1102, + /*0289*/ 0x00ff1000, + /*028a*/ 0x00ff1000, + /*028b*/ 0x04041000, + /*028c*/ 0x18020100, + /*028d*/ 0x01010018, + /*028e*/ 0x005f005f, + /*028f*/ 0x005f005f, + /*0290*/ 0x050f0000, + /*0291*/ 0x051e051e, + /*0292*/ 0x0c01021e, + /*0293*/ 0x00000c0c, + /*0294*/ 0x00003400, + /*0295*/ 0x00000000, + /*0296*/ 0x00000000, + /*0297*/ 0x00000000, + /*0298*/ 0x00000000, + /*0299*/ 0x002e00d4, + /*029a*/ 0x11360031, + /*029b*/ 0x00d41611, + /*029c*/ 0x0031002e, + /*029d*/ 0x16111136, + /*029e*/ 0x002e00d4, + /*029f*/ 0x11360031, + /*02a0*/ 0x00001611, + /*02a1*/ 0x002e00d4, + /*02a2*/ 0x11360031, + /*02a3*/ 0x00d41611, + /*02a4*/ 0x0031002e, + /*02a5*/ 0x16111136, + /*02a6*/ 0x002e00d4, + /*02a7*/ 0x11360031, + /*02a8*/ 0x00001611, + /*02a9*/ 0x002e00d4, + /*02aa*/ 0x11360031, + /*02ab*/ 0x00d41611, + /*02ac*/ 0x0031002e, + /*02ad*/ 0x16111136, + /*02ae*/ 0x002e00d4, + /*02af*/ 0x11360031, + /*02b0*/ 0x00001611, + /*02b1*/ 0x002e00d4, + /*02b2*/ 0x11360031, + /*02b3*/ 0x00d41611, + /*02b4*/ 0x0031002e, + /*02b5*/ 0x16111136, + /*02b6*/ 0x002e00d4, + /*02b7*/ 0x11360031, + /*02b8*/ 0x00001611, + /*02b9*/ 0x00018d00, + /*02ba*/ 0x018d018d, + /*02bb*/ 0x1d220c08, + /*02bc*/ 0x00001f12, + /*02bd*/ 0x4301b344, + /*02be*/ 0x17032006, + /*02bf*/ 0x220c1010, + /*02c0*/ 0x001f121d, + /*02c1*/ 0x4301b344, + /*02c2*/ 0x17062006, + /*02c3*/ 0x220c1010, + /*02c4*/ 0x001f121d, + /*02c5*/ 0x4301b344, + /*02c6*/ 0x17182006, + /*02c7*/ 0x00021010, + /*02c8*/ 0x00020002, + /*02c9*/ 0x00020002, + /*02ca*/ 0x00020002, + /*02cb*/ 0x00020002, + /*02cc*/ 0x00000002, + /*02cd*/ 0x00000000, + /*02ce*/ 0x00000000, + /*02cf*/ 0x00000000, + /*02d0*/ 0x00000000, + /*02d1*/ 0x00000000, + /*02d2*/ 0x00000000, + /*02d3*/ 0x00000000, + /*02d4*/ 0x00000000, + /*02d5*/ 0x00000000, + /*02d6*/ 0x00000000, + /*02d7*/ 0x00000000, + /*02d8*/ 0x00000000, + /*02d9*/ 0x00000400, + /*02da*/ 0x15141312, + /*02db*/ 0x11100f0e, + /*02dc*/ 0x080b0c0d, + /*02dd*/ 0x05040a09, + /*02de*/ 0x01000706, + /*02df*/ 0x00000302, + /*02e0*/ 0x01030201, + /*02e1*/ 0x00304c08, + /*02e2*/ 0x0001e2f8, + /*02e3*/ 0x0000304c, + /*02e4*/ 0x0001e2f8, + /*02e5*/ 0x0000304c, + /*02e6*/ 0x0001e2f8, + /*02e7*/ 0x08000000, + /*02e8*/ 0x00000100, + /*02e9*/ 0x00000000, + /*02ea*/ 0x00000000, + /*02eb*/ 0x00000000, + /*02ec*/ 0x00000000, + /*02ed*/ 0x00010000, + /*02ee*/ 0x00000000, + /*02ef*/ 0x00000000, + /*02f0*/ 0x00000000, + /*02f1*/ 0x00000000, + /*02f2*/ 0x00000000, + /*02f3*/ 0x00000000, + /*02f4*/ 0x00000000, + /*02f5*/ 0x00000000, + /*02f6*/ 0x00000000, + /*02f7*/ 0x00000000, + /*02f8*/ 0x00000000, + /*02f9*/ 0x00000000, + /*02fa*/ 0x00000000, + /*02fb*/ 0x00000000, + /*02fc*/ 0x00000000, + /*02fd*/ 0x00000000, + /*02fe*/ 0x00000000, + /*02ff*/ 0x00000000, + /*0300*/ 0x00000000, + /*0301*/ 0x00000000, + /*0302*/ 0x00000000, + /*0303*/ 0x00000000, + /*0304*/ 0x00000000, + /*0305*/ 0x00000000, + /*0306*/ 0x00000000, + /*0307*/ 0x00000000, + /*0308*/ 0x00000000, + /*0309*/ 0x00000000, + /*030a*/ 0x00000000, + /*030b*/ 0x00000000, + /*030c*/ 0x00000000, + /*030d*/ 0x00000000, + /*030e*/ 0x00000000, + /*030f*/ 0x00050002, + /*0310*/ 0x015c0057, + /*0311*/ 0x01000100, + /*0312*/ 0x01020001, + /*0313*/ 0x00010300, + /*0314*/ 0x05000104, + /*0315*/ 0x01060001, + /*0316*/ 0x00010700, + /*0317*/ 0x00000000, + /*0318*/ 0x00000000, + /*0319*/ 0x00000001, + /*031a*/ 0x00000000, + /*031b*/ 0x00000000, + /*031c*/ 0x00000000, + /*031d*/ 0x20080101 }; -- cgit v1.2.3 From bf881832e81e1057153a8de4b0ab707cce3536cd Mon Sep 17 00:00:00 2001 From: Yoshifumi Hosoya Date: Mon, 1 Jul 2019 19:45:41 +0900 Subject: rcar_gen3: drivers: qos: update QoS setting [IPL/QoS] - Update M3 Ver.3.0 QoS setting rev.0.04. Signed-off-by: Yoshifumi Hosoya Signed-off-by: Marek Vasut Change-Id: I798401f417df6a352d94311ea07a1e96ba562f6a --- drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c | 2 +- drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h | 6 +++--- drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c index e300fd54..43d21d71 100644 --- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c +++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c @@ -12,7 +12,7 @@ #include "../qos_reg.h" #include "qos_init_m3_v30.h" -#define RCAR_QOS_VERSION "rev.0.03" +#define RCAR_QOS_VERSION "rev.0.04" #define QOSWT_TIME_BANK0 20000000U /* unit:ns */ diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h index cd820e85..2ab14dad 100644 --- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h +++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat195.h @@ -32,8 +32,8 @@ static uint64_t mstat_fix[] = { /* 0x00c0, */ 0x000C04020000FFFFUL, /* 0x00c8, */ 0x000C04010000FFFFUL, /* 0x00d0, */ 0x000C04010000FFFFUL, - /* 0x00d8, */ 0x000C100D0000FFFFUL, - /* 0x00e0, */ 0x000C1C1B0000FFFFUL, + /* 0x00d8, */ 0x000C08050000FFFFUL, + /* 0x00e0, */ 0x000C10100000FFFFUL, /* 0x00e8, */ 0x0000000000000000UL, /* 0x00f0, */ 0x001024090000FFFFUL, /* 0x00f8, */ 0x0000000000000000UL, @@ -41,7 +41,7 @@ static uint64_t mstat_fix[] = { /* 0x0108, */ 0x0000000000000000UL, /* 0x0110, */ 0x00100C090000FFFFUL, /* 0x0118, */ 0x0000000000000000UL, - /* 0x0120, */ 0x000C1C1B0000FFFFUL, + /* 0x0120, */ 0x000C10100000FFFFUL, /* 0x0128, */ 0x0000000000000000UL, /* 0x0130, */ 0x0000000000000000UL, /* 0x0138, */ 0x00100C0B0000FFFFUL, diff --git a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h index e9037e1f..faac3d9f 100644 --- a/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h +++ b/drivers/renesas/rcar/qos/M3/qos_init_m3_v30_mstat390.h @@ -32,8 +32,8 @@ static uint64_t mstat_fix[] = { /* 0x00c0, */ 0x000C08040000FFFFUL, /* 0x00c8, */ 0x000C04020000FFFFUL, /* 0x00d0, */ 0x000C04020000FFFFUL, - /* 0x00d8, */ 0x000C1C1A0000FFFFUL, - /* 0x00e0, */ 0x000C38360000FFFFUL, + /* 0x00d8, */ 0x000C0C0A0000FFFFUL, + /* 0x00e0, */ 0x000C201F0000FFFFUL, /* 0x00e8, */ 0x0000000000000000UL, /* 0x00f0, */ 0x001044110000FFFFUL, /* 0x00f8, */ 0x0000000000000000UL, @@ -41,7 +41,7 @@ static uint64_t mstat_fix[] = { /* 0x0108, */ 0x0000000000000000UL, /* 0x0110, */ 0x001014110000FFFFUL, /* 0x0118, */ 0x0000000000000000UL, - /* 0x0120, */ 0x000C38360000FFFFUL, + /* 0x0120, */ 0x000C201F0000FFFFUL, /* 0x0128, */ 0x0000000000000000UL, /* 0x0130, */ 0x0000000000000000UL, /* 0x0138, */ 0x001018150000FFFFUL, -- cgit v1.2.3 From fbee88fbb039c2d2a5f5c78fac74a1942146de95 Mon Sep 17 00:00:00 2001 From: Chiaki Fujii Date: Mon, 8 Jul 2019 23:44:56 +0900 Subject: rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N [IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.37. Signed-off-by: Chiaki Fujii Signed-off-by: Marek Vasut Change-Id: I072c0f61cd896e74e4e1eee39d313f82cf2f7295 --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 39 ++++++++++++---------- .../renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h | 2 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h | 2 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h | 2 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h | 2 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h | 2 +- 6 files changed, 27 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index 9c7f9c8a..9f7c9549 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -90,7 +90,7 @@ static const struct _boardcnf *board_cnf; static uint32_t ddr_phyvalid; static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; static uint32_t ch_have_this_cs[CS_CNT] __aligned(64); -static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; +static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9]; static uint32_t max_density; static uint32_t ddr0800_mul; static uint32_t ddr_mul; @@ -358,15 +358,13 @@ static void pll3_control(uint32_t high) if (high) { tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr_mul) / 2; - data_mul = (((ddr_mul * tmp_div) - 1) << 24) | - (brd_clkdiva << 7); + data_mul = ((ddr_mul * tmp_div) - 1) << 24; pll3_mode = 1; loop_max = 2; } else { tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr0800_mul) / 2; - data_mul = (((ddr0800_mul * tmp_div) - 1) << 24) | - (brd_clkdiva << 7); + data_mul = ((ddr0800_mul * tmp_div) - 1) << 24; pll3_mode = 0; loop_max = 8; } @@ -2711,8 +2709,8 @@ static void ddr_register_set(void) uint32_t tmp; for (fspwp = 1; fspwp >= 0; fspwp--) { - /*MR13,fspwp */ - send_dbcmd(0x0e840d08 | (fspwp << 6)); + /*MR13, fspwp */ + send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6)); tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, @@ -2745,7 +2743,16 @@ static void ddr_register_set(void) send_dbcmd(0x0e840e00 | tmp); /* MR22 */ send_dbcmd(0x0e841616); + + /* ZQCAL start */ + send_dbcmd(0x0d84004F); + + /* ZQLAT */ + send_dbcmd(0x0d840051); } + + /* MR13, fspwp */ + send_dbcmd(0x0e840d08); } /* Training handshake functions */ @@ -3038,12 +3045,6 @@ static uint32_t init_ddr(void) /* MRS */ ddr_register_set(); - /* ZQCAL start */ - send_dbcmd(0x0d84004F); - - /* ZQLAT */ - send_dbcmd(0x0d840051); - /* Thermal sensor setting */ /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */ data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; @@ -3478,17 +3479,21 @@ static uint32_t wdqdm_man(void) const uint32_t retry_max = 0x10; uint32_t ch, ddr_csn, mr14_bkup[4][4]; - ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12); + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, + (mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19); if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) || (prr_product == PRR_PRODUCT_M3N) || (prr_product == PRR_PRODUCT_V3H)) { + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0, + (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, - (DBSC_DBTR(12) & 0xFF) + 1); + (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); } else { ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR, - (DBSC_DBTR(12) & 0xFF) + 1); + (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); } - ddr_setval_ach(_reg_PI_TRFC_F1, (DBSC_DBTR(13) & 0x1FF)); + ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); + ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF); retry_cnt = 0; err = 0; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h index 8eb3859a..5047e5cc 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#define RCAR_DDR_VERSION "rev.0.36" +#define RCAR_DDR_VERSION "rev.0.37" #define DRAM_CH_CNT 0x04 #define SLICE_CNT 0x04 #define CS_CNT 0x02 diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h index 69db2a73..357f8bad 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h @@ -104,7 +104,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = { /*044d*/ 0x00000200, /*044e*/ 0x01000000, /*044f*/ 0x00000200, - /*0450*/ 0x4041a141, + /*0450*/ 0x4041a151, /*0451*/ 0xc00141a0, /*0452*/ 0x0e0100c0, /*0453*/ 0x0010000c, diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h index b94f308f..e5258af6 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h @@ -114,7 +114,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2 /*0456*/ 0x01000000, /*0457*/ 0x00000200, /*0458*/ 0x00000004, - /*0459*/ 0x4041a141, + /*0459*/ 0x4041a151, /*045a*/ 0xc00141a0, /*045b*/ 0x0e0000c0, /*045c*/ 0x0010000c, diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h index a09b0041..b491f0e9 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h @@ -105,7 +105,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = { /*084e*/ 0x00000000, /*084f*/ 0x00010000, /*0850*/ 0x00000200, - /*0851*/ 0x4041a141, + /*0851*/ 0x4041a151, /*0852*/ 0xc00141a0, /*0853*/ 0x0e0100c0, /*0854*/ 0x0010000c, diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h index 996d9144..8d80842f 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h @@ -115,7 +115,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = { /*0858*/ 0x01000000, /*0859*/ 0x00000200, /*085a*/ 0x00000004, - /*085b*/ 0x4041a141, + /*085b*/ 0x4041a151, /*085c*/ 0x0141c0a0, /*085d*/ 0x0000c0c0, /*085e*/ 0x0e0c000e, -- cgit v1.2.3