From 80942622fe760c23f0a677eac48aff37e90f4251 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Tue, 20 Aug 2019 15:51:24 -0500 Subject: Neoverse N1 Errata Workaround 1542419 Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6 --- docs/design/cpu-specific-build-macros.rst | 3 +++ 1 file changed, 3 insertions(+) (limited to 'docs') diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index d3fe89d6..a392eea2 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -258,6 +258,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. + DSU Errata Workarounds ---------------------- -- cgit v1.2.3