From e34606f2e400c192bac3abeb9b2053b2c91ccd7c Mon Sep 17 00:00:00 2001 From: lauwal01 Date: Mon, 24 Jun 2019 11:28:34 -0500 Subject: Workaround for Neoverse N1 erratum 1130799 Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister --- docs/design/cpu-specific-build-macros.rst | 3 +++ 1 file changed, 3 insertions(+) (limited to 'docs/design') diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 55109dc7..01ee4162 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -231,6 +231,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. +- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. -- cgit v1.2.3