From c3e8b0be9bde36d220beea5d0452ecd04dcd94c6 Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Tue, 20 Aug 2019 15:22:44 +0100 Subject: AArch32: Disable Secure Cycle Counter This patch changes implementation for disabling Secure Cycle Counter. For ARMv8.5 the counter gets disabled by setting SDCR.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR.DP bit. In 'include\aarch32\arch.h' header file new ARMv8.5-PMU related definitions were added. Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8 Signed-off-by: Alexei Fedorov --- bl32/sp_min/aarch32/entrypoint.S | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) (limited to 'bl32') diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index 2ffef6a2..0a684754 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -183,15 +183,6 @@ func sp_min_handle_smc stcopr r0, SCR isb - /* - * Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode. - * Also, the PMCR.LC field has an architecturally UNKNOWN value on reset - * and so set to 1 as ARM has deprecated use of PMCR.LC=0. - */ - ldcopr r0, PMCR - orr r0, r0, #(PMCR_LC_BIT | PMCR_DP_BIT) - stcopr r0, PMCR - ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */ /* Check whether an SMC64 is issued */ tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT) @@ -236,15 +227,6 @@ func sp_min_handle_fiq stcopr r0, SCR isb - /* - * Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode. - * Also, the PMCR.LC field has an architecturally UNKNOWN value on reset - * and so set to 1 as ARM has deprecated use of PMCR.LC=0. - */ - ldcopr r0, PMCR - orr r0, r0, #(PMCR_LC_BIT | PMCR_DP_BIT) - stcopr r0, PMCR - push {r2, r3} bl sp_min_fiq pop {r0, r3} -- cgit v1.2.3