From 8cd16e6b5b4a83a2cf704362b9acb1c2eea1417e Mon Sep 17 00:00:00 2001 From: Soby Mathew Date: Tue, 17 May 2016 14:01:32 +0100 Subject: Build option to include AArch32 registers in cpu context The system registers that are saved and restored in CPU context include AArch32 systems registers like SPSR_ABT, SPSR_UND, SPSR_IRQ, SPSR_FIQ, DACR32_EL2, IFSR32_EL2 and FPEXC32_EL2. Accessing these registers on an AArch64-only (i.e. on hardware that does not implement AArch32, or at least not at EL1 and higher ELs) platform leads to an exception. This patch introduces the build option `CTX_INCLUDE_AARCH32_REGS` to specify whether to include these AArch32 systems registers in the cpu context or not. By default this build option is set to 1 to ensure compatibility. AArch64-only platforms must set it to 0. A runtime check is added in BL1 and BL31 cold boot path to verify this. Fixes ARM-software/tf-issues#386 Change-Id: I720cdbd7ed7f7d8516635a2ec80d025f478b95ee --- bl31/bl31_main.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'bl31') diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c index 835d41e8..7f04d218 100644 --- a/bl31/bl31_main.c +++ b/bl31/bl31_main.c @@ -145,6 +145,19 @@ void bl31_prepare_next_image_entry(void) entry_point_info_t *next_image_info; uint32_t image_type; +#if CTX_INCLUDE_AARCH32_REGS + /* + * Ensure that the build flag to save AArch32 system registers in CPU + * context is not set for AArch64-only platforms. + */ + if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT) + & ID_AA64PFR0_ELX_MASK) == 0x1) { + ERROR("EL1 supports AArch64-only. Please set build flag " + "CTX_INCLUDE_AARCH32_REGS = 0"); + panic(); + } +#endif + /* Determine which image to execute next */ image_type = bl31_get_next_image_type(); -- cgit v1.2.3