From e28150e16c774ea63d6df76e8c2e20c7360dbf61 Mon Sep 17 00:00:00 2001
From: Nitin Garg <nitin.garg@nxp.com>
Date: Wed, 7 Jun 2017 15:47:04 -0500
Subject: Enable CPU, FP, L2 retention counters to 64 cycles

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
---
 include/lib/cpus/aarch64/cortex_a35.h | 33 +++++++++++++++++++++++++++++++++
 plat/imx/common/imx8_helpers.S        | 27 +++++++++++++++++++++++++++
 plat/imx/imx8qm/platform.mk           |  5 +++++
 plat/imx/imx8qx/platform.mk           |  5 +++++
 4 files changed, 70 insertions(+)

diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h
index 5421478d..abef0428 100644
--- a/include/lib/cpus/aarch64/cortex_a35.h
+++ b/include/lib/cpus/aarch64/cortex_a35.h
@@ -12,6 +12,15 @@
 /* Cortex-A35 Main ID register for revision 0 */
 #define CORTEX_A35_MIDR				U(0x410FD040)
 
+/* Retention timer tick definitions */
+#define RETENTION_ENTRY_TICKS_2		0x1
+#define RETENTION_ENTRY_TICKS_8		0x2
+#define RETENTION_ENTRY_TICKS_32	0x3
+#define RETENTION_ENTRY_TICKS_64	0x4
+#define RETENTION_ENTRY_TICKS_128	0x5
+#define RETENTION_ENTRY_TICKS_256	0x6
+#define RETENTION_ENTRY_TICKS_512	0x7
+
 /*******************************************************************************
  * CPU Extended Control register specific definitions.
  * CPUECTLR_EL1 is an implementation-specific register.
@@ -26,4 +35,28 @@
 
 #define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI	(ULL(1) << 44)
 
+#define CPUECTLR_CPU_RET_CTRL_SHIFT		0
+#define CPUECTLR_CPU_RET_CTRL_MASK		(0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
+
+#define CPUECTLR_FPU_RET_CTRL_SHIFT		3
+#define CPUECTLR_FPU_RET_CTRL_MASK		(0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT)
+
+/*******************************************************************************
+ * CPU Memory Error Syndrome register specific definitions.
+ ******************************************************************************/
+#define CPUMERRSR_EL1			S3_1_C15_C2_2	/* Instruction def. */
+
+/*******************************************************************************
+ * L2 Extended Control register specific definitions.
+ ******************************************************************************/
+#define L2ECTLR_EL1			S3_1_C11_C0_3	/* Instruction def. */
+
+#define L2ECTLR_RET_CTRL_SHIFT		0
+#define L2ECTLR_RET_CTRL_MASK		(0x7 << L2ECTLR_RET_CTRL_SHIFT)
+
+/*******************************************************************************
+ * L2 Memory Error Syndrome register specific definitions.
+ ******************************************************************************/
+#define L2MERRSR_EL1			S3_1_C15_C2_3	/* Instruction def. */
+
 #endif /* CORTEX_A35_H */
diff --git a/plat/imx/common/imx8_helpers.S b/plat/imx/common/imx8_helpers.S
index b9603a46..15934757 100644
--- a/plat/imx/common/imx8_helpers.S
+++ b/plat/imx/common/imx8_helpers.S
@@ -92,6 +92,33 @@ endfunc plat_calc_core_pos
 	 * ----------------------------------------------
 	 */
 func plat_reset_handler
+#if ENABLE_L2_DYNAMIC_RETENTION
+	/* ---------------------------
+	 * Enable processor retention
+	 * ---------------------------
+	*/
+	mrs	x0, L2ECTLR_EL1
+	mov	x1, #RETENTION_ENTRY_TICKS_64 << L2ECTLR_RET_CTRL_SHIFT
+	bic	x0, x0, #L2ECTLR_RET_CTRL_MASK
+	orr	x0, x0, x1
+	msr	L2ECTLR_EL1, x0
+	isb
+#endif
+
+#if ENABLE_CPU_DYNAMIC_RETENTION
+	mrs	x1, CORTEX_A72_ECTLR_EL1
+	mov	x2, #RETENTION_ENTRY_TICKS_64 << CPUECTLR_CPU_RET_CTRL_SHIFT
+	bic	x1, x1, #CPUECTLR_CPU_RET_CTRL_MASK
+	orr	x1, x1, x2
+	jump_if_cpu_midr CORTEX_A72_MIDR, SKIP_FP
+	mov	x2, #RETENTION_ENTRY_TICKS_64 << CPUECTLR_FPU_RET_CTRL_SHIFT
+	bic	x1, x1, #CPUECTLR_FPU_RET_CTRL_MASK
+	orr	x1, x1, x2
+SKIP_FP:
+	msr	CORTEX_A72_ECTLR_EL1, x1
+	isb
+#endif
+
 	/* enable EL2 cpuectlr RW access */
 	mov	x0, #0x73
 	msr	actlr_el3, x0
diff --git a/plat/imx/imx8qm/platform.mk b/plat/imx/imx8qm/platform.mk
index 3a772e51..5cadf518 100644
--- a/plat/imx/imx8qm/platform.mk
+++ b/plat/imx/imx8qm/platform.mk
@@ -41,3 +41,8 @@ ERRATA_A72_859971	:=	1
 ERRATA_A53_835769	:=	1
 ERRATA_A53_843419	:=	1
 ERRATA_A53_855873	:=	1
+
+ENABLE_CPU_DYNAMIC_RETENTION := 1
+$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION))
+ENABLE_L2_DYNAMIC_RETENTION := 1
+$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION))
diff --git a/plat/imx/imx8qx/platform.mk b/plat/imx/imx8qx/platform.mk
index d5629d12..c21b6f64 100644
--- a/plat/imx/imx8qx/platform.mk
+++ b/plat/imx/imx8qx/platform.mk
@@ -33,3 +33,8 @@ include plat/imx/common/sci/sci_api.mk
 
 USE_COHERENT_MEM	:=	1
 RESET_TO_BL31		:=	1
+
+ENABLE_CPU_DYNAMIC_RETENTION := 1
+$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION))
+ENABLE_L2_DYNAMIC_RETENTION := 1
+$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION))
-- 
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