From 96f4d3768c8b35d2d8cbcce75617790f3bb037f6 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Mon, 28 Aug 2017 14:22:15 +0800 Subject: fix sw pup/pdn issue on imx8mq The bits[3:0] of CPU_PGC_PUP/PDN_TRG use core's SW power up/down. prevous bits assignment is wrong, so fix it. Signed-off-by: Bai Ping --- plat/freescale/imx8mq/gpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/freescale/imx8mq/gpc.c b/plat/freescale/imx8mq/gpc.c index b3ddd770..c1836d93 100644 --- a/plat/freescale/imx8mq/gpc.c +++ b/plat/freescale/imx8mq/gpc.c @@ -270,7 +270,7 @@ void imx_gpc_set_core_pdn_pup_by_software(unsigned int cpu, bool pdn) /*Set the core PCR bit before sw PUP/PDN trigger */ imx_gpc_set_m_core_pgc(GPC_ARM_PGC + cpu * 0x40, true); - index = cpu < 2 ? cpu : cpu + 1; + index = cpu; val |= (BM_CPU_PGC_SW_PDN_PUP_REQ << index); mmio_write_32(IMX_GPC_BASE + (pdn ? GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ), val); -- cgit v1.2.3