From 5f103fc89151f8fbdafd5cce8d2a2c9b59e27715 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 2 Feb 2021 20:06:40 -0800 Subject: MLK-25293 iMX8MQ: Add version for B2 iMX8MQ B2 chip uses same OCOTP magic value with B1. So read the ROM version to distinguish it with B1. Signed-off-by: Ye Li Reviewed-by: Jacky Bai (cherry picked from commit dcfce7731ed19c6235f9b1ad3a68fbfe33b69f9a) --- plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c index f4c45895..7b320f0e 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c @@ -94,7 +94,10 @@ static void imx8mq_soc_info_init(void) ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1); if (ocotp_val == 0xff0055aa) { imx_soc_revision &= ~0xff; - imx_soc_revision |= 0x21; + if (rom_version == 0x22) + imx_soc_revision |= 0x22; + else + imx_soc_revision |= 0x21; return; } } -- cgit v1.2.3 From ed66400156db65fca3f69aae2536282555b63798 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 9 Mar 2021 14:51:28 +0800 Subject: MLK-25321 plat: imx8m: Add 4000mts frequency config on imx8m Add the PLL frequency config for 4000mts. Signed-off-by: Jacky Bai Reviewed-by: Ye Li (cherry picked from commit 3409e57d59ee897e519d87d20ada926638f6be4d) --- plat/imx/imx8m/ddr/clock.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/imx/imx8m/ddr/clock.c b/plat/imx/imx8m/ddr/clock.c index 7ddc25cc..7eb989f9 100644 --- a/plat/imx/imx8m/ddr/clock.c +++ b/plat/imx/imx8m/ddr/clock.c @@ -84,6 +84,9 @@ void dram_pll_init(unsigned int drate) mmio_clrbits_32(DRAM_PLL_CTRL, (1 << 9)); switch (drate) { + case 4000: + mmio_write_32(DRAM_PLL_CTRL + 0x4, (250 << 12) | (3 << 4) | 1); + break; case 3200: mmio_write_32(DRAM_PLL_CTRL + 0x4, (200 << 12) | (3 << 4) | 1); break; -- cgit v1.2.3 From 768e16f784bd7462d7df684e24deb0b777bdfc28 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 16 Mar 2021 16:42:54 +0800 Subject: MLK-25345 plat: imx8m: Add ddr4 dvfs sw workaround for ERR050712 APB Write data corruption following MRCTRL0.mr_wr=1 while hardware-driven MR access is occurring When performing a software driven MR access, the following sequence must be done automatically before performing other APB register accesses: 1. Set MRCTRL0.mr_wr=1 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2) 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2) Signed-off-by: Jacky Bai Reviewed-by: Ye Li (cherry picked from commit 1eb7ad6c5ea2c47952ab5e083df9802e27c165f5) --- plat/imx/imx8m/ddr/ddr4_dvfs.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/plat/imx/imx8m/ddr/ddr4_dvfs.c b/plat/imx/imx8m/ddr/ddr4_dvfs.c index 52dd2066..d1c0d750 100644 --- a/plat/imx/imx8m/ddr/ddr4_dvfs.c +++ b/plat/imx/imx8m/ddr/ddr4_dvfs.c @@ -18,8 +18,22 @@ void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, * 1. Poll MRSTAT.mr_wr_busy until it is 0 to make sure * that there is no outstanding MR transAction. */ - while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) - ; + + /* + * ERR050712: + * When performing a software driven MR access, the following sequence + * must be done automatically before performing other APB register accesses. + * 1. Set MRCTRL0.mr_wr=1 + * 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2) + * 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2) + */ + mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); + + do { + while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) + ; + + } while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1); /* * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank -- cgit v1.2.3 From 2a26786460edd4f0ec3111e7027c93c57fc572c1 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 22 Mar 2021 14:26:05 +0800 Subject: MLK-25358 plat: imx8m: Correct the csu sa & hpctrl setting Correct the csu sa & hpctrl setting. Signed-off-by: Jacky Bai Reviewed-by: Ye Li (cherry picked from commit 9e09b4970ebce21d7a085afffbadf8851a7fd647) --- plat/imx/imx8m/imx8m_csu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/plat/imx/imx8m/imx8m_csu.c b/plat/imx/imx8m/imx8m_csu.c index 3405fa59..b1f6886e 100644 --- a/plat/imx/imx8m/imx8m_csu.c +++ b/plat/imx/imx8m/imx8m_csu.c @@ -34,14 +34,14 @@ void imx_csu_init(const struct imx_csu_cfg *csu_cfg) if (val & CSU_SA_LOCK(csu->idx)) break; mmio_clrsetbits_32(CSU_SA_REG(csu->idx), CSU_SA_CFG(0x1, csu->idx), - CSU_SA_CFG(csu->hp | (csu->lock << 0x1), csu->idx)); + CSU_SA_CFG(csu->sa | (csu->lock << 0x1), csu->idx)); break; case CSU_HPCONTROL: val = mmio_read_32(CSU_HPCONTROL_REG(csu->idx)); if (val & CSU_HPCONTROL_LOCK(csu->idx)) break; mmio_clrsetbits_32(CSU_HPCONTROL_REG(csu->idx), CSU_HPCONTROL_CFG(0x1, csu->idx), - CSU_HPCONTROL_CFG(csu->hp | (csu->lock << 0x1), csu->idx)); + CSU_HPCONTROL_CFG(csu->hpctrl | (csu->lock << 0x1), csu->idx)); break; default: break; -- cgit v1.2.3