From 7b62aea017c0366b5132dedfe9711cd094cd5cc3 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Fri, 31 Aug 2018 15:47:39 +0800 Subject: plat: imx8mq: update the ddr controller perf QoS setting update the ddr controller perf QoS setting on i.MX8MQ. Signed-off-by: Bai Ping --- plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c b/plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c index dba387b0..a09f12a3 100644 --- a/plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c +++ b/plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c @@ -38,8 +38,8 @@ static inline void umctl2_perf(void) mmio_write_32(DDRC_SCHED(0), 0x29511505); mmio_write_32(DDRC_SCHED1(0), 0x0000002c); mmio_write_32(DDRC_PERFHPR1(0), 0x5900575b); - mmio_write_32(DDRC_PERFLPR1(0), 0x00000009); - mmio_write_32(DDRC_PERFWR1(0), 0x02005574); + mmio_write_32(DDRC_PERFLPR1(0), 0x90000096); + mmio_write_32(DDRC_PERFWR1(0), 0x1000012c); mmio_write_32(DDRC_DBG0(0), 0x00000016); mmio_write_32(DDRC_DBG1(0), 0x00000000); mmio_write_32(DDRC_DBGCMD(0), 0x00000000); @@ -49,10 +49,10 @@ static inline void umctl2_perf(void) mmio_write_32(DDRC_PCFGR_0(0), 0x000010f3); mmio_write_32(DDRC_PCFGW_0(0), 0x000072ff); mmio_write_32(DDRC_PCTRL_0(0), 0x00000001); - mmio_write_32(DDRC_PCFGQOS0_0(0), 0x01110d00); - mmio_write_32(DDRC_PCFGQOS1_0(0), 0x00620790); - mmio_write_32(DDRC_PCFGWQOS0_0(0), 0x00100001); - mmio_write_32(DDRC_PCFGWQOS1_0(0), 0x0000041f); + mmio_write_32(DDRC_PCFGQOS0_0(0), 0x00000e00); + mmio_write_32(DDRC_PCFGQOS1_0(0), 0x0062ffff); + mmio_write_32(DDRC_PCFGWQOS0_0(0), 0x00000e00); + mmio_write_32(DDRC_PCFGWQOS1_0(0), 0x0000ffff); mmio_write_32(DDRC_FREQ1_DERATEEN(0), 0x00000202); mmio_write_32(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5); mmio_write_32(DDRC_FREQ1_RFSHCTL0(0), 0x00618040); -- cgit v1.2.3