From 2f45f6e5ef517fe5f201bcd5046368b854442749 Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Wed, 7 Jun 2017 15:47:04 -0500 Subject: Enable CPU, FP, L2 retention counters to 64 cycles Signed-off-by: Nitin Garg --- include/lib/cpus/aarch64/cortex_a35.h | 33 +++++++++++++++++++++++++++++++++ plat/freescale/common/imx8_helpers.S | 28 ++++++++++++++++++++++++++++ plat/freescale/imx8qm/platform.mk | 4 ++++ plat/freescale/imx8qxp/platform.mk | 4 ++++ 4 files changed, 69 insertions(+) diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h index ad0fedc7..c9370244 100644 --- a/include/lib/cpus/aarch64/cortex_a35.h +++ b/include/lib/cpus/aarch64/cortex_a35.h @@ -10,6 +10,15 @@ /* Cortex-A35 Main ID register for revision 0 */ #define CORTEX_A35_MIDR 0x410FD040 +/* Retention timer tick definitions */ +#define RETENTION_ENTRY_TICKS_2 0x1 +#define RETENTION_ENTRY_TICKS_8 0x2 +#define RETENTION_ENTRY_TICKS_32 0x3 +#define RETENTION_ENTRY_TICKS_64 0x4 +#define RETENTION_ENTRY_TICKS_128 0x5 +#define RETENTION_ENTRY_TICKS_256 0x6 +#define RETENTION_ENTRY_TICKS_512 0x7 + /******************************************************************************* * CPU Extended Control register specific definitions. * CPUECTLR_EL1 is an implementation-specific register. @@ -17,4 +26,28 @@ #define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1 #define CORTEX_A35_CPUECTLR_SMPEN_BIT (1 << 6) +#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 +#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) + +#define CPUECTLR_FPU_RET_CTRL_SHIFT 3 +#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) + +/******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* + * L2 Extended Control register specific definitions. + ******************************************************************************/ +#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */ + +#define L2ECTLR_RET_CTRL_SHIFT 0 +#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + #endif /* __CORTEX_A35_H__ */ diff --git a/plat/freescale/common/imx8_helpers.S b/plat/freescale/common/imx8_helpers.S index f2da325d..ecc2481e 100644 --- a/plat/freescale/common/imx8_helpers.S +++ b/plat/freescale/common/imx8_helpers.S @@ -31,6 +31,7 @@ #include #include #include +#include .globl plat_is_my_cpu_primary .globl plat_my_core_pos @@ -112,6 +113,33 @@ endfunc plat_calc_core_pos * ---------------------------------------------- */ func plat_reset_handler +#if ENABLE_L2_DYNAMIC_RETENTION + /* --------------------------- + * Enable processor retention + * --------------------------- + */ + mrs x0, L2ECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_64 << L2ECTLR_RET_CTRL_SHIFT + bic x0, x0, #L2ECTLR_RET_CTRL_MASK + orr x0, x0, x1 + msr L2ECTLR_EL1, x0 + isb +#endif + +#if ENABLE_CPU_DYNAMIC_RETENTION + mrs x1, CORTEX_A72_ECTLR_EL1 + mov x2, #RETENTION_ENTRY_TICKS_64 << CPUECTLR_CPU_RET_CTRL_SHIFT + bic x1, x1, #CPUECTLR_CPU_RET_CTRL_MASK + orr x1, x1, x2 + jump_if_cpu_midr CORTEX_A72_MIDR, SKIP_FP + mov x2, #RETENTION_ENTRY_TICKS_64 << CPUECTLR_FPU_RET_CTRL_SHIFT + bic x1, x1, #CPUECTLR_FPU_RET_CTRL_MASK + orr x1, x1, x2 +SKIP_FP: + msr CORTEX_A72_ECTLR_EL1, x1 + isb +#endif + /* enable EL2 cpuectlr RW access */ mov x0, #0x73 msr actlr_el3, x0 diff --git a/plat/freescale/imx8qm/platform.mk b/plat/freescale/imx8qm/platform.mk index b3137932..c516c8df 100644 --- a/plat/freescale/imx8qm/platform.mk +++ b/plat/freescale/imx8qm/platform.mk @@ -58,3 +58,7 @@ USE_COHERENT_MEM := 0 RESET_TO_BL31 := 1 ERROR_DEPRECATED := 1 A53_DISABLE_NON_TEMPORAL_HINT := 0 +ENABLE_CPU_DYNAMIC_RETENTION := 1 +$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION)) +ENABLE_L2_DYNAMIC_RETENTION := 1 +$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION)) diff --git a/plat/freescale/imx8qxp/platform.mk b/plat/freescale/imx8qxp/platform.mk index 24a55236..50b695ef 100644 --- a/plat/freescale/imx8qxp/platform.mk +++ b/plat/freescale/imx8qxp/platform.mk @@ -57,3 +57,7 @@ RESET_TO_BL31 := 1 ERROR_DEPRECATED := 1 ARM_GIC_ARCH := 3 A53_DISABLE_NON_TEMPORAL_HINT := 0 +ENABLE_CPU_DYNAMIC_RETENTION := 1 +$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION)) +ENABLE_L2_DYNAMIC_RETENTION := 1 +$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION)) -- cgit v1.2.3