From 2b93f4a8a277daf8f354790cde3728b62a0c1931 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 18 Aug 2020 09:41:15 +0800 Subject: MLK-24513 plat: imx8mp: disable the memrepair clock when do domain power down The memrepair clock also need to be disable before domain power down, so fix it to make sure the memrepair logic can work as expected. Signed-off-by: Jacky Bai Reviewed-by: Anson Huang Reviewed-by: Jian Li Tested-by: Jian Li --- plat/imx/imx8m/imx8mp/gpc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c index d281685e..ed1f6c11 100644 --- a/plat/imx/imx8m/imx8mp/gpc.c +++ b/plat/imx/imx8m/imx8mp/gpc.c @@ -473,6 +473,9 @@ void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) return; + /* disable the memory repair clock before power down */ + mmio_write_32(IMX_CCM_BASE + 0x4640, 0x0); + if (domain_id == VPUMIX) mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ | VPU_G2_PWR_REQ | VPU_H1_PWR_REQ); @@ -483,6 +486,9 @@ void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) /* wait for power request done */ while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req); + /* enable the memory repair clock after power down */ + mmio_write_32(IMX_CCM_BASE + 0x4640, 0x3); + if (domain_id == HDMIMIX) { /* disable all the clocks of HDMIMIX */ mmio_write_32(0x32fc0040, 0x0); -- cgit v1.2.3