From 282f524de7f60a722910669a62bfd49eb4ec239c Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 11 Oct 2018 16:26:50 +0800 Subject: imx8qxp: add support for cpuidle This patch adds support for cpuidle with CPU powerdown, there will be 3 idle states in Linux kernel: 1: wfi; 2: cpu power down; 3: cluster power down. As Linux kernel needs a broadcast timer for waking up CPU when whole CLUSTER is powerdown, GPT is adopted as broadcast timer, and to make the clock & power management easy for Linux kernel to avoid many workaround/hake in Linux kernel, TF-A will handle GPT's power & clock management as well as registers save/restore when suspend/resume. Also, psci power states are used to determine CORE/CLUSTER/SYSTEM power state to distinguish CPU idle and SYSTEM suspend which share same domain_suspend callback. The SoC IPs register mmap regions are merged into 1 large section to cover all the SoC IPs register ranges TF-A needs, this is to save mmap regions and make it simple. Signed-off-by: Anson Huang --- plat/imx/imx8qxp/imx8qxp_bl31_setup.c | 18 ++-- plat/imx/imx8qxp/imx8qxp_psci.c | 174 ++++++++++++++++++++------------ plat/imx/imx8qxp/include/platform_def.h | 4 + plat/imx/imx8qxp/include/sec_rsrc.h | 2 + plat/imx/imx8qxp/platform.mk | 1 + 5 files changed, 124 insertions(+), 75 deletions(-) diff --git a/plat/imx/imx8qxp/imx8qxp_bl31_setup.c b/plat/imx/imx8qxp/imx8qxp_bl31_setup.c index 470f6254..edc2ea46 100644 --- a/plat/imx/imx8qxp/imx8qxp_bl31_setup.c +++ b/plat/imx/imx8qxp/imx8qxp_bl31_setup.c @@ -372,6 +372,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, */ sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON); + /* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON); + sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0); + mmio_write_32(IMX_GPT0_LPCG_BASE, mmio_read_32(IMX_GPT0_LPCG_BASE) | (1 << 25)); + /* create new partition for non-secure OS/Hypervisor * * uses global structs defined in sec_rsrc.h @@ -407,18 +412,9 @@ void bl31_plat_arch_setup(void) MT_MEMORY | MT_RW); mmap_add_region(BL31_BASE, BL31_BASE, BL31_RO_LIMIT - BL31_RO_BASE, MT_MEMORY | MT_RO); - mmap_add_region(IMX_BOOT_UART_BASE, IMX_BOOT_UART_BASE, - 0x1000, MT_DEVICE | MT_RW); - mmap_add_region(SC_IPC_CH, SC_IPC_CH, 0x10000, - MT_DEVICE | MT_RW); - mmap_add_region(PLAT_GICD_BASE, PLAT_GICD_BASE, 0x10000, - MT_DEVICE | MT_RW); - mmap_add_region(PLAT_GICR_BASE, PLAT_GICR_BASE, 0xc0000, - MT_DEVICE | MT_RW); -// mmap_add_region(IMX_GPT0_BASE, IMX_GPT0_BASE, 0x10000, -// MT_DEVICE | MT_RW); - mmap_add_region(IMX_WUP_IRQSTR, IMX_WUP_IRQSTR, 0x10000, + mmap_add_region(IMX_REG_BASE, IMX_REG_BASE, IMX_REG_SIZE, MT_DEVICE | MT_RW); + #ifdef SPD_trusty mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); #endif diff --git a/plat/imx/imx8qxp/imx8qxp_psci.c b/plat/imx/imx8qxp/imx8qxp_psci.c index 267ea225..1445ad2c 100644 --- a/plat/imx/imx8qxp/imx8qxp_psci.c +++ b/plat/imx/imx8qxp/imx8qxp_psci.c @@ -15,12 +15,17 @@ #include #include "../../common/sci/mx8_mu.h" +#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) +#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) +#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) + extern sc_ipc_t ipc_handle; extern void mdelay(uint32_t msec); extern bool wakeup_src_irqsteer; /* save gic dist/redist context when GIC is power down */ static struct plat_gic_ctx imx_gicv3_ctx; +static unsigned int gpt_lpcg, gpt_reg[2]; const unsigned char imx_power_domain_tree_desc[] = { @@ -71,33 +76,20 @@ static void imx_disable_irqstr_wakeup(void) sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_OFF); } -plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, - const plat_local_state_t *target_state, - unsigned int ncpu) -{ - /* TODO */ - return 0; -} - int imx_pwr_domain_on(u_register_t mpidr) { int ret = PSCI_E_SUCCESS; - unsigned int cluster_id, cpu_id; - - cluster_id = MPIDR_AFFLVL1_VAL(mpidr); - cpu_id = MPIDR_AFFLVL0_VAL(mpidr); - - tf_printf("imx_pwr_domain_on cluster_id %d, cpu_id %d\n", cluster_id, cpu_id); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], SC_PM_PW_MODE_ON) != SC_ERR_NONE) { - ERROR("cluster0 core %d power on failed!\n", cpu_id); + ERROR("core %d power on failed!\n", cpu_id); ret = PSCI_E_INTERN_FAIL; } if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id], true, 0x80000000) != SC_ERR_NONE) { - ERROR("boot cluster0 core %d failed!\n", cpu_id); + ERROR("boot core %d failed!\n", cpu_id); ret = PSCI_E_INTERN_FAIL; } @@ -106,28 +98,20 @@ int imx_pwr_domain_on(u_register_t mpidr) void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) { - uint64_t mpidr = read_mpidr_el1(); - unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); - unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); - /* program the GIC per cpu dist and rdist interface */ plat_gic_pcpu_init(); /* enable the GICv3 cpu interface */ plat_gic_cpuif_enable(); - - tf_printf("cluster:%d core:%d is on\n", cluster_id, cpu_id); } void imx_pwr_domain_off(const psci_power_state_t *target_state) { u_register_t mpidr = read_mpidr_el1(); - unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); plat_gic_cpuif_disable(); sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_NONE); - tf_printf("turn off cluster:%d core:%d\n", cluster_id, cpu_id); } void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) @@ -149,21 +133,21 @@ int imx_validate_power_state(unsigned int power_state, psci_power_state_t *req_state) { int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int pwr_type = psci_get_pstate_type(power_state); + int state_id = psci_get_pstate_id(power_state); if (pwr_lvl > PLAT_MAX_PWR_LVL) return PSCI_E_INVALID_PARAMS; - /* Sanity check the requested afflvl */ - if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { - if (pwr_lvl != MPIDR_AFFLVL0) - return PSCI_E_INVALID_PARAMS; - /* power domain in standby state */ - req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE; - - return PSCI_E_SUCCESS; + if (pwr_type == PSTATE_TYPE_POWERDOWN) { + CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; + if (!state_id) + CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; + else + CLUSTER_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; } - return 0; + return PSCI_E_SUCCESS; } void imx_cpu_standby(plat_local_state_t cpu_state) @@ -184,23 +168,52 @@ void imx_domain_suspend(const psci_power_state_t *target_state) u_register_t mpidr = read_mpidr_el1(); unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); - plat_gic_cpuif_disable(); - - /* save gic context */ - plat_gic_save(cpu_id, &imx_gicv3_ctx); - /* enable the irqsteer for wakeup */ - imx_enable_irqstr_wakeup(); - - /* Put GIC in OFF mode. */ - sc_pm_set_resource_power_mode(ipc_handle, SC_R_GIC, SC_PM_PW_MODE_OFF); - sc_pm_set_cpu_resume(ipc_handle, ap_core_index[cpu_id], true, 0x080000000); - if (wakeup_src_irqsteer) - sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], - SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_IRQSTEER); - else + if (is_local_state_off(CORE_PWR_STATE(target_state))) { + plat_gic_cpuif_disable(); + sc_pm_set_cpu_resume(ipc_handle, ap_core_index[cpu_id], true, 0x80000000); sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], - SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_SCU); + SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC); + } else { + dsb(); + write_scr_el3(read_scr_el3() | 0x4); + isb(); + } + if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) + sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_OFF); + + if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { + plat_gic_cpuif_disable(); + + /* save gic context */ + plat_gic_save(cpu_id, &imx_gicv3_ctx); + /* enable the irqsteer for wakeup */ + imx_enable_irqstr_wakeup(); + + /* Save GPT clock and registers, then turn off its power */ + gpt_lpcg = mmio_read_32(IMX_GPT0_LPCG_BASE); + gpt_reg[0] = mmio_read_32(IMX_GPT0_BASE); + gpt_reg[1] = mmio_read_32(IMX_GPT0_BASE + 0x4); + sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_OFF); + + sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_OFF); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_DDR, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_MU, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); + + /* Put GIC in OFF mode. */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_GIC, SC_PM_PW_MODE_OFF); + sc_pm_set_cpu_resume(ipc_handle, ap_core_index[cpu_id], true, 0x080000000); + if (wakeup_src_irqsteer) + sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], + SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_IRQSTEER); + else + sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], + SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_SCU); + } } void imx_domain_suspend_finish(const psci_power_state_t *target_state) @@ -208,20 +221,51 @@ void imx_domain_suspend_finish(const psci_power_state_t *target_state) u_register_t mpidr = read_mpidr_el1(); unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); - MU_Resume(SC_IPC_CH); + if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { + MU_Resume(SC_IPC_CH); - sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id], SC_PM_PW_MODE_ON); - sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], SC_PM_PW_MODE_ON, SC_PM_WAKE_SRC_GIC); + sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id], SC_PM_PW_MODE_ON); + sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], + SC_PM_PW_MODE_ON, SC_PM_WAKE_SRC_GIC); - /* Put GIC back to high power mode. */ - sc_pm_set_resource_power_mode(ipc_handle, SC_R_GIC, SC_PM_PW_MODE_ON); + /* Put GIC back to high power mode. */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_GIC, SC_PM_PW_MODE_ON); - /* restore gic context */ - plat_gic_restore(cpu_id, &imx_gicv3_ctx); - /* disable the irqsteer wakeup */ - imx_disable_irqstr_wakeup(); + /* restore gic context */ + plat_gic_restore(cpu_id, &imx_gicv3_ctx); - plat_gic_cpuif_enable(); + /* Turn on GPT power and restore its clock and registers */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON); + sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0); + mmio_write_32(IMX_GPT0_BASE, gpt_reg[0]); + mmio_write_32(IMX_GPT0_BASE + 0x4, gpt_reg[1]); + mmio_write_32(IMX_GPT0_LPCG_BASE, gpt_lpcg); + + sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_DDR, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_MU, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + + /* disable the irqsteer wakeup */ + imx_disable_irqstr_wakeup(); + + plat_gic_cpuif_enable(); + } + + if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) + sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_ON); + + if (is_local_state_off(CORE_PWR_STATE(target_state))) { + sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], + SC_PM_PW_MODE_ON, SC_PM_WAKE_SRC_GIC); + plat_gic_cpuif_enable(); + } else { + write_scr_el3(read_scr_el3() & (~0x4)); + isb(); + } } void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) @@ -271,13 +315,15 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint, /* sec_entrypoint is used for warm reset */ *psci_ops = &imx_plat_psci_ops; - /* request low power mode for A35 cluster, only need to do once */ - sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_OFF); + /* make sure system sources power ON in low power mode by default */ + sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_ON); - /* Request RUN and LP modes for DDR, system interconnect etc. */ - sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); - sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); - sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_DDR, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_MU, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); + sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT, + SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON); return 0; } diff --git a/plat/imx/imx8qxp/include/platform_def.h b/plat/imx/imx8qxp/include/platform_def.h index 55ce4a6e..fa6d2709 100644 --- a/plat/imx/imx8qxp/include/platform_def.h +++ b/plat/imx/imx8qxp/include/platform_def.h @@ -49,6 +49,10 @@ #define MAX_XLAT_TABLES 8 #define MAX_MMAP_REGIONS 9 +#define IMX_REG_BASE 0x50000000 +#define IMX_REG_SIZE 0x10000000 +#define IMX_GPT0_LPCG_BASE 0x5d540000 +#define IMX_GPT0_BASE 0x5d140000 #define IMX_WUP_IRQSTR 0x51090000 #define IMX_BOOT_UART_BASE 0x5a060000 #define IMX_BOOT_UART_BAUDRATE 115200 diff --git a/plat/imx/imx8qxp/include/sec_rsrc.h b/plat/imx/imx8qxp/include/sec_rsrc.h index 2beffb6f..81114d18 100644 --- a/plat/imx/imx8qxp/include/sec_rsrc.h +++ b/plat/imx/imx8qxp/include/sec_rsrc.h @@ -16,10 +16,12 @@ sc_rsrc_t secure_rsrcs[] = { SC_R_A35_3, SC_R_GIC, SC_R_SYSTEM, + SC_R_GPT_0, SC_R_IRQSTR_SCU2 }; /* resources that have register access for non-secure domain */ sc_rsrc_t ns_access_allowed[] = { SC_R_GIC, + SC_R_GPT_0, }; diff --git a/plat/imx/imx8qxp/platform.mk b/plat/imx/imx8qxp/platform.mk index baf2f3b9..42626bcd 100644 --- a/plat/imx/imx8qxp/platform.mk +++ b/plat/imx/imx8qxp/platform.mk @@ -50,6 +50,7 @@ BL31_SOURCES += plat/imx/common/lpuart_console.S \ plat/imx/imx8qxp/imx8qxp_bl31_setup.c \ plat/imx/imx8qxp/imx8qxp_psci.c \ plat/imx/common/imx8_topology.c \ + plat/common/plat_psci_common.c \ lib/xlat_tables/xlat_tables_common.c \ lib/xlat_tables/aarch64/xlat_tables.c \ lib/cpus/aarch64/cortex_a35.S \ -- cgit v1.2.3