From 19ae85634b84adf67012cdabbf6d7673186f31e5 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 14 Jul 2017 17:40:07 +0800 Subject: imx8mq: gpc: mask m4 irq and override PLLs for dsm Need to mask all M4 IRQ and override all PLLs/OSC before entering DSM mode, but due to DRAM self-refresh NOT ready, non-fast wakeup mode is NOT working, so we still use fast wakeup mode, which means DSM mode by default is NOT entered. After DRAM self-refresh is added, we will switch to non-fast wakeup mode to make DSM work. Signed-off-by: Anson Huang --- plat/freescale/imx8mq/gpc.c | 66 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/plat/freescale/imx8mq/gpc.c b/plat/freescale/imx8mq/gpc.c index 58744c24..98ae2b28 100644 --- a/plat/freescale/imx8mq/gpc.c +++ b/plat/freescale/imx8mq/gpc.c @@ -38,6 +38,7 @@ #define GPC_IMR2_CORE1_A53 0x44 #define GPC_IMR3_CORE1_A53 0x48 #define GPC_IMR4_CORE1_A53 0x4c +#define GPC_IMR1_CORE0_M4 0x50 #define GPC_IMR1_CORE2_A53 0x1c0 #define GPC_IMR2_CORE2_A53 0x1c4 #define GPC_IMR3_CORE2_A53 0x1c8 @@ -98,6 +99,19 @@ #define GPC_ARM_PGC 0x800 #define PGC_PCR 0 +#define ANAMIX_HW_AUDIO_PLL1_CFG0 0x0 +#define ANAMIX_HW_AUDIO_PLL2_CFG0 0x8 +#define ANAMIX_HW_VIDEO_PLL1_CFG0 0x10 +#define ANAMIX_HW_GPU_PLL_CFG0 0x18 +#define ANAMIX_HW_VPU_PLL_CFG0 0x20 +#define ANAMIX_HW_ARM_PLL_CFG0 0x28 +#define ANAMIX_HW_SYS_PLL1_CFG0 0x30 +#define ANAMIX_HW_SYS_PLL2_CFG0 0x3c +#define ANAMIX_HW_SYS_PLL3_CFG0 0x48 +#define ANAMIX_HW_VIDEO_PLL2_CFG0 0x54 +#define ANAMIX_HW_DRAM_PLL_CFG0 0x60 +#define ANAMIX_HW_ANAMIX_MISC_CFG 0x70 + static uint32_t gpc_saved_imrs[128]; static uint32_t gpc_wake_irqs[128]; //static uint32_t gpc_mf_irqs[128]; @@ -306,6 +320,31 @@ void imx_gpc_pre_suspend(bool arm_power_off) mmio_write_32(IMX_GPC_BASE + GPC_IMR1_CORE0_A53 + i * 4, ~gpc_wake_irqs[i]); } + /* override PLL/OSC to let ccm control them */ + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL1_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL1_CFG0) | 0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL2_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL2_CFG0) | 0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_VIDEO_PLL1_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_VIDEO_PLL1_CFG0) | 0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_GPU_PLL_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_GPU_PLL_CFG0) | 0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_VPU_PLL_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_VPU_PLL_CFG0) | 0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_ARM_PLL_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_ARM_PLL_CFG0) | 0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL1_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL1_CFG0) | 0x1555540); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL2_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL2_CFG0) | 0x1555540); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL3_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL3_CFG0) | 0x140); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_VIDEO_PLL2_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_VIDEO_PLL2_CFG0) | 0x140); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_DRAM_PLL_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_DRAM_PLL_CFG0) | 0x140); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_ANAMIX_MISC_CFG, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_ANAMIX_MISC_CFG) | 0xa); } void imx_gpc_post_resume(void) @@ -332,6 +371,32 @@ void imx_gpc_post_resume(void) } /* set DUMMY PDN/PUP ACK by default for A53 domain */ mmio_write_32(IMX_GPC_BASE + GPC_PGC_ACK_SEL_A53, 1 << 31 | 1 << 15); + + /* clear override of PLL/OSC */ + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL1_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL1_CFG0) & ~0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL2_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL2_CFG0) & ~0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_VIDEO_PLL1_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_VIDEO_PLL1_CFG0) & ~0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_GPU_PLL_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_GPU_PLL_CFG0) & ~0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_VPU_PLL_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_VPU_PLL_CFG0) & ~0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_ARM_PLL_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_ARM_PLL_CFG0) & ~0x140000); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL1_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL1_CFG0) & ~0x1555540); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL2_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL2_CFG0) & ~0x1555540); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL3_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_SYS_PLL3_CFG0) & ~0x140); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_VIDEO_PLL2_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_VIDEO_PLL2_CFG0) & ~0x140); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_DRAM_PLL_CFG0, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_DRAM_PLL_CFG0) & ~0x140); + mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_ANAMIX_MISC_CFG, + mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_ANAMIX_MISC_CFG) & ~0xa); } static void imx_gpc_hwirq_mask(unsigned int hwirq) @@ -388,6 +453,7 @@ void imx_gpc_init(void) mmio_write_32(IMX_GPC_BASE + GPC_IMR1_CORE1_A53 + i * 4, ~0x0); mmio_write_32(IMX_GPC_BASE + GPC_IMR1_CORE2_A53 + i * 4, ~0x0); mmio_write_32(IMX_GPC_BASE + GPC_IMR1_CORE3_A53 + i * 4, ~0x0); + mmio_write_32(IMX_GPC_BASE + GPC_IMR1_CORE0_M4 + i * 4, ~0x0); } /* Due to the hardware design requirement, need to make -- cgit v1.2.3