From 079eebba34b09d6f9ffeb70d999fb4a065008b1c Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Mon, 20 Aug 2018 17:32:21 +0800 Subject: MLK-19256 plat: imx8mm: correct dram apb clock rate dvfs The DRAM APB bus clock rate is wrong before and after DVFS. The register offset for APB bus clock is wrong, so fix it. Signed-off-by: Bai Ping --- plat/imx/common/imx8m/clock.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/plat/imx/common/imx8m/clock.c b/plat/imx/common/imx8m/clock.c index 72ddbd9a..fee68218 100644 --- a/plat/imx/common/imx8m/clock.c +++ b/plat/imx/common/imx8m/clock.c @@ -8,9 +8,10 @@ #include #include -#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (IMX_CCM_BASE + 0x80 * (i) + 0x00) -#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (IMX_CCM_BASE + 0x80 * (i) + 0x04) -#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (IMX_CCM_BASE + 0x80 * (i) + 0x08) +#define IMX_CCM_IP_BASE (IMX_CCM_BASE + 0xa000) +#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x00) +#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x04) +#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x08) void ddr_pll_bypass_100mts(void) { -- cgit v1.2.3