Age | Commit message (Collapse) | Author |
|
Updating the CPU CORE power up timing to make sure
the RDC reload is done before CPU start to run code
in OCRAM space.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Current reset uses WDOG timeout function and default timeout
value is set to 0.5 second. However, it is better to trigger
reset immediately to speed up reboot process as well as prevent
the scenario of WDOG_B toggling later than CPU reset and PMIC
does NOT reset.
Set the WDE bit when IMX_WDOG_B_RESET is not enabled, or
reboot will fail.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Align code style between 8mq, 8mm and 8mn files.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
|
|
8DX and 8QX share the same die,
so will reuse the same implementation
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
(cherry picked from commit bb209a0b4ccca2aa4a3a887f9606dc4a3d294adf)
|
|
Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
|
|
Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
|
|
Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
|
|
Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
|
|
Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
|
|
Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
|
|
i.MX8 SoC with SCU inside support partition reboot, the partition reboot
will NOT reload the bl31.bin, so the data section could have some dirty
data of previous boot up, it will impact the reboot, so need to restore
the data section for partition reboot.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
|
|
i.MX8DXL ONLY supports up to 12*32 interrupt number, so the
first SPI interrupt offset should be from 0x2c.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit cd0519bf70382292768adc1e9c0337808c55f148)
|
|
Add support for new SoC i.MX8DXL
Signed-off-by: Teo Hall <teo.hall@nxp.com>
(cherry picked from a7a008da03cd08cae3387c428ad8145fb1fae354)
|
|
Add trusty support for imx8mq, default load address
and size for trusty os will be 0xfe000000 and 0x2000000.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from a708794ccde53d8253a74ff578ca9d5258971690)
|
|
Add trusty support for imx8mn, default load address and
size of trusty are 0xbe000000 and 0x2000000.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from commit 1566947ab431388906d71a1fb48e802fc9a1eec9)
|
|
Add trusty support for imx8mm, default load address
and size of trusty are 0xbe000000 anx 0x2000000.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from commit 28d3f0fa26ff11efb98281ed603b6f44cea3c6c5)
|
|
Open the power domain of MU4 and assign it to secure
world so trusty can call the SCFW API.
Test: Get SCFW and SECO-FW by trusty.
Change-Id: I6188f905426fd66072346089505fb1945e4362e3
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry-picked from commit 4dd8919a805336c6df8a791f238e8da1830dfe7b)
|
|
JR0 and JR1 of CAAM are owned by SECO, only kick the power
of JR2 and JR3 here and assign the resources to be accessed
by secure world.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from commit d82c0e65e74ce8b650ea3237a02249246080840d)
|
|
Mapped the BL32 code into MMU due the Trusty
SPD need to check the code status and decide
the CPU executing mode.
To reserve and protect the memory for secure
world, modify the partition code to keep
BL32 spaces in secure_part.
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 36ad60e46fd94eac7646218ae2b3e760bcfc33d6)
|
|
spd trusty requires memory dynamic mapping feature to be
enabled, so we have to use xlat table library v2 instead
of v1.
Test: builds.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
|
|
Build break due to result of β1 << 31β requires 33 bits to represent,
but βintβ only has 32 bits [-Werror=shift-overflow=].
Signed-off-by: Ji Luo <ji.luo@nxp.com>
|
|
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
|
|
Replace the magic number index with enum type to make RDC/CSU config
more clear for user.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the M core low power audio support on i.MX8M.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Enable the NOC wrapper power down support for SoC that
have switchable NOC power domain.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the NOC QoS setting SiP handler on imx8mq.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the SRC SiP handler for M4/M7 boot support on i.MX8M SoC.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the HAB secure boot support for the i.MX8M SoC family.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Enable DRAM DVFS support on i.MX8MQ.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
A53 core's power up ack need to be used when system resume
from DSM mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Use non-fast wakeup stop mode for system suspend support, so
the SOC can enter DSM mode by default.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the anamix PLL override setting for DSM mode support,
so that the PLL can be power down in DSM mode to save power.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
This new workaround takes advantage of the per core IMR registers in GPC in
order to unmask the IRQ0, still generated by the 12bit in IOMUX_GPR register
(which now remains always set), so it can only wake up one core at the time.
Also, this entire workaround has now been moved here in TF-A, allowing the
kernel side to be minimal.
Another advantage this workaround brings is the removal of the 50us delay
(which was necessary before in gic_raise_softirq in kernel) by allowing the
core that is waking up to mask his own IRQ0 in the suspend finish callback.
One important change here is the way the cores are woken up in
dram_dvfs_handler. Since the wake up mechanism has changed from asserting the
12th bit in IOMUX_GPR and leaving the IMR1 1st bit on for each core to exactly
the reverse, that is, leaving the IOMUX_GPR 12th bit always set and then
masking/unmasking the IMR1 1st bit for each independent core, we need to use
the imx_gpc_core_wake to wake up the cores.
Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off) from kernel
(gic_raise_softirq), since the new cpuidle workaround does not need it in order
to clean the IOMUX_GPC 12bit. For now, the udelay seems to be still needed
in order to delay the affinity info OFF for the dying core. This is something
that needs further investigation.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be copied from dram into ocram.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Move the stack & xlat table into ocram_s due to the
ocram is not enough.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the CSU init on i.MX8MN & config the ocram
secure access range. CSU config for specific
system design can be added in the 'csu_cfg' array.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Enable the CSU init on imx8mm. The 'csu_cfg' array
is just a placeholder for now as example. In real
use case, user can add the CSU config as needed
based on system design.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add a simple CSU driver for i.MX8M family.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
CPU hotplug & cpuidle have some race condition when doing CPU hotplug
stress test. different CPU cores have the chance to access the same
GPC register(A53_AD), so lock is necessary to do exlusive access.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.
for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
delay time should longer than 82us.
2. after system clock configuration. ipg clock runs at 66.5MHz.
delay time should longer than 15.3us.
so add udelay 100 to safely clear the SRC bit 0.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
No need to keep all PU domains on as the full power domain driver
support has been added.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the PU power domain support for imx8mm/mn.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add PLL power down override & bypass support when
system enter DSM mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Keep A53 PLAT(SCU) power domain on in wait mode(ret).
RBC count only need to be set in PLAT OFF mode, so
change it accordingly.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
On iMX8 Rev A the OCRAM is used to pass over ROM info, and u-boot
needs to access it. So we can't assign the OCRAM to ATF partition.
This will cause boot hang.
Rev A does not support SPL, so it is ok to not protect the OCRAM.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit c9a168bfd16e06b4d6b9f94185910023e4923cf2)
|
|
Because the partition reboot won't reload the first level bootloader (SPL),
the SPL won't be authenticated. Users can corrupt the SPL image to break
the boot trust chain in secure boot if we don't protect that OCRAM area.
This patch configures the memory area from 0x0 to 0x118000 only accessed by
secure partition (ATF and OPTEE). Non-secure partitions (u-boot and kernel)
can't access it.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1eff7d3ef6f121782e56bb1807744ede48b8580b)
(cherry picked from commit 96d33120bb57895db73e669ef0aeccde0d4875d5)
|
|
Sync SCFW API to commit b3c575a62b0e2
SCFW API version 16
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
|
|
Update flags for expected behavior in ATF
Signed-off-by: Teo Hall <teo.hall@nxp.com>
|
|
Add the DDR frequency change support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I84f0ef51b04b84da8ba2cbeca86a07338a4903de
|