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2020-03-31plat: imx8mp: add main noc Qos setting when exit from power downJacky Bai
If the Main NOC is power down before, need to reinit the QoS setting for A53, GIC & Supermix port. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-31plat: imx8mp: Override the the domain suspend callbackJacky Bai
The common domain suspend callback function is not suitable for i.MX8MP due to the wait mode workaround. it will be removed together with the wait mode workaround in the future. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-31plat: imx8m: Fix the m4 enabled check for imx8mJacky Bai
On i.MX8MN & i.MX8MP, the M core enabled check should relay on the IOMUX GPR CPU_WAIT bit, when this bit is cleared, it means M core is active & running, so refine the m4 enabled check method. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-31plat: imx8m: Replace magic number with macro definesJacky Bai
Replace the imr offset magic number with macro defines. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-27plat: imx8mp: Enable BL32 fdt overlay support on imx8mpJacky Bai
Allow OP-TEE to generate a device-tree overlay binary that will be applied by u-boot on the regular dtb. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-27plat: imx8mp: Add clock handling for hsiomixJacky Bai
Due to the design requirement, the HSIOMIX need to be RPM always on, so HSIOMIX need to be boot on by default. There are no way to manage the clocks when doing domain on/off, add clock handling in TF-A to resolve this issue. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-27plat: imx8mp: imx8mp wait mode workaroundJacky Bai
Add the i.MX8MP workaround for wait mode just for Alpha release, this patch will be dropped in the future. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-27plat: imx8mp: Add basic support for imx8mpJacky Bai
Add the basic support for i.MX8MP. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-27plat: imx8m: move the gpc reg & macro to a separate header fileJacky Bai
move the gpc reg offset, bit define & macro to a separate header file for code reuse. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-27plat: imx8mm: Update the cpu core power up timingJacky Bai
Updating the CPU CORE power up timing to make sure the RDC reload is done before CPU start to run code in OCRAM space. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-27plat: imx8m: update the wdog config for system resetJacky Bai
Current reset uses WDOG timeout function and default timeout value is set to 0.5 second. However, it is better to trigger reset immediately to speed up reboot process as well as prevent the scenario of WDOG_B toggling later than CPU reset and PMIC does NOT reset. Set the WDE bit when IMX_WDOG_B_RESET is not enabled, or reboot will fail. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-27plat: imx8mq/mm/mn: Cleanup bl31_setupSilvano di Ninno
Align code style between 8mq, 8mm and 8mn files. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2020-03-27TEE-532-7 plat: imx8dx: Add support for BL32Silvano di Ninno
8DX and 8QX share the same die, so will reuse the same implementation Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit bb209a0b4ccca2aa4a3a887f9606dc4a3d294adf)
2020-03-27TEE-532-6: plat: imx8qx: add optee supportSilvano di Ninno
Port and cleanup OP-TEE support. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2020-03-27TEE-532-5: plat: imx8qm: add optee supportSilvano di Ninno
Port and cleanup OP-TEE support. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2020-03-27TEE-532-4: plat: imx8mq: add optee supportSilvano di Ninno
Port and cleanup OP-TEE support. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2020-03-27TEE-532-3: plat: imx8mn: add optee supportSilvano di Ninno
Port and cleanup OP-TEE support. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2020-03-27TEE-532-2: plat: imx8mm: add optee supportSilvano di Ninno
Port and cleanup OP-TEE support. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2020-03-27TEE-532-1: plat: imx8dxl: add optee supportSilvano di Ninno
Port and cleanup OP-TEE support. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2020-03-27plat: imx: Add data section restore for i.MX8 SoCs with partition rebootAnson Huang
i.MX8 SoC with SCU inside support partition reboot, the partition reboot will NOT reload the bl31.bin, so the data section could have some dirty data of previous boot up, it will impact the reboot, so need to restore the data section for partition reboot. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2020-03-25plat: imx8dxl: Update IRQSTEER mask offset for proper wakeupAnson Huang
i.MX8DXL ONLY supports up to 12*32 interrupt number, so the first SPI interrupt offset should be from 0x2c. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit cd0519bf70382292768adc1e9c0337808c55f148)
2020-03-10plat: imx8dxl: Add iMX8DXL supportTeo Hall
Add support for new SoC i.MX8DXL Signed-off-by: Teo Hall <teo.hall@nxp.com> (cherry picked from a7a008da03cd08cae3387c428ad8145fb1fae354)
2020-03-09MA-14173 Enable trusty for imx8mqJi Luo
Add trusty support for imx8mq, default load address and size for trusty os will be 0xfe000000 and 0x2000000. Signed-off-by: Ji Luo <ji.luo@nxp.com> (cherry picked from a708794ccde53d8253a74ff578ca9d5258971690)
2020-03-09MA-15087 Enable Trusty OS for imx8mnJi Luo
Add trusty support for imx8mn, default load address and size of trusty are 0xbe000000 and 0x2000000. Signed-off-by: Ji Luo <ji.luo@nxp.com> (cherry picked from commit 1566947ab431388906d71a1fb48e802fc9a1eec9)
2020-03-09MA-13758 Enable Trusty OS on imx8mmJi Luo
Add trusty support for imx8mm, default load address and size of trusty are 0xbe000000 anx 0x2000000. Signed-off-by: Ji Luo <ji.luo@nxp.com> (cherry picked from commit 28d3f0fa26ff11efb98281ed603b6f44cea3c6c5)
2020-03-09MA-15289-4 Integrate SCFW API lib to trustyJi Luo
Open the power domain of MU4 and assign it to secure world so trusty can call the SCFW API. Test: Get SCFW and SECO-FW by trusty. Change-Id: I6188f905426fd66072346089505fb1945e4362e3 Signed-off-by: Ji Luo <ji.luo@nxp.com> (cherry-picked from commit 4dd8919a805336c6df8a791f238e8da1830dfe7b)
2020-03-09imx8q: [trusty] Kick CAAM powerJi Luo
JR0 and JR1 of CAAM are owned by SECO, only kick the power of JR2 and JR3 here and assign the resources to be accessed by secure world. Signed-off-by: Ji Luo <ji.luo@nxp.com> (cherry picked from commit d82c0e65e74ce8b650ea3237a02249246080840d)
2020-03-09MA-11015 Support Trusty OS on imx8qm/qxpHaoran.Wang
Mapped the BL32 code into MMU due the Trusty SPD need to check the code status and decide the CPU executing mode. To reserve and protect the memory for secure world, modify the partition code to keep BL32 spaces in secure_part. Signed-off-by: Haoran.Wang <elven.wang@nxp.com> Signed-off-by: Ji Luo <ji.luo@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 36ad60e46fd94eac7646218ae2b3e760bcfc33d6)
2020-03-09MA-16438 plat:imx8/imx8m: switch to xlat_tables_v2Ji Luo
spd trusty requires memory dynamic mapping feature to be enabled, so we have to use xlat table library v2 instead of v1. Test: builds. Signed-off-by: Ji Luo <ji.luo@nxp.com>
2020-03-09imx8q: Fix build errorsJi Luo
Build break due to result of β€˜1 << 31’ requires 33 bits to represent, but β€˜int’ only has 32 bits [-Werror=shift-overflow=]. Signed-off-by: Ji Luo <ji.luo@nxp.com>
2020-03-07Enable CPU, FP, L2 retention counters to 64 cyclesNitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2020-03-03plat: imx8m: Replace the magic number rdc/csu index with enum typeJacky Bai
Replace the magic number index with enum type to make RDC/CSU config more clear for user. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-03plat: imx8m: add enum type for RDC/CSU indexJacky Bai
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8m: Add the M4 low power audio support on imx8mJacky Bai
Add the M core low power audio support on i.MX8M. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8m: Enable the noc power down support on imx8mJacky Bai
Enable the NOC wrapper power down support for SoC that have switchable NOC power domain. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mq: Add the NOC sip handler on imx8mqJacky Bai
Add the NOC QoS setting SiP handler on imx8mq. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8m: Add the src handler for m4/m7 core boot supportJacky Bai
Add the SRC SiP handler for M4/M7 boot support on i.MX8M SoC. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8m: Add hab suport on imx8m SoC familyJacky Bai
Add the HAB secure boot support for the i.MX8M SoC family. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mq: Enable dram dvfs support on imx8mqJacky Bai
Enable DRAM DVFS support on i.MX8MQ. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mq: Correct the slot ack setting for STOP modeJacky Bai
A53 core's power up ack need to be used when system resume from DSM mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8m: use non-fast wakeup stop mode for system suspendJacky Bai
Use non-fast wakeup stop mode for system suspend support, so the SOC can enter DSM mode by default. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mq: Add anamix pll override setting for DSM modeJacky Bai
Add the anamix PLL override setting for DSM mode support, so that the PLL can be power down in DSM mode to save power. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mq: Add workaround code for ERR11171 on imx8mqJacky Bai
This new workaround takes advantage of the per core IMR registers in GPC in order to unmask the IRQ0, still generated by the 12bit in IOMUX_GPR register (which now remains always set), so it can only wake up one core at the time. Also, this entire workaround has now been moved here in TF-A, allowing the kernel side to be minimal. Another advantage this workaround brings is the removal of the 50us delay (which was necessary before in gic_raise_softirq in kernel) by allowing the core that is waking up to mask his own IRQ0 in the suspend finish callback. One important change here is the way the cores are woken up in dram_dvfs_handler. Since the wake up mechanism has changed from asserting the 12th bit in IOMUX_GPR and leaving the IMR1 1st bit on for each core to exactly the reverse, that is, leaving the IOMUX_GPR 12th bit always set and then masking/unmasking the IMR1 1st bit for each independent core, we need to use the imx_gpc_core_wake to wake up the cores. Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off) from kernel (gic_raise_softirq), since the new cpuidle workaround does not need it in order to clean the IOMUX_GPC 12bit. For now, the udelay seems to be still needed in order to delay the affinity info OFF for the dying core. This is something that needs further investigation. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mq: Add the dram retention support for imx8mqJacky Bai
Add the dram retention support for i.MX8MQ. As there is no enough ocram space available before entering TF-A, so the timing info need to be copied from dram into ocram. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mq: move the stack & xlat table into ocram_sJacky Bai
Move the stack & xlat table into ocram_s due to the ocram is not enough. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mn: Add the csu init on imx8mnJacky Bai
Add the CSU init on i.MX8MN & config the ocram secure access range. CSU config for specific system design can be added in the 'csu_cfg' array. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mm: Enable the csu init on imx8mmJacky Bai
Enable the CSU init on imx8mm. The 'csu_cfg' array is just a placeholder for now as example. In real use case, user can add the CSU config as needed based on system design. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8m: Add a simple csu driver for imx8m familyJacky Bai
Add a simple CSU driver for i.MX8M family. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8m: Fix the race condition during cpu hotplugJacky Bai
CPU hotplug & cpuidle have some race condition when doing CPU hotplug stress test. different CPU cores have the chance to access the same GPC register(A53_AD), so lock is necessary to do exlusive access. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mq: add 100us delay after USB OTG SRC bit 0 clearJacky Bai
After the SRC bit clear, we must wait for a while to make sure the operation is finished. And don't enable all the PU domains by default. for USB OTG, the limitations are: 1. before system clock configuration. ipg clock runs at 12.5MHz. delay time should longer than 82us. 2. after system clock configuration. ipg clock runs at 66.5MHz. delay time should longer than 15.3us. so add udelay 100 to safely clear the SRC bit 0. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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