summaryrefslogtreecommitdiff
path: root/plat
AgeCommit message (Collapse)Author
2017-07-12Add i.MX8QXP supportAnson Huang
Add i.MX8QXP platform support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12Add i.MX8QM suport.Anson Huang
Add i.MX8QM platform support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-12Add i.MX8 SoCs supportAnson Huang
This patch adds i.MX8 SoCs ATFW support, including below basic features: * LPUART * SCFW RPC * SMP boot up Each SoC will have its own platform definition and driver to support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-06-28Use CryptoCell to set/get NVcounters and ROTPKSoby Mathew
This patch implements the platform APIs plat_get_rotpk_info, plat_get_nv_ctr, plat_set_nv_ctr to invoke CryptoCell SBROM APIs when ARM_CRYPTOCELL_INT is set. Change-Id: I693556b3c7f42eceddd527abbe6111e499f55c45 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28ARM plat changes to enable CryptoCell integrationSoby Mathew
This patch makes the necessary changes to enable ARM platform to successfully integrate CryptoCell during Trusted Board Boot. The changes are as follows: * A new build option `ARM_CRYPTOCELL_INTEG` is introduced to select the CryptoCell crypto driver for Trusted Board boot. * The TrustZone filter settings for Non Secure DRAM is modified to allow CryptoCell to read this memory. This is required to authenticate BL33 which is loaded into the Non Secure DDR. * The CSS platforms are modified to use coherent stacks in BL1 and BL2 when CryptoCell crypto is selected. This is because CryptoCell makes use of DMA to transfer data and the CryptoCell SBROM library allocates buffers on the stack during signature/hash verification. Change-Id: I1e6f6dcd1899784f1edeabfa2a9f279bbfb90e31 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Merge pull request #1004 from rockchip-linux/erratum-rk3399danh-arm
rockchip: enable A53's erratum 855873 for rk3399
2017-06-28Merge pull request #1002 from douglas-raillard-arm/dr/fix_errata_a53danh-arm
Apply workarounds for A53 Cat A Errata 835769 and 843419
2017-06-28Merge pull request #1001 from davidcunado-arm/dc/fix-signed-comparisonsdanh-arm
Resolve signed-unsigned comparison issues
2017-06-28rockchip: enable A53's erratum 855873 for rk3399Caesar Wang
For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't support WriteEvict. and you will hit the condition L2ACTLR[3] with 0, as the Evict transactions should propagate to CCI-500 since it has snoop filters. Maybe this erratum applies to all Cortex-A53 cores so far, especially if RK3399's A53 is a r0p4. we should enable it to avoid data corruption, Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-06-27Merge pull request #1000 from dp-arm/dp/aarch32-bootdavidcunado-arm
juno/aarch32: Fix boot on Cortex A57 and A72
2017-06-27Resolve signed-unsigned comparison issuesDavid Cunado
A recent commit 030567e6f51731982a7e71cbd387de93bc0e35fd added U()/ULL() macro to TF constants. This has caused some signed-unsigned comparison warnings / errors in the TF static analysis. This patch addresses these issues by migrating impacted variables from signed ints to unsigned ints and vice verse where applicable. Change-Id: I4b4c739a3fa64aaf13b69ad1702c66ec79247e53 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-27Merge pull request #999 from douglas-raillard-arm/dr/fix_tegra_CFLAGSdavidcunado-arm
Fix Tegra CFLAGS usage
2017-06-26juno: Invalidate all caches before warm reset to AArch32 state.Dimitris Papastamos
On Juno AArch32, the L2 cache may contain garbage after the warm reset from AArch64 to AArch32. This is all fine until the MMU is configured and the data caches enabled. To avoid fetching stale data from the L2 unified cache, invalidate it before the warm reset to AArch32 state. Change-Id: I7d27e810692c02c3e83c9f31de67f6bae59a960a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-26juno/aarch32: Restore `SCP_BOOT_CFG_ADDR` to the cold boot valueDimitris Papastamos
Before BL2 loads the SCP ram firmware, `SCP_BOOT_CFG_ADDR` specifies the primary core. After the SCP ram firmware has started executing, `SCP_BOOT_CFG_ADDR` is modified. This is not normally an issue but the Juno AArch32 boot flow is a special case. BL1 does a warm reset into AArch32 and the core jumps to the `sp_min` entrypoint. This is effectively a `RESET_TO_SP_MIN` configuration. `sp_min` has to be able to determine the primary core and hence we need to restore `SCP_BOOT_CFG_ADDR` to the cold boot value before `sp_min` runs. This magically worked when booting on A53 because the core index was zero and it just so happened to match with the new value in `SCP_BOOT_CFG_ADDR`. Change-Id: I105425c680cf6238948625c1d1017b01d3517c01 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-23Merge pull request #997 from dp-arm/dp/spedavidcunado-arm
aarch64: Enable Statistical Profiling Extensions for lower ELs
2017-06-23Fix Tegra CFLAGS usageDouglas Raillard
Use TF_CFLAGS instead of CFLAGS, to allow CFLAGS to be overriden from the make command line. Change-Id: I3e5726c04bcd0176f232581b8be2c94413374ac7 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-22Apply workarounds for A53 Cat A Errata 835769 and 843419Douglas Raillard
These errata are only applicable to AArch64 state. See the errata notice for more details: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm048406/index.html Introduce the build options ERRATA_A53_835769 and ERRATA_A53_843419. Enable both of them for Juno. Apply the 835769 workaround as following: * Compile with -mfix-cortex-a53-835769 * Link with --fix-cortex-a53-835769 Apply the 843419 workaround as following: * Link with --fix-cortex-a53-843419 The erratum 843419 workaround can lead the linker to create new sections suffixed with "*.stub*" and 4KB aligned. The erratum 835769 can lead the linker to create new "*.stub" sections with no particular alignment. Also add support for LDFLAGS_aarch32 and LDFLAGS_aarch64 in Makefile for architecture-specific linker options. Change-Id: Iab3337e338b7a0a16b0d102404d9db98c154f8f8 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-22Merge pull request #990 from masahir0y/uniphierdavidcunado-arm
uniphier: embed ROTPK hash into BL1/BL2
2017-06-22Merge pull request #988 from Leo-Yan/fix_cpu_off_v1davidcunado-arm
plat: Hikey960: fix the CPU hotplug
2017-06-22aarch64: Enable Statistical Profiling Extensions for lower ELsdp-arm
SPE is only supported in non-secure state. Accesses to SPE specific registers from SEL1 will trap to EL3. During a world switch, before `TTBR` is modified the SPE profiling buffers are drained. This is to avoid a potential invalid memory access in SEL1. SPE is architecturally specified only for AArch64. Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-06-20uniphier: embed ROTPK hash into BL1/BL2Masahiro Yamada
Currently, ROTPK_NOT_DEPLOYED flag is set in plat_get_rotpk_info(). It is up to users how to retrieve ROTPK if the ROT verification is desired. This is not nice. This commit improves plat_get_rotpk_info() implementation and automates the ROTPK deployment. UniPhier platform has no ROTPK storage, so it should be embedded in BL1/BL2, like ARM_ROTPK_LOCATION=devel_rsa case. This makes sense because UniPhier platform implements its internal ROM i.e. BL1 is used as updatable pseudo ROM. Things work like this: - ROT_KEY (default: $(BUILD_PLAT)/rot_key.pem) is created if missing. Users can override ROT_KEY from the command line if they want to use a specific ROT key. - ROTPK_HASH is generated based on ROT_KEY. - ROTPK_HASH is included by uniphier_rotpk.S and compiled into BL1/BL2. - ROT_KEY is input to cert_create tool. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-20juno: Fix AArch32 buildDimitris Papastamos
Commit 6de8b24f52cf2bd74adefbaa86dd2a0676c3eaa2 broke Juno AArch32 build. Change-Id: Ied70d9becb86e53ccb46a2e3245e2a551d1bf701 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20sp_min: Implement `sp_min_plat_runtime_setup()`Dimitris Papastamos
On ARM platforms before exiting from SP_MIN ensure that the default console is switched to the runtime serial port. Change-Id: I0ca0d42cc47e345d56179eac16aa3d6712767c9b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20Resolve build errors flagged by GCC 6.2David Cunado
With GCC 6.2 compiler, more C undefined behaviour is being flagged as warnings, which result in build errors in ARM TF build. This patch addresses issue caused by enums with values that exceed maximum value for an int. For these cases the enum is converted to a set of defines. Change-Id: I5114164be10d86d5beef3ea1ed9be5863855144d Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-20Merge pull request #991 from davidcunado-arm/dc/update_hikeydavidcunado-arm
hikey960: migrate to use A53 specific defines
2017-06-20hikey960: migrate to use A53 specific definesDavid Cunado
The patch fb7d32e5881ef2445e8fe2305005f5590d4a7cfa migrated the CPU libraries to have unique defines, prefixing them with the CPU name. This patch migrates the hikey960 platform port to use the A53 specific defines. Change-Id: Id76f544b0b236bbd4974ab5ffa1203f073c20021 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-19plat: Hikey960: fix the CPU hotplugLeo Yan
In CPU off callback function, the old code uses the function hisi_test_pwrdn_allcores() to check if all CPUs in cluster have been powered off and if it's valid then power off the whole cluster. But the function hisi_test_pwrdn_allcores() only maintains the different power states only for CPU suspend/resume flow, so it cannot return correct states for CPU on/off flow. This patch is to change use hisi_test_cpu_down() to check if all CPUs have been powered off, so that can power off the whole cluster properly when all CPUs in cluster have been hotplugged off. Signed-off-by: Tao Wang <kevin.wangtao@hisilicon.com> Signed-off-by: Leo Yan <leo.yan@linaro.org>
2017-06-16Merge pull request #953 from vwadekar/tegra-misra-fixes-v1davidcunado-arm
Tegra misra fixes v1
2017-06-16Merge pull request #984 from masahir0y/uniphierdavidcunado-arm
uniphier memory-overrun bug fix
2017-06-16Merge pull request #986 from jagadeeshujja/jagujj/fix-get-power-statedavidcunado-arm
CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is set
2017-06-15Merge pull request #981 from soby-mathew/sm/cov_scmidavidcunado-arm
Fix coverity error in CSS SCMI driver
2017-06-15CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is setjagadeesh ujja
The ARM_PLAT_MT bit enables the support for MT bit in MPIDR format. This means that the level 0 affinity represents the thread and CPU / Cluster levels are at affinity level 1 and 2 respectively. This was not catered for in the scpi 'css_scp_get_power_state, API. Since the SCPI driver can only cater for single threaded CPUs, this patch fixes the problem by catering for this shift by effectively ignoring the Thread (level 0) affinity level. Change-Id: If44f55c9fb2773c8d3f8a9bbcf5420a6f7409dfe Signed-off-by: jagadeesh ujja <jagadeesh.ujja@arm.com>
2017-06-15hikey960: remove mailbox driverHaojian Zhuang
Since this mailbox driver is abandoned, remove it. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-06-15uniphier: fix memory over-run bugMasahiro Yamada
Check the array index before the write. This issue was found by a static analysis tool. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-14Tegra186: mce: fix MISRA defectsAnthony Zhou
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] * Added parentheses [Rule 12.1] * Voided non C-library functions whose return types are not used [Rule 17.7] Change-Id: I91404edec2e2194b1ce2672d2a3fc6a1f5bf41f1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: delay_timer: fix MISRA defectsAnthony Zhou
Main fixes: * Include header file for function declarations [Rule 8.4] * Move global object into function [Rule 8.9] Change-Id: I1bc9f3f0ebd4ffc0b8444ac856cd97b0cb56bda4 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2017-06-14Tegra: gic: fix MISRA defectsVarun Wadekar
Main fixes: * Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Fixed assert/if statements conditions to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Convert macros form headers to unsigned ints Change-Id: I8051cc16499cece2039c9751bd347645f40f0901 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: fiq_glue: fix MISRA defectsAnthony Zhou
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Convert object type to match the type of function parameters [Rule 10.3] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses[Rule 20.7] Change-Id: I5cf83caafcc1650b545ca731bf3eb8f0bfeb362b Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2017-06-14Tegra: pmc: fix defects flagged during MISRA analysisAnthony Zhou
Main fixes: * Fixed if/while statement conditional to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if/for/while statements in order to make them compound [Rule 15.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Change-Id: Ic72b248aeede6cf18bf85051188ea7b8fd8ae829 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2017-06-14Tegra: memctrl: check GPU reset state from common placeVarun Wadekar
This patch moves the GPU reset state check, during VideoMem resize, to the common SiP handler, to reduce code duplication. Change-Id: I3818c5f104b809da83dc2a61d6a8149606f81c13 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: memctrl_v2: fix software logic to check "flush complete"Varun Wadekar
This patch fixes the logic to check if the command written to the MC_CLIENT_HOTRESET_CTRLx registers, was accepted by the hardware module. Change-Id: If94fff9424555cb4688042eda17b4b20f4eb399a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: add explicit casts for integer macrosVarun Wadekar
This patch adds explicit casts (U(x)) to integers in the tegra_def.h headers, to make them compatible with whatever operation they're used in [MISRA-C Rule 10.1] Change-Id: Ic5fc611aad986a2c6e6e6f625e0753ab9b69eb02 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Unique names for defines in the CPU librariesVarun Wadekar
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: enable 'signed-comparison' compilation warning/errorsVarun Wadekar
This patch enables the 'sign-compare' flag, to enable warning/errors for comparisons between signed/unsigned variables. The warning has been enabled for all the Tegra platforms, to start with. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-13Merge pull request #974 from masahir0y/uniphierdavidcunado-arm
UniPhier Initial Support
2017-06-13hikey960: fix the calculation in boardidHaojian Zhuang
Since the type of ADC value is always unsigned int, don't need to check the value with negative value. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-06-13uniphier: add TSP supportMasahiro Yamada
Add TSP to test BL32 without relying on external projects. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-13uniphier: support Socionext UniPhier platformMasahiro Yamada
Initial commit for Socionext UniPhier SoC support. BL1, Bl2, and BL31 are supported. Refer to docs/plat/socionext-uniphier.md for more detais. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-09Fix coverity error in CSS SCMI driverSoby Mathew
Change-Id: Ia7d731f429e452e4bc9f9a553d7105b6394c621c Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-09Merge pull request #971 from Xilinx/tegradavidcunado-arm
tegra: Fix build errors
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-23 05:45:48 +0000