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2017-08-02imx8mq: fix the pcie power domain dependencyBai Ping
the PCIE1 and PCIE2 share the same reset signal, if PCIE2 is power down, PCIE1 will also be power down, so when we need to power up PCIE1, the PCIE2 need to power up too, only PCIE1 is power down, the PCIE2 power domain can be power down too Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-26imx8mq: do NOT enable all PU power during boot upAnson Huang
No need to enable all PU power during boot up, module driver will enable their power domain as needed. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-24imx8mq: Add the AIPS4 configurationsYe Li
Set the MPROTx and OPACRx in AIPS4 configuration registers to allow user mode and non-supervisor privilege level to access. Signed-off-by: Ye Li <ye.li@nxp.com>
2017-07-21imx8qm/qxp: Reserve memory region for ATFYe Li
Reserve the memory region that is only can access by ATF. ATF is running in this memory region, while masters in other partitions can't access it. Signed-off-by: Ye Li <ye.li@nxp.com>
2017-07-19imx8qm/qxp: Modify the memory regions allocation to NS partitionYe Li
Change to search the ATF owned memory regions and assign them to non-secure OS partition. Not allocate new memory region for each one. Signed-off-by: Ye Li <ye.li@nxp.com>
2017-07-19imx8mq: gpc: power domain id needs to be mapped to register bit offsetAnson Huang
The power domain id does NOT equal to the register bit offset, so need to do a mapping here. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-19imx8mq: gpc: add hardware power down for power domainAnson Huang
Add hardware power down for all power domains. Make imx_gpc_set_m_core_pgc usable for all MIX and PU PGC. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-14imx8mq: gpc: mask m4 irq and override PLLs for dsmAnson Huang
Need to mask all M4 IRQ and override all PLLs/OSC before entering DSM mode, but due to DRAM self-refresh NOT ready, non-fast wakeup mode is NOT working, so we still use fast wakeup mode, which means DSM mode by default is NOT entered. After DRAM self-refresh is added, we will switch to non-fast wakeup mode to make DSM work. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-13Move TZC EN into SPLPeng Fan
Move TZC EN into SPL, and add check in ATF. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12imx8m: add SNVS mappingPeng Fan
Add SNVS mapping to avoid system off failure. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12imx8mq: enable tzc380Peng Fan
enable tzc380 for i.mx8mq Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12imx8mq: change back BL31_LIMIT to 0x40020000Peng Fan
Change back BL31_LIMIT to 0x40020000, because TZC380 could not support 4K aligned address. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12imx8mq: add console initPeng Fan
Add console init Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12plat: freescale: imx8mq: add system off supportAnson Huang
Add system off support, linux kernel can issue "poweroff" to power down system. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-12imx8mq: add wdog resetPeng Fan
Add wdog reset support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12imx8mq: config the aipstz2 for imx8mqBai Ping
Enable the non-privilege access for AIPS address space. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-12i.mx8mq: Add basic support for i.mx8mqBai Ping
Add basic support for i.MX8MQ. 1. SMP support is ok. 2. basic suspend/resume support is ok. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-12imx8qm/imx8qxp: no need to disable console in plat runtime setupAnson Huang
As we already have control for debug console in platform_def.h, so no need to un-initialize console in plat runtime setup, just overwrite the common implementation with blank function. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-12Enable CPU, FP, L2 retention counters to 64 cyclesNitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2017-07-12iMX8QM/QXP: Allocate memory regions to NS partitionYe Li
Not only the resources, but also the memory regions need to assign to non-secure partition. Otherwise, when the boot partition is secured, the OS non-secure partition can't access any memory. This patch currently assign all memory to NS partition, since it is not isolated, the current secure partition also can access them. In future, may need to change the regions for reserving some memory in secure partition for ATF and BL32. Signed-off-by: Ye Li <ye.li@nxp.com>
2017-07-12iMX8QM: Do not terminate barrier transcations in CCINitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2017-07-12Fix the UART PAD ctrl in last commitNitin Garg
missed bit 31 and 30 which are needed Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2017-07-12Fix the pinmux to use correct resource ID for iMX8QM/QXNitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2017-07-12i.MX8: Update to the latest SCFW APIRanjani Vaidyanathan
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2017-07-12i.MX8QM: disable debug console by defaultNitin Garg
Disable ATF console output for iMX8QM Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2017-07-12i.MX8QXP: disable debug console by defaultAnson Huang
Disable debug console by default on i.MX8QXP. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-12Correct debug console baudrate for i.MX8QXP real boardAnson Huang
Debug console baudrate should be 115200 for i.MX8QXP real board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-12Add necessary resources to secure partition for i.MX8QXPAnson Huang
Add necessary resources to secure partition for protection. Also add in functionality to allow for register access of some secure-owned peripherals. These peripherals will still be protected from power or clk changes. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Teo Hall <teo.hall@nxp.com>
2017-07-12Add support for A72 CPU0 as primary cpuAnson Huang
Need to add support for booting up A72 cluster only, so on need to check the cluster ID for primary CPU, that means if CPU ID is 0, then it can be as primary CPU. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-12Fix A72 L2 DATA latency and support booting CA72 as primaryNitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2017-07-12Fix MMU mapping for MU in useTeo Hall
change MMU mapping to use the address of the MU currently being used for ATF Signed-off-by: Teo Hall <teo.hall@nxp.com>
2017-07-12update secure partition and add NS accessTeo Hall
add more resources to secure partition for protection. Also add in functionality to allow for register access of some secure-owned peripherals. These peripherals will still be protected from power or clk changes. Signed-off-by: Teo Hall <teo.hall@nxp.com>
2017-07-12add RM scu svc and partition secure MUTeo Hall
add rm svc api and set aside separate MU for secure api calls into SCU Signed-off-by: Teo Hall <teo.hall@nxp.com>
2017-07-12add macro for debug buildTeo Hall
add plat_crash_print_regs macro function to allow building with debug Signed-off-by: Teo Hall <teo.hall@nxp.com>
2017-07-12Correct debug uart baudrate for i.MX8QMAnson Huang
UART baudrate is 115200 on i.MX8QM ARM2 board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-12Add i.MX8QXP supportAnson Huang
Add i.MX8QXP platform support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12Add i.MX8QM suport.Anson Huang
Add i.MX8QM platform support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-12Add i.MX8 SoCs supportAnson Huang
This patch adds i.MX8 SoCs ATFW support, including below basic features: * LPUART * SCFW RPC * SMP boot up Each SoC will have its own platform definition and driver to support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-06-28Use CryptoCell to set/get NVcounters and ROTPKSoby Mathew
This patch implements the platform APIs plat_get_rotpk_info, plat_get_nv_ctr, plat_set_nv_ctr to invoke CryptoCell SBROM APIs when ARM_CRYPTOCELL_INT is set. Change-Id: I693556b3c7f42eceddd527abbe6111e499f55c45 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28ARM plat changes to enable CryptoCell integrationSoby Mathew
This patch makes the necessary changes to enable ARM platform to successfully integrate CryptoCell during Trusted Board Boot. The changes are as follows: * A new build option `ARM_CRYPTOCELL_INTEG` is introduced to select the CryptoCell crypto driver for Trusted Board boot. * The TrustZone filter settings for Non Secure DRAM is modified to allow CryptoCell to read this memory. This is required to authenticate BL33 which is loaded into the Non Secure DDR. * The CSS platforms are modified to use coherent stacks in BL1 and BL2 when CryptoCell crypto is selected. This is because CryptoCell makes use of DMA to transfer data and the CryptoCell SBROM library allocates buffers on the stack during signature/hash verification. Change-Id: I1e6f6dcd1899784f1edeabfa2a9f279bbfb90e31 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Merge pull request #1004 from rockchip-linux/erratum-rk3399danh-arm
rockchip: enable A53's erratum 855873 for rk3399
2017-06-28Merge pull request #1002 from douglas-raillard-arm/dr/fix_errata_a53danh-arm
Apply workarounds for A53 Cat A Errata 835769 and 843419
2017-06-28Merge pull request #1001 from davidcunado-arm/dc/fix-signed-comparisonsdanh-arm
Resolve signed-unsigned comparison issues
2017-06-28rockchip: enable A53's erratum 855873 for rk3399Caesar Wang
For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't support WriteEvict. and you will hit the condition L2ACTLR[3] with 0, as the Evict transactions should propagate to CCI-500 since it has snoop filters. Maybe this erratum applies to all Cortex-A53 cores so far, especially if RK3399's A53 is a r0p4. we should enable it to avoid data corruption, Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-06-27Merge pull request #1000 from dp-arm/dp/aarch32-bootdavidcunado-arm
juno/aarch32: Fix boot on Cortex A57 and A72
2017-06-27Resolve signed-unsigned comparison issuesDavid Cunado
A recent commit 030567e6f51731982a7e71cbd387de93bc0e35fd added U()/ULL() macro to TF constants. This has caused some signed-unsigned comparison warnings / errors in the TF static analysis. This patch addresses these issues by migrating impacted variables from signed ints to unsigned ints and vice verse where applicable. Change-Id: I4b4c739a3fa64aaf13b69ad1702c66ec79247e53 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-27Merge pull request #999 from douglas-raillard-arm/dr/fix_tegra_CFLAGSdavidcunado-arm
Fix Tegra CFLAGS usage
2017-06-26juno: Invalidate all caches before warm reset to AArch32 state.Dimitris Papastamos
On Juno AArch32, the L2 cache may contain garbage after the warm reset from AArch64 to AArch32. This is all fine until the MMU is configured and the data caches enabled. To avoid fetching stale data from the L2 unified cache, invalidate it before the warm reset to AArch32 state. Change-Id: I7d27e810692c02c3e83c9f31de67f6bae59a960a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-26juno/aarch32: Restore `SCP_BOOT_CFG_ADDR` to the cold boot valueDimitris Papastamos
Before BL2 loads the SCP ram firmware, `SCP_BOOT_CFG_ADDR` specifies the primary core. After the SCP ram firmware has started executing, `SCP_BOOT_CFG_ADDR` is modified. This is not normally an issue but the Juno AArch32 boot flow is a special case. BL1 does a warm reset into AArch32 and the core jumps to the `sp_min` entrypoint. This is effectively a `RESET_TO_SP_MIN` configuration. `sp_min` has to be able to determine the primary core and hence we need to restore `SCP_BOOT_CFG_ADDR` to the cold boot value before `sp_min` runs. This magically worked when booting on A53 because the core index was zero and it just so happened to match with the new value in `SCP_BOOT_CFG_ADDR`. Change-Id: I105425c680cf6238948625c1d1017b01d3517c01 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-23Merge pull request #997 from dp-arm/dp/spedavidcunado-arm
aarch64: Enable Statistical Profiling Extensions for lower ELs
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