Age | Commit message (Collapse) | Author |
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Move TZC EN into SPL, and add check in ATF.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add SNVS mapping to avoid system off failure.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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enable tzc380 for i.mx8mq
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Change back BL31_LIMIT to 0x40020000,
because TZC380 could not support 4K aligned address.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add console init
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add system off support, linux kernel can issue
"poweroff" to power down system.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add wdog reset support.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Enable the non-privilege access for AIPS address space.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add basic support for i.MX8MQ.
1. SMP support is ok.
2. basic suspend/resume support is ok.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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As we already have control for debug console in platform_def.h,
so no need to un-initialize console in plat runtime setup, just
overwrite the common implementation with blank function.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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Not only the resources, but also the memory regions need to assign to
non-secure partition. Otherwise, when the boot partition is secured,
the OS non-secure partition can't access any memory.
This patch currently assign all memory to NS partition, since it is not
isolated, the current secure partition also can access them. In future,
may need to change the regions for reserving some memory in secure
partition for ATF and BL32.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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missed bit 31 and 30 which are needed
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
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Disable ATF console output for iMX8QM
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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Disable debug console by default on i.MX8QXP.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Debug console baudrate should be 115200 for i.MX8QXP real board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add necessary resources to secure partition for protection.
Also add in functionality to allow for register access
of some secure-owned peripherals.
These peripherals will still be protected from power or
clk changes.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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Need to add support for booting up A72 cluster only,
so on need to check the cluster ID for primary CPU,
that means if CPU ID is 0, then it can be as primary
CPU.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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change MMU mapping to use the address of
the MU currently being used for ATF
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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add more resources to secure partition for
protection. Also add in functionality to allow
for register access of some secure-owned
peripherals.
These peripherals will still be protected from
power or clk changes.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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add rm svc api and set aside separate MU for
secure api calls into SCU
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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add plat_crash_print_regs macro function to
allow building with debug
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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UART baudrate is 115200 on i.MX8QM ARM2 board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add i.MX8QXP platform support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add i.MX8QM platform support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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This patch adds i.MX8 SoCs ATFW support, including below
basic features:
* LPUART
* SCFW RPC
* SMP boot up
Each SoC will have its own platform definition and driver
to support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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This patch implements the platform APIs plat_get_rotpk_info,
plat_get_nv_ctr, plat_set_nv_ctr to invoke CryptoCell SBROM
APIs when ARM_CRYPTOCELL_INT is set.
Change-Id: I693556b3c7f42eceddd527abbe6111e499f55c45
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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This patch makes the necessary changes to enable ARM platform to
successfully integrate CryptoCell during Trusted Board Boot. The
changes are as follows:
* A new build option `ARM_CRYPTOCELL_INTEG` is introduced to select
the CryptoCell crypto driver for Trusted Board boot.
* The TrustZone filter settings for Non Secure DRAM is modified
to allow CryptoCell to read this memory. This is required to
authenticate BL33 which is loaded into the Non Secure DDR.
* The CSS platforms are modified to use coherent stacks in BL1 and BL2
when CryptoCell crypto is selected. This is because CryptoCell makes
use of DMA to transfer data and the CryptoCell SBROM library allocates
buffers on the stack during signature/hash verification.
Change-Id: I1e6f6dcd1899784f1edeabfa2a9f279bbfb90e31
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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rockchip: enable A53's erratum 855873 for rk3399
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Apply workarounds for A53 Cat A Errata 835769 and 843419
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Resolve signed-unsigned comparison issues
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For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't
support WriteEvict. and you will hit the condition L2ACTLR[3] with 0,
as the Evict transactions should propagate to CCI-500 since it has
snoop filters.
Maybe this erratum applies to all Cortex-A53 cores so far, especially
if RK3399's A53 is a r0p4. we should enable it to avoid data corruption,
Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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juno/aarch32: Fix boot on Cortex A57 and A72
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A recent commit 030567e6f51731982a7e71cbd387de93bc0e35fd added U()/ULL()
macro to TF constants. This has caused some signed-unsigned comparison
warnings / errors in the TF static analysis.
This patch addresses these issues by migrating impacted variables from
signed ints to unsigned ints and vice verse where applicable.
Change-Id: I4b4c739a3fa64aaf13b69ad1702c66ec79247e53
Signed-off-by: David Cunado <david.cunado@arm.com>
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Fix Tegra CFLAGS usage
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On Juno AArch32, the L2 cache may contain garbage after the warm reset
from AArch64 to AArch32. This is all fine until the MMU is configured
and the data caches enabled. To avoid fetching stale data from the L2
unified cache, invalidate it before the warm reset to AArch32 state.
Change-Id: I7d27e810692c02c3e83c9f31de67f6bae59a960a
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Before BL2 loads the SCP ram firmware, `SCP_BOOT_CFG_ADDR` specifies
the primary core. After the SCP ram firmware has started executing,
`SCP_BOOT_CFG_ADDR` is modified. This is not normally an issue but
the Juno AArch32 boot flow is a special case. BL1 does a warm reset
into AArch32 and the core jumps to the `sp_min` entrypoint. This is
effectively a `RESET_TO_SP_MIN` configuration. `sp_min` has to be
able to determine the primary core and hence we need to restore
`SCP_BOOT_CFG_ADDR` to the cold boot value before `sp_min` runs.
This magically worked when booting on A53 because the core index was
zero and it just so happened to match with the new value in
`SCP_BOOT_CFG_ADDR`.
Change-Id: I105425c680cf6238948625c1d1017b01d3517c01
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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aarch64: Enable Statistical Profiling Extensions for lower ELs
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Use TF_CFLAGS instead of CFLAGS, to allow CFLAGS to be overriden from
the make command line.
Change-Id: I3e5726c04bcd0176f232581b8be2c94413374ac7
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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These errata are only applicable to AArch64 state. See the errata notice
for more details:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm048406/index.html
Introduce the build options ERRATA_A53_835769 and ERRATA_A53_843419.
Enable both of them for Juno.
Apply the 835769 workaround as following:
* Compile with -mfix-cortex-a53-835769
* Link with --fix-cortex-a53-835769
Apply the 843419 workaround as following:
* Link with --fix-cortex-a53-843419
The erratum 843419 workaround can lead the linker to create new sections
suffixed with "*.stub*" and 4KB aligned. The erratum 835769 can lead the
linker to create new "*.stub" sections with no particular alignment.
Also add support for LDFLAGS_aarch32 and LDFLAGS_aarch64 in Makefile for
architecture-specific linker options.
Change-Id: Iab3337e338b7a0a16b0d102404d9db98c154f8f8
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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uniphier: embed ROTPK hash into BL1/BL2
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plat: Hikey960: fix the CPU hotplug
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SPE is only supported in non-secure state. Accesses to SPE specific
registers from SEL1 will trap to EL3. During a world switch, before
`TTBR` is modified the SPE profiling buffers are drained. This is to
avoid a potential invalid memory access in SEL1.
SPE is architecturally specified only for AArch64.
Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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Currently, ROTPK_NOT_DEPLOYED flag is set in plat_get_rotpk_info().
It is up to users how to retrieve ROTPK if the ROT verification is
desired. This is not nice.
This commit improves plat_get_rotpk_info() implementation and automates
the ROTPK deployment. UniPhier platform has no ROTPK storage, so it
should be embedded in BL1/BL2, like ARM_ROTPK_LOCATION=devel_rsa case.
This makes sense because UniPhier platform implements its internal ROM
i.e. BL1 is used as updatable pseudo ROM.
Things work like this:
- ROT_KEY (default: $(BUILD_PLAT)/rot_key.pem) is created if missing.
Users can override ROT_KEY from the command line if they want to
use a specific ROT key.
- ROTPK_HASH is generated based on ROT_KEY.
- ROTPK_HASH is included by uniphier_rotpk.S and compiled into BL1/BL2.
- ROT_KEY is input to cert_create tool.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Commit 6de8b24f52cf2bd74adefbaa86dd2a0676c3eaa2 broke Juno AArch32
build.
Change-Id: Ied70d9becb86e53ccb46a2e3245e2a551d1bf701
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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On ARM platforms before exiting from SP_MIN ensure that
the default console is switched to the runtime serial port.
Change-Id: I0ca0d42cc47e345d56179eac16aa3d6712767c9b
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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