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2018-02-27Update ULL() macro and instances of ull to comply with MISRADavid Cunado
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
2018-01-29Disable workaround for CVE-2017-5715 on unaffected platformsDimitris Papastamos
Change-Id: Ib67b841ab621ca1ace3280e44cf3e1d83052cb73 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-08zynqmp: pm_service: use zynqmp_ipi APIsWendy Liang
Use zynqmp_ipi APIs to access IPI registers in pm_service. As the zynqmp_ipi APIs doesn't cover IPI buffers, the pm_ipi in pm_service will still directly access the IPI buffers. Signed-off-by: Wendy Liang <jliang@xilinx.com>
2018-01-08Add Xilinx ZynqMP IPI mailbox serviceWendy Liang
Add IPI mailbox service to manage Xilinx ZynqMP IPI(Inter Processors Interrupt) access. Signed-off-by: Wendy Liang <jliang@xilinx.com>
2018-01-08Introduce ZynqMP IPI implementationWendy Liang
Previously, ZynqMP IPI in ATF is only for ZynqMP PM, This patch is to have a ZynqMP IPI implementation to handle both ZynqMP PM IPI requirement and IPI mailbox service requirement which will be introduced next. We control IPI agents registers access but not IPI buffers access in this implementation. Each IPI mailbox user will directly access the IPI buffers. Signed-off-by: Wendy Liang <jliang@xilinx.com>
2017-11-30Do not enable SVE on pre-v8.2 platformsDavid Cunado
Pre-v8.2 platforms such as the Juno platform does not have the Scalable Vector Extensions implemented and so the build option ENABLE_SVE is set to zero. This has a minor performance improvement with no functional impact. Change-Id: Ib072735db7a0247406f8b60e325b7e28b1e04ad1 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-10-17zynqmp: Migrate to using interrupt propertiesJeenu Viswambharan
Change-Id: Ia8503d446cc8b4246013046f6294fea364c9c882 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-09-18zynqmp: Sync function declaration and definitionSoren Brinkmann
Synchronize argument order between function definition and declaration of pm_fpga_load. Fixes ARM-software/tf-issues#514 Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2017-07-14Fix order of remaining platform #includesIsla Mitchell
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-07-01zynqmp: Remove duplicate 'const' declarationSoren Brinkmann
Fixing compilation errors due to duplicate 'const' keyword: plat/xilinx/zynqmp/pm_service/pm_client.c:39:29: error: duplicate 'const' declaration specifier [-Werror=duplicate-decl-specifier] static const struct pm_proc const pm_procs_all[] = { ^~~~~ Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-04-06zynqmp: Enable workaround for errata 855873Soren Brinkmann
Zynqmp implements a version of the Cortex A53 affected by errata 855873. Enable the workaround for the errata and silence the warning: "WARNING: BL31: cortex_a53: errata workaround for 855873 was missing!". Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2017-03-20Move plat/common source file definitions to generic Makefilesdp-arm
These source file definitions should be defined in generic Makefiles so that all platforms can benefit. Ensure that the symbols are properly marked as weak so they can be overridden by platforms. NOTE: This change is a potential compatibility break for non-upstream platforms. Change-Id: I7b892efa9f2d6d216931360dc6c436e1d10cffed Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-02-06Replace some memset call by zeromemDouglas Raillard
Replace all use of memset by zeromem when zeroing moderately-sized structure by applying the following transformation: memset(x, 0, sizeof(x)) => zeromem(x, sizeof(x)) As the Trusted Firmware is compiled with -ffreestanding, it forbids the compiler from using __builtin_memset and forces it to generate calls to the slow memset implementation. Zeromem is a near drop in replacement for this use case, with a more efficient implementation on both AArch32 and AArch64. Change-Id: Ia7f3a90e888b96d056881be09f0b4d65b41aa79e Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-01-18Move BL_COHERENT_RAM_BASE/END defines to common_def.hMasahiro Yamada
We have lots of duplicated defines (and comment blocks too). Move them to include/plat/common/common_def.h. While we are here, suffix the end address with _END instead of _LIMIT. The _END is a better fit to indicate the linker-derived real end address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-18Use *_END instead of *_LIMIT for linker derived end addressesMasahiro Yamada
The usage of _LIMIT seems odd here, so rename as follows: BL_CODE_LIMIT --> BL_CODE_END BL_RO_DATA_LIMIT --> BL_RO_DATA_END BL1_CODE_LIMIT --> BL1_CODE_END BL1_RO_DATA_LIMIT --> BL1_RO_DATA_END Basically, we want to use _LIMIT and _END properly as follows: *_SIZE + *_MAX_SIZE = *_LIMIT *_SIZE + *_SIZE = *_END The _LIMIT is generally defined by platform_def.h to indicate the platform-dependent memory constraint. So, its typical usage is ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") in a linker script. On the other hand, _END is used to indicate the end address of the compiled image, i.e. we do not know it until the image is linked. Here, all of these macros belong to the latter, so should be suffixed with _END. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-06zynqmp: Migrate to new address space macrosSoren Brinkmann
Commit 0029624fe2d4c327ac885d04d5933f82f38e7071 ("Add PLAT_xxx_ADDR_SPACE_SIZE definition") deprecates 'ADDR_SPACE_SIZE' in favor of PLAT_(PHY|VIRT)_ADDRESS_SPACE_SIZE. Migrate the zynqmp platform to use the new interface. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-12-21zynqmp: add "override" directive to mandatory optionsMasahiro Yamada
The platform.mk sets build options required for ZynqMP, but users can still change them from the command line, like: make PLAT=zynqmp RESET_TO_BL31=0 CROSS_COMPILE=... Then, the makefile shows an error message in that case: Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1. If the option is not user-configurable, the makefile can specify "override" to prevent users from changing it. We do not need the error message for the case that never happens. Likewise, ENABLE_PLAT_COMPAT := 0 and PROGRAMMABLE_RESET_ADDRESS := 1 are mandatory to avoid build error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-12-14Fix incorrect copyright noticesAntonio Nino Diaz
Some files have incorrect copyright notices, this patch fixes all files with deviations from the standard notice. Change-Id: I66b73e78a50a235acb55f1e2ec2052a42c0570d2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2016-12-05Define and use no_ret macro where no return is expectedJeenu Viswambharan
There are many instances in ARM Trusted Firmware where control is transferred to functions from which return isn't expected. Such jumps are made using 'bl' instruction to provide the callee with the location from which it was jumped to. Additionally, debuggers infer the caller by examining where 'lr' register points to. If a 'bl' of the nature described above falls at the end of an assembly function, 'lr' will be left pointing to a location outside of the function range. This misleads the debugger back trace. This patch defines a 'no_ret' macro to be used when jumping to functions from which return isn't expected. The macro ensures to use 'bl' instruction for the jump, and also, for debug builds, places a 'nop' instruction immediately thereafter (unless instructed otherwise) so as to leave 'lr' pointing within the function range. Change-Id: Ib34c69fc09197cfd57bc06e147cc8252910e01b0 Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2016-11-16zynqmp: pm: Add SiP call to obtain PM callback dataSoren Brinkmann
The callback IRQ is delivered to the NS OS. Provide an interface to allow the NS OS to obtain the callback data from the secure HW. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-11-16zynqmp: pm: Enable IPI IRQ when API version is probedSoren Brinkmann
The IPI hardware is secure and managed by ATF, nevertheless we deliver the IRQ to the rich OS. The IRQ is needed to receive PM callbacks. Enable the IPI interrupt when the rich OS probes the API version. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-11-16zynqmp: Remove dead codeSoren Brinkmann
Remove dead code pieces and stale comments. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-11-16zynqmp: Fix UART1 base addressSoren Brinkmann
Cc: Michal Simek <michal.simek@xilinx.com> Reported-by: Jonas Karlsson <jonas.karlsson@atero.se> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-11-16zynqmp: PM: Migrate to new shutdown interfaceSoren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-11-16zynqmp: pm: Plumb get_chipid through FW interfaceSoren Brinkmann
Use the PMUFW get_chipid call to obtain IDCODE and version register. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-11-16zynqmp: pm: Allow obtaining additional return values from FWSoren Brinkmann
Allow reading more than just a single value from the message buffer. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-11-16zynqmp: Do not alter system counterSoren Brinkmann
On ZynqMP the FSBL will configure the system counter. Hence, remove the initialization of the system counter with hardcoded values from the ATF and use the setup provided by the bootloader. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-11-16zynqmp: Read silicon ID register only onceSoren Brinkmann
The silicon ID does not change at runtime. Skip the IO access if the ID has been read before. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-13zynqmp: Make MMIO write FW call synchronousSoren Brinkmann
We must guarantee that writes have become effective before returning to the caller. Hence, wait for PMUFW signaling completion of the FW call before returning to the rich OS. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: Add support to provide silicon id through SMCSiva Durga Prasad Paladugu
Add support to provide silicon id to non-secure software through SMC. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [ sb Move zynqmp_get_silicon_id outside of compile guards to avoid build errors. ] Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-09-13zynqmp: pm: Implemented pm API functions to load the bitstream into PLNava kishore Manne
This patch adds pm_fpga_load() and pm_fpga_get_status() API's to provide the Access to the xilfpga library to load the bitstream into zynqmp PL region. Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2016-09-13zynqmp: pm: adds new pm ID to sync with PMUFW ID numbersNava kishore Manne
This patch adds a new pm ID to sync with PMUFW ID numbers. Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2016-09-13zynqmp: Initialize GIC on suspend_finishSoren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: pm: Call set_wakeup_source for all wake devices on sys-suspendFilip Drazic
During system suspend, identify slaves which are configured as wake sources and call pm_set_wakeup_source API for each of them. Identifying if device may wake the system is done by checking if any interrupt of that device is enabled in GICD_ISENABLER when the APU is about to enter SUSPEND_TO_RAM state. If such interrupt is found, pm_set_wakeup_source is called with corresponding PM node ID as argument. Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
2016-09-13zynqmp: pm: Add PM node IDs for GPU, PCIE, PCAP and RTCFilip Drazic
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
2016-09-13zynqmp: pm: Provide state argument to the pm_self_suspend API callFilip Drazic
The state argument of the pm_self_suspend API encodes the state to which the APU intends to suspend. The state can be: - PM_APU_STATE_CPU_IDLE - processor power down, all memories remain on - PM_APU_STATE_SUSPEND_TO_RAM - all processors powered down, L2$ powered down, all OCM banks in retention and DDR in self-refresh. The calls for setting requirements for L2$ and OCM banks are now redundant and removed. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> [ sb - remove redundant #defines ] Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: Add simple implementation of zynqmp_validate_power_state()Stefan Krsmanovic
Implementation is based on arm_validate_power_state(). This function is called during CPU_SUSPEND PSCI call to validate power_state parameter. If state is valid this function populate it in req_state array as power domain level specific local state. ATF platform migration guide chapter 2.2 defines this function as mandatory for PSCIv1.0 CPU_SUSPEND support. Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>
2016-09-13zynqmp: Increase MAX_XLAT_TABLESSoren Brinkmann
When moving the ATF into the DRAM address space an additional translation table is required. Reported-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: Change default BL31 address spaceSoren Brinkmann
The OCM space was reorganized to use the space more efficiently. Adjust the default ATF location to be aligned with other ZynqMP software components. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: Add RW access to L2ACTLR_EL1 and CPUACTLR_EL1Naga Sureshkumar Relli
Arm provided error injection support. To enable this error injection, we need to set L2DEIEN in L2ACTLR_EL1 register and L1DEIEN in CPUACTLR_EL1 register. This is needed for our cortexa53 edac linux driver testing. These registers need write access from non secure EL1 i.e linux at the time of setting the above bits. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
2016-09-13zynqmp: Set RESET_TO_BL31 through platform.mkSoren Brinkmann
ZynqMP only supports builds with RESET_TO_BL31=1. Set this option through the platform makefile on default. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-09-13zynqmp: pm: Added NODE_IPI_RPU_0 node definition in pm_defsMirela Simonovic
Nodes represent IPI dedicated to the RPU (not accessible by APU) Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
2016-09-13zynqmp: Add support for generic_delay_timerSoren Brinkmann
Initialize the generic_delay_timer in the zynqmp port. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-08-09Migrate platform makefile to new console driver locationSoby Mathew
This patch migrates the upstream platform makefiles to include the console drivers from the new location in ARM Trusted Firmware code base. Change-Id: I866d6c4951e475de1f836ce8a8c1d5e6da9577e3
2016-07-25Merge pull request #667 from soby-mathew/sm/PSCI_libdanh-arm
Introduce PSCI library
2016-07-19Move `arm_common.c` out of aarch64 folderSoby Mathew
This patch moves the `arm_common.c` file from `plat/arm/common/aarch64/` to the parent directory since the functions implemented in the file are not AArch64 specific. The platform makefiles are also modified for this change. Change-Id: I776d2e4958f59041476cf2f53a9adb5b2d304ee0
2016-07-19Include `plat_psci_common.c` from the new locationSoby Mathew
The `plat_psci_common.c` was moved to the new location `plat/common` and a stub file was retained at previous location for compatibility. This patch modifies the platform makefiles to include the file from the new location. Change-Id: Iabddeeb824e9a5d72d176d7c644735966c8c0699
2016-07-11zynqmp: Separate code and rodataSoren Brinkmann
Set the SEPARATE_CODE_AND_RODATA build flag to map read-only data as execute never. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-07-08ARM platforms: Add support for SEPARATE_CODE_AND_RODATASandrine Bailleux
The arm_setup_page_tables() function used to expect a single set of addresses defining the extents of the whole read-only section, code and read-only data mixed up, which was mapped as executable. This patch changes this behaviour. arm_setup_page_tables() now expects 2 separate sets of addresses: - the extents of the code section; - the extents of the read-only data section. The code is mapped as executable, whereas the data is mapped as execute-never. New #defines have been introduced to identify the extents of the code and the read-only data section. Given that all BL images except BL1 share the same memory layout and linker script structure, these #defines are common across these images. The slight memory layout differences in BL1 have been handled by providing values specific to BL1. Note that this patch also affects the Xilinx platform port, which uses the arm_setup_page_tables() function. It has been updated accordingly, such that the memory mappings on this platform are unchanged. This is achieved by passing null values as the extents of the read-only data section so that it is ignored. As a result, the whole read-only section is still mapped as executable. Fixes ARM-software/tf-issues#85 Change-Id: I1f95865c53ce6e253a01286ff56e0aa1161abac5
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