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2019-09-03uniphier: set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driverMasahiro Yamada
This console driver sends '\r' before 'n', not after. It works, but the convention is "\r\n" (i.e. CRLF) Instead of fixing it in the driver, set CONSOLE_FLAG_TRANSLATE_CRLF to leave it to the framework. Change-Id: I2154e29313739a40dff70cfb5c0f8989136d4ad2 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-31uniphier: fix typo and coding styleMasahiro Yamada
Fix the typo "warn" -> "warm". Also fix the following checkpatch.pl warnings: CHECK: Prefer using the BIT macro CHECK: No space is necessary after a cast CHECK: Alignment should match open parenthesis CHECK: Unnecessary parentheses around uniphier_io_policies[image_id].dev_handle Change-Id: Ic11eea2668c4bf2d1e8f089e6338ba7b7156d80b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-31uniphier: replace DIV_ROUND_UP() with div_round_up() from utils_def.hMasahiro Yamada
Use the helper in utils_def.h instead of the own macro. Change-Id: I527f9e75914d60f66354e365006b960ba5e8cbae Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-12synquacer: Fix compilation fail for SPM support build configMadhukar Pappireddy
Fix the header file path Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I73a92a3f0049ecbda7eade452405927c04048e01
2019-07-05uniphier: support console based on multi-consoleMasahiro Yamada
The legacy console is gone. Re-add the console support based on the multi-console framework. I am still keeping the putc, getc, and flush callbacks in uniphier_console.S to use plat/common/aarch64/crash_console_helpers.S The console registration code already relies on that C environment has been set up. So, I just filled the struct console fields with the callback pointers, then called console_register() directly. I also re-implemented the init function in C to improve the readability. Removing the custom crash console implementation has one disadvantage; we cannot use the crash console on very early crashes because crash_console_helpers.S works only after the console is registered. I can live with this limitation. Tested on my boards, and confirmed this worked like before. Change-Id: Ieab9c849853ff6c525c15ea894a85944f257db59 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-28Remove MULTI_CONSOLE_API flag and references to itAmbroise Vincent
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-12Mbed TLS: Remove weak heap implementationAmbroise Vincent
The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13plat/arm: mhu: make mhu driver genericMasahisa Kojima
MHU doorbell driver requires arm platform specific macro "PLAT_CSS_MHU_BASE". Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm can use generic MHU doorbell driver. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2019-03-13plat/synquacer: enable SCMI supportMasahisa Kojima
Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific protocol(0x80). This vendor specific protocol is used to get the dram mapping information from SCP. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2019-02-01Remove unneeded include paths in PLAT_INCLUDESAntonio Nino Diaz
Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-01Remove duplicated definitions of linker symbolsAntonio Nino Diaz
Many parts of the code were duplicating symbols that are defined in include/common/bl_common.h. It is better to only use the definitions in this header. As all the symbols refer to virtual addresses, they have to be uintptr_t, not unsigned long. This has also been fixed in bl_common.h. Change-Id: I204081af78326ced03fb05f69846f229d324c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-22SPM: Rename SPM_DEPRECATED flag to SPM_MMAntonio Nino Diaz
The SPM implementation based on MM is going to be kept for the foreseeable future. Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Acked-by: Sumit Garg <sumit.garg@linaro.org>
2019-01-15plat/synquacer: enable SPM supportArd Biesheuvel
Enable the deprecated SPM framework for the SynQuacer platform. It involves creating a memory layout in secure DRAM, and wiring up the SPM infrastructure so that the secure partition payload that is loaded into this region by the SCP firmware is dispatched appropriately. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2019-01-15plat/synquacer: enable OP-TEE logic only if SPD_opteed is setArd Biesheuvel
The logic that initializes the BL32 entry point data structure should only be executed if we are in fact loading OP-TEE, and not if BL32_BASE is set for other reasons (i.e., when enabling SPM) Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-12-10io_block: define MAX_IO_BLOCK_DEVICES as unsignedYann Gautier
This is used as a table index, and already compared with an unsigned int: block_dev_count. Signed-off-by: Yann Gautier <yann.gautier@st.com>
2018-11-08Standardise header guards across codebaseAntonio Nino Diaz
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-30uniphier: revise SCP protocol handshakeDai Okamura
When the SoC issues a command IRQ to SCP, SCP sets STMTOBEIRQ as ACK. The SoC must wait for it before issuing the next command. This commit makes sure to meet the requirement. Signed-off-by: Dai Okamura <okamura.dai@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-30uniphier: terminate boot if SCP_BL2 image is missing in SCP boot modeMasahiro Yamada
Skipping SCP_BL2 image is just a temporary workaround. If on-chip SCP needs to work, BL2 should load the SCP_BL2 image. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-28uniphier: Migrate to new interfacesAntonio Nino Diaz
- Remove references to removed build options. - Migrate to bl31_early_platform_setup2(). Change-Id: I9242c4d02a36e385bf0bf8ee56287106030153d1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28synquacer: Migrate to new interfacesAntonio Nino Diaz
- Remove references to removed build options. - Update Makefile paths. - Migrate to bl31_early_platform_setup2(). Change-Id: I51cbf09a0297ac1ee645a959063238c9d556d8e1 Tested-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-30Fix MISRA defects in BL31 common codeAntonio Nino Diaz
Change-Id: I5993b425445ee794e6d2a792c244c0af53640655 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-08-22libc: Fix all includes in codebaseAntonio Nino Diaz
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-25Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misradanh-arm
Fix several MISRA defects in PSCI library
2018-07-24synquacer: Enable optional OP-TEE supportSumit Garg
OP-TEE loading is optional on Developerbox controlled via SCP firmware. To check if OP-TEE is loaded or not, we use DRAM1 region info passed by SCP firmware. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
2018-07-20PSCI: Fix types of definitionsAntonio Nino Diaz
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-06-21synquacer: Add platform makefile and documentationSumit Garg
Add Makefile and plaform definations file. My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces I've taken from their earlier work regarding build and deploy steps for Developerbox based on Synquacer SoCs. They deserve much of the credit for this work although, since I assembled and tested things, any blame is probably mine. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-06-21synquacer: Enable PSCI frameworkSumit Garg
PSCI framework uses SCPI driver to communicate to SCP firmware for various power management operations. Following PSCI operations are supported: - CPU ON - CPU OFF - CPU STANDBY - SYSTEM RESET - SYSTEM OFF Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Retrieve DRAM info from SCP firmwareArd Biesheuvel
Retrieve DRAM info from SCP firmware using SCPI driver. Board supports multiple DRAM slots so its required to fetch DRAM info from SCP firmware and pass this info to UEFI via non-secure SRAM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Add SCPI driverSumit Garg
Add System Control and Power Interface (SCPI) driver which provides APIs for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate with SCP firmware for various system control and power operations. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Add MHU driverSumit Garg
Add Message Handling Unit (MHU) driver used to communicate among Application Processors (AP) and System Control Processor (SCP). Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Enable MMU using xlat_tables_v2 librarySumit Garg
BL31 runs from SRAM which is a non-coherent memory on synquacer. So enable MMU with SRAM memory marked as Non-Cacheable and mark page tables kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables for Device address space. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Enable System level Generic timerSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Enable GICv3 supportSumit Garg
synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Enable CCN driver supportSumit Garg
synquacer has CCN-512 interconnect. So enable proper CCN driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Implement topology functionsSumit Garg
These functions describe the layout of the cores and clusters in order to support the PSCI framework. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Populate BL32 and BL33 entrypointsSumit Garg
As this platform supports direct entry to BL31 and no BL2, so populate BL32 and BL33 entrypoints with static memory load info. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Enable PL011 UART ConsoleSumit Garg
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Add platform core management helpersSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-21synquacer: Introduce basic platform supportSumit Garg
synquacer supports direct entry to BL31 without BL1 and BL2 as SCP firmware does similar work. So this patch adds BL31 stub APIs. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2018-06-12uniphier: fix CCI-500 connection for LD20Satoshi Ikawa
The slave ports of LD20 CCI-500 are connected as follows: S0: CA53 S1: CA72 Be careful because the slave interface is not arranged in the cluster number order (CA72: cluster 0, CA53: cluster 1). Root-caused-by: Tetsuya Yoshizaki <yoshizaki.tetsuya@socionext.com> Signed-off-by: Satoshi Ikawa <ikawa.satoshi@socionext.com>
2018-03-26plat: fix switch statements to comply with MISRA rulesJonathan Wright
Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7. Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
2018-02-06Merge pull request #1224 from masahir0y/gzipdavidcunado-arm
Support GZIP-compressed images for faster loading and verification
2018-02-02uniphier: add ULL to physical address literalsMasahiro Yamada
Looks like this is requirement in the pre-merge static analysis. misra_violation: [Required] MISRA C-2012 Rule 7.2 violation: Unsigned constants must be declared with U or u suffix. Adding ULL as requested. I used ULL() macros for BL*_{BASE,LIMIT} because they are referenced from linker scripts. Requested-by: David Cunado <david.cunado@arm.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-02-02uniphier: allocate xlat region of on-chip SRAM only when neededMasahiro Yamada
Currently, the xlat region of the on-chip SRAM is always allocated for all BL images. The access to the on-chip SRAM is necessary for loading images from a USB memory device (i.e. when updating firmware), so unneeded for the usual boot procedure. To avoid this waste, allocate the xlat region dynamically only for BL2, and only when it is necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-02-02uniphier: get back original BL31/32 location used before BL2-AT-EL3Masahiro Yamada
Commit 247fc0435191 ("uniphier: switch to BL2-AT-EL3 and remove BL1 support") accidentally changed the location of BL31 and BL32. The new memory map overlaps with the audio DSP images, also gives impact to OP-TEE. They are both out of control of ARM Trusted Firmware, so not easy to change. This commit restores the image layout that was originally used prior to the BL2-AT-EL3 migration. Reported-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-02-02uniphier: support GZIP-compressed imagesMasahiro Yamada
Allow to handle GZIP-compressed images by giving FIP_GZIP=1 from the command line. - Images are GZIP-compressed, then packed into FIP. If Trusted Board Boot is enabled, certificates are generated based on the compressed images. - GZIP decompressor is linked into BL2 to decompress images at run-time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-02-02uniphier: add a helper to get image_infoMasahiro Yamada
In the next commit, I will have more usecases to get struct image_info from image ID. It is better to make a helper function at a different layer. I do not need the current uniphier_image_descs_fixup() since the code is small enough to be squashed into the caller side. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-24uniphier: switch to BL2-AT-EL3 and remove BL1 supportMasahiro Yamada
UniPhier platform implements non-TF boot ROM. Prior to the BL2-AT-EL3 support, BL1 (worked as a pseudo ROM) was needed just for ensuring BL2 is entered at EL1-S. Now, this platform is able to avoid this waste. Enable the BL2_AT_EL3 option, and remove BL1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-24uniphier: set PROGRAMMABLE_RESET_ADDRESS to disable warm boot mailboxMasahiro Yamada
The warm boot mailbox code is compiled if PROGRAMMABLE_RESET_ADDRESS is disabled. The warm boot mailbox is useless for UniPhier SoC family because BL1 is not the first image. The UniPhier platform implements non-TF ROM, then BL1 works as a pseudo ROM, so it is never executed in the warm boot. The reset vector address is not actually programmable for UniPhier platform, but it should not hurt to enable PROGRAMMABLE_RESET_ADDRESS to disable the mailbox and remove pointless plat_get_my_entrypoint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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