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2017-06-28rockchip: enable A53's erratum 855873 for rk3399Caesar Wang
For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't support WriteEvict. and you will hit the condition L2ACTLR[3] with 0, as the Evict transactions should propagate to CCI-500 since it has snoop filters. Maybe this erratum applies to all Cortex-A53 cores so far, especially if RK3399's A53 is a r0p4. we should enable it to avoid data corruption, Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-06-14Unique names for defines in the CPU librariesVarun Wadekar
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-08rockchip: check wakeup cpu when resumeLin Huang
unlike rk3399 and rk3368, there are some rockchip 64bit SOC do not have CPUPD, and pmu_cpuson_entrypoint() is common function for rockchip platform, so we need to check wakeup cpu when resume. Change-Id: I6313e8a9d7c16b03e033414f0cb281646c2159ff Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-06-08rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspendLin Huang
with PMU_PERILP_PD_EN bit enable, the soc will shutdown cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con, spi, i2c, uart, saradc, tsadc when suspend, we have M0 code need to run when suspend in normal SRAM, so we need to take care of that. Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-06-08rockchip/rk3399: Move DRAM restore to PMUSRAMDerek Basehore
This moves the DRAM restore code to PMUSRAM. This is so that the voltage domain that contains the SRAM that it was stored in before may be turned off during system suspend. Change-Id: Id761181a30caadd12f1ce061d1034f3159a76d28 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip/rk3399: convert to for-loops to save code spaceDerek Basehore
This converts two functions to use for-loops. This saves a bit of space to help moving DRAM resume code to PMUSRAM. Change-Id: Ie6ca490cf50c2ec83335cf1845b337c3e8a47496 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip/rk3399: Remove unneeded if statementDerek Basehore
The removed if statement would make the same check that the for loop it is in does to break out of the for loop, so it doesn't make any sense to keep it there. Change-Id: I819c29f9182e6de1fc47e418aed15ad38e8f9fa9 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip/rk3399: Remove unneeded register setsDerek Basehore
This removes the mmio_... function calls to set the multicast bit for the PHY registers when overriding the write leveling values. These are not needed since multicast is set by default when calling the function, and it's also better not to leave the side effect of disabling multicast when exiting the function. Change-Id: I83e089a2a2d55268b3832f36724c3b2c4be81082 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip/rk3399: remove unneeded DDR restore functionDerek Basehore
This removes the phy_dll_bypass_set function as it is unneeded. The values that function sets are saved during suspend, so the proper values will be restored on resume. Change-Id: I17542206c56e639ce8cb6375233145167441d4e2 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip/rk3399: Save space for DRAM suspend dataDerek Basehore
This removes the space allocation for the unused PHY register space. For instance in PHY registers 0-127, only 0-90 are used, so don't save the 91-127 registers. This saves about 1.6KB of space. Change-Id: I0c9f6d9bed8f0c1f3b8b805dfb10cf0c06208919 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-06-08rockchip: add pmusram sectionLin Huang
the function pmu_cpuon_entrypoint() need to run in the pmusram, we just copy bin file to pmusram before, now we add pmusram section and link pmu_cpuon_entrypoint() to pmusram directly Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-06-08rockchip/rk3399: fix DRAM gate training issueLin Huang
The differential signal of DQS need keep low level before gate training. It need enable RPULL and disable PHY side ODT to ensure it when do gate training. But it can not access the PHY registers to do it when perform DFS.So the workaroud as below: It is ensure that the PHY's read gate is landing somewhere in the incoming DQS's pulses before it starts searching for pre-amble window. It need get the rddqs_delay_ps to calculate the start point of gate training for DFS. Change-Id: I79eabcf4ec9a9c8f4539f68a51f22afba49c72fe Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-05-15rockchip: rk3328: Add assert check in pmu.ctony.xie
Add assert() check for cpuson_flags[] and cpuson_entry_point[]. Change-Id: I971fe54c2baa3b4514a3979042341220f5e20901 Signed-off-by: tony.xie <tony.xie@rock-chips.com>
2017-05-10Use SPDX license identifiers for remaining filesdp-arm
Change-Id: I7f54f45db65f32481cc05e1bd2c9c683b756e19a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-10Merge pull request #918 from rockchip-linux/rk3328davidcunado-arm
rockchip: rk3328: support rk3328
2017-05-10Revert "rockchip: Remove unused rockchip_pd_pwr_down_wfi function"Antonio Nino Diaz
This reverts commit b6dcbf588af442fa87721dc707ff9e54d04ff504. This function wasn't used when it was removed, but it is needed to compile the new changes proposed for Rockchip platforms. Change-Id: Ia5bfe1f8398e08431f96923e2f059a83e5cb78d4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-10rockchip: rk3328: Add a missing paragraph for copyright notice.tony.xie
Change-Id: I78c7e304d3070f66e2ca3bf838c76ee6a2ae3430 Signed-off-by: tony.xie <tony.xie@rock-chips.com>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-04-25rockchip: rk3328: support rk3328tony.xie
rk3328 is a Quad-core soc and Cortex-a53 inside! This patch supports the following functions: 1、power up/off cpus 2、suspend/resume cpus 3、suspend/resume system 4、reset system 5、power off system Change-Id: I60687058d13912c6929293b06fed9c6bc72bdc84 Signed-off-by: tony.xie <tony.xie@rock-chips.com>
2017-04-07Merge pull request #892 from rockchip-linux/fixes-a-typodavidcunado-arm
rockchip/rk3399: the printf changed to tf_printf for console output
2017-04-07rockchip/rk3399: changed printf/tf_printf for console outputCaesar Wang
The printf() isn't used by the firmware itself, just by the tools under the ./tools/ folder. Then tf_printf will unconditionally print. Remove the unused print_dram_status_info() function. Change-Id: Ie699ccb54a5be9a2cbbd7b8d4193b57075a2f57a Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-04-05rockchip: Remove unused rockchip_pd_pwr_down_wfi functionPaul Kocialkowski
The rockchip_pd_pwr_down_wfi function is currently unused, which may trigger compiler warnings or errors. Remove it. Change-Id: I7e1b0ae092e8855528ac2065ecefc8bd45305f31 Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2017-03-20Move plat/common source file definitions to generic Makefilesdp-arm
These source file definitions should be defined in generic Makefiles so that all platforms can benefit. Ensure that the symbols are properly marked as weak so they can be overridden by platforms. NOTE: This change is a potential compatibility break for non-upstream platforms. Change-Id: I7b892efa9f2d6d216931360dc6c436e1d10cffed Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-03-03Merge pull request #854 from rockchip-linux/pm_platdavidcunado-arm
rockchip: plat_pm.c: Change callbacks implement for our SOCs.
2017-03-03rockchip: Change the callback implement of power domain for rk3368tony.xie
Change-Id: I6d39b4cac9b34b1f841e9bbddaf9c49785ba0c5e Signed-off-by: tony.xie <tony.xie@rock-chips.com>
2017-03-01rockchip: plat_pm.c: Change callbacks implement for our SOCs.tony.xie
Remove struct rockchip_pm_ops_cb and instead of using weak functions implement; in this way we want the codes look clear and simple; Change-Id: Ib9e8a5e932fdfc2b3e6a1ec502c40dfe720ac400 Signed-off-by: tony.xie <tony.xie@rock-chips.com>
2017-02-27Merge pull request #835 from rockchip-linux/rk3399-atf-cleanup-20170210davidcunado-arm
RK3399 ARM TF clean up 20170210
2017-02-24rockchip: rk3399: enable secure accessing for SRAMXing Zheng
Sorry to miss the security configuration for SRAM, if we don't support it, somebody may modify the comment of SRAM in the non-secure space. Let's fix this issue. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2017-02-24rockchip: rk3399: Use tFC value instead of tRFC valueDerek Basehore
This fixes code that set a tFC value in a register using the tRFC value instead. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: rk3399: Fix CAS latency settingDerek Basehore
The F1 CAS latency setting was not bit shifted, which resulted in setting the DRAM additive latency value instead. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: rk3399: disable training modules after DDR DFSXing Zheng
On resume, we use the DFS hardware to switch frequency index, followed by a full training sequence on that index. Leaving the DFS training modules enabled causes issues with the full training done at resume. We also only needs these enabled during a call to ddr_set_rate during runtime, so there's no issue disabling them at the end of ddr_set_rate. Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2017-02-24rockchip: rk3399: Move DQS drive strength setting to M0Derek Basehore
This moves the setting of the DQS drive strength to the M0 to minimize the impact on DDR transactions. We need to have the DQS drive strength changed for data training, which is triggered by the M0, but it also needs to be changed back when data training is finished. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: rk3399: Remove dram dfs optimizationDerek Basehore
This removes an optimization to not recalculate parameters if the frequency index being switched to hold the next frequency. This is because some registers do not have a copy per frequency index, so this optimization might be causing problems. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: rk3399: Save and restore RX_CAL_DQS valuesDerek Basehore
We were getting far off values on resume for the RX_CAL_DQS values. This saves and restores the values for suspend/resume until the root of the problem is figured out Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: Add MIN() and MAX() macros back to M0 codeJulius Werner
These macros were accidentally deleted in a previous cleanup. This slipped through because the code using them is currently unused, but that may change in the future. Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-02-24rockchip: Clean up M0 Makefile, clarify float-abiJulius Werner
This patch shuffles the M0 Makefile flags around a bit trying to make their purpose clearer and remove duplication. Since all three build steps (compiling, assembling, linking) actually call GCC, remove the misleading aliases $(AS) and $(LD) to avoid confusion that those tools might be called directly. Split flags into a common group that has meaning for all three steps and separate variables specific to each step. Remove -nostartfiles which is a strict subset of -nostdlib. Also add explicit parameters for -mfloat-abi=soft, -fomit-frame-pointer and -fno-common. If omitted these settings depend on the toolchain's built-in default and cause various problems if they resolve to unexpected values. Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-02-24rockchip: rk3399: Clean up and seprate secure parts from SoC codesXing Zheng
The goal is that make clear the secure and SoC codes. Now cleaning them will help secure code extensions for RK3399 in the future. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2017-02-24rockchip: rk3399: sperate the BL31 parameters for sharingXing Zheng
Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE and TZRAM_SIZE for DDR secure regions), we can split them and don't have to hardcode the range in two places. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2017-02-24rockchip: rk3399: configure the DDR secure region for BL31 imageXing Zheng
Move the BL31 loaded base address 0x10000 to 0x1000, and configure the the memory range 0~1MB is secure, the goal is that make sure the BL31 image will be not modified. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2017-02-24rockchip: Clean up header and referenced filesXing Zheng
So far, there are more and more features are supported on the RK3399, meanwhile, these features are increasingly being defined and intertwined. It's time to clean up and make them clearer. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2017-02-24rockchip: rk3399: Don't wait for vblank in M0 for ddrfreqDerek Basehore
This removes waiting for vblank on the M0 during ddrfreq transitions. That will now be done in the kernel to allow scheduling to be done on the CPU core that changes the ddr frequency. Waiting for vblank in the M0 would have the CPU core that waits on the M0 spin looping for up to 16ms (1 frame for the display). Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: rk3399: restore PMU_CRU_GATEDIS_CON0 value after ddr dvfsLin Huang
we will set PMU_CRU_GATEDIS_CON0 when idle port, it will enable all clock, for save power consumption, we need to restore old value when finish it. Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-02-24rockchip: rk3399: fix PMU_CRU_GATEDIS_CON0 setting errorLin Huang
As rk3399 TRM1.1 document show, when set PMU_CRU_GATEDIS_CON0/1 register, it need set the write_mask bit (bit16 ~ bit31), but as we test, it not need it. So need to correct the setting way, otherwise it will set wrong value to this register. Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-02-24FIXUP: rockchip: rk3399: fix the incorrect bit during m0_initXing Zheng
We found that the DUT will be hanged if we don't set the bit_1 of the PMUCRU_GATEDIS_CON0. But, from the TRM, there is weird that the bit_1 is set the clk_center1_gating_dis, not clk_pmum0_gating_dis. Is the TRM incorrect? We need to check it with the IC team and re-clean the commit message and explain it tomorrow. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2017-02-24rockchip: rk3399: improve the m0 enable flowLin Huang
This patch do following things: 1. Request hresetn_cm0s_pmu_req first then request poresetn_cm0s_pmu_req during M0 enable. 2. Do not diable M0 clock for ddr dvfs. 3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1 4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate to the M0 clock. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: rk3399: check vop status when we wait dma finish flagLin Huang
When vop is disabled and we read the vop register the system will hang, so check vop status when we wait for the DMA finish flag to avoid this sitiuation. This is done by checking for standby, DMA stop mode, and disabled window states. Any one of these will prevent the DMA finish flag from triggering. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: rk3399: add stopwatch functions to m0Lin Huang
There is system timer in m0, we can use it to implement a set of stopwatch functions for measuring timeouts. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0Lin Huang
The phy pll needs to get 2X frequency to the DDR, so set the pll_postdiv to 0. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: rk3399: enable CA training when do ddr dfsLin Huang
For ddr dfs stable, We need to enable ddr CA training when do ddr dfs. Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-02-24rockchip: rk3399: fix hang in ddr set rateDerek Basehore
This fixes a hang with setting the DRAM rate based on a race condition with the M0 which sets the DRAM rate. The AP can also starve the M0, so this also delays the AP reads to the DONE parameter for the M0. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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