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2017-02-24rockchip: rk3399: Enable per CS training at 666MHzDerek Basehore
This enables per CS training at 666MHz and above for ddrfreq per vendor recommendation. Since the threshold was used for latency was the same value, this also adds a new value for that. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: rk3399: add support for ddrfreq suspend/resumeDerek Basehore
This patch sets the frequency configuration of the next DRAM DFS index to the configuration of the current index. This does not perform a frequency transition. It just configures registers so the training on resume for both indices will be correct. Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2017-02-24rk3399: dram: use PMU M0 to do ddr frequency scalingXing Zheng
We used dcf do ddr frequency scaling, but we just include a dcf binary, it hard to maintain later, we have M0 compile flow in ATF, and M0 can also work for ddr frequency scaling, so let's use it. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2017-02-24rockchip/rk3399: Cleanup platform.mk fileDerek Basehore
This makes the file consistently use tabs instead of mixing in spaces. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2017-02-24rockchip: update the raw read/write APIs for M0Xing Zheng
Since the ATF project, we usually use the mmio_read_32 and mmio_write_32. And the mmio_write_32, the firse parameter is ADDR, the second is VALUE. In order to style consistency: 1/ rename readl/writel to mmio_read_32/mmio_write_32 2/ for keeping the same with mmio_write_32 in the ATF project, swap the order of the parameters for M0 mmio_write_32 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-02-24rk3399: dram: making phy into dll bypass mode at low frequencyDerek Basehore
when dram frequency below 260MHz, phy master dll may unlock, so let phy master dll working at dll bypass mode when frequency is below 260MHz. Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-02-24rockchip: rk3399: dram: remove dram_init and dts_timing_receive functionDerek Basehore
we can reuse the dram config from loader, so we can remove dram_init() and dts_timing_receive() funciton in dram.c, add the dram_set_odt_pd() function to get the odt and auto power down parameter from kernel. This also removes the dcf_code_init function to allow the system to actually boot. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
2017-02-06Replace some memset call by zeromemDouglas Raillard
Replace all use of memset by zeromem when zeroing moderately-sized structure by applying the following transformation: memset(x, 0, sizeof(x)) => zeromem(x, sizeof(x)) As the Trusted Firmware is compiled with -ffreestanding, it forbids the compiler from using __builtin_memset and forces it to generate calls to the slow memset implementation. Zeromem is a near drop in replacement for this use case, with a more efficient implementation on both AArch32 and AArch64. Change-Id: Ia7f3a90e888b96d056881be09f0b4d65b41aa79e Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-01-24Use #ifdef for IMAGE_BL* instead of #ifMasahiro Yamada
One nasty part of ATF is some of boolean macros are always defined as 1 or 0, and the rest of them are only defined under certain conditions. For the former group, "#if FOO" or "#if !FOO" must be used because "#ifdef FOO" is always true. (Options passed by $(call add_define,) are the cases.) For the latter, "#ifdef FOO" or "#ifndef FOO" should be used because checking the value of an undefined macro is strange. Here, IMAGE_BL* is handled by make_helpers/build_macro.mk like follows: $(eval IMAGE := IMAGE_BL$(call uppercase,$(3))) $(OBJ): $(2) @echo " CC $$<" $$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -D$(IMAGE) -c $$< -o $$@ This means, IMAGE_BL* is defined when building the corresponding image, but *undefined* for the other images. So, IMAGE_BL* belongs to the latter group where we should use #ifdef or #ifndef. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-18Merge pull request #801 from masahir0y/cleanupdavidcunado-arm
Macro cleanups
2017-01-18Move BL_COHERENT_RAM_BASE/END defines to common_def.hMasahiro Yamada
We have lots of duplicated defines (and comment blocks too). Move them to include/plat/common/common_def.h. While we are here, suffix the end address with _END instead of _LIMIT. The _END is a better fit to indicate the linker-derived real end address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-13utils: move BIT(n) macro to utils.hMasahiro Yamada
We are duplicating this macro define, and it is useful enough to be placed in the common place. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-04rockchip: Build m0 firmware without standard librariesPatrick Georgi
Depending on the compiler used, it might try to link in libc even though it's not required. Stop it from doing that. Signed-off-by: Patrick Georgi <pgeorgi@google.com>
2016-12-14Fix incorrect copyright noticesAntonio Nino Diaz
Some files have incorrect copyright notices, this patch fixes all files with deviations from the standard notice. Change-Id: I66b73e78a50a235acb55f1e2ec2052a42c0570d2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2016-11-24rk3399: Add CFI debug information to SRAM functionsSoren Brinkmann
Commit b91d935feebdf2c3edef19949023645b6cb34b20 ("Add CFI debug frame information for ASM functions") modifies the assembly macros 'func' and 'endfunc' to include CFI debug frame information. The rockchip platform uses a custom version of the 'func' macro with the common 'endfunc' macro. The custom macro wasn't updated in b91d935feebdf2c3edef19949023645b6cb34b20 resulting in the following build error: plat/rockchip/rk3399/drivers/pmu/plat_pmu_macros.S: Assembler messages: plat/rockchip/rk3399/drivers/pmu/plat_pmu_macros.S:155: Error: .cfi_endproc without corresponding .cfi_startproc Makefile:532: recipe for target 'build/rk3399/release/bl31/plat_helpers.o' failed make: *** [build/rk3399/release/bl31/plat_helpers.o] Error 1 Fixing this by updating the sram_func macro in the rk3399 port. Fixes: b91d935feebdf2c3edef19949023645b6cb34b20 ("Add CFI debug frame information for ASM functions") Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-11-08Merge pull request #752 from rockchip-linux/rk3399/fixes-s2r-1107danh-arm
rk3399: fixes and updates for s2r
2016-11-08Merge pull request #750 from jwerner-chromium/m0_builddanh-arm
RK3399 M0 build system improvements
2016-11-07rockchip: remove no needed code for rk3399Caesar Wang
We have do something for clocks gate. Fox example as the below: susped: clk_gate_con_save(); clk_gate_con_disable(); resume: clk_gate_con_restore(); -- SO, add the plls_suspend_prepare() and plls_resume_finish() are not necessary to S2R, that will save S2R time if remove them. BRANCH=none BUG=chrome-os-partner:58870,chrome-os-partner:55934 TEST=build kevin, two dogfooders with suspend_stress_test passing 3000 cycles and still going on. Change-Id: Icfbabc0b3ea8d2b5108d4f3de99a803b6d459669 Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-11-07rockchip: disable watchdog during suspendCaesar Wang
The CA53 and CM0 WDT clock gating in rk3399 SGRF, and ATF is in charge of it because the kernel can't touch SGRF. Basically the WDT didn't stop at suspend time, it just switched from the 24M to the 32k clock. That meant that the WDT would fire if you slept for long enough. In other word, the watchdog timer over count will increase to 750 (24*1000/32) times. The RK3399 HW watchdog interval is 21 seconds. When machine enters the suspend, the watchdog will reset the system after 35.7 (750/21) hours. BUG=chrome-os-partner:59257 TEST=daisydog checked and set value, powerd_dbus_suspend to verify. Change-Id: I88bb2a05b7d67d5ffd292f9d05d033ae9a6a3593 Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-11-03rockchip: Add proper dependency tracking to M0 MakefileJulius Werner
This patch adds dependency rule generation and inclusion to the M0 Makefile, so that M0 objects will get correctly remade with an incremental build if a header file they included changed. Change-Id: I2067bd9fd4d9dad3e77a09cbf09c7b4db3c1eda5 Signed-off-by: Julius Werner <jwerner@chromium.org>
2016-11-03rockchip: Clean up parent directory creation for M0Julius Werner
The dependencies in the M0 Makefile are not correctly laid out, which may lead to errors with make -j if the binary target gets evaluated before the target that creates the directory. In addition, the M0 Makefile just calls mkdir without using the platform-independent macros from the main ARM TF build system. This patch fixes those issues, removes some unused (and broken) M0 build targets and merges the two M0 output directories into one (since there's no real point splitting it up and it creates more hassle). Change-Id: Ia5002479cf9c57fea7aefa8ca88e373df3a51f61 Signed-off-by: Julius Werner <jwerner@chromium.org>
2016-10-27rockchip: close the PD center logic during suspendCaesar Wang
The RK3399 supports close the center logic enter power mode, so we can close PD_CENTER to save more power during suspend. Therefore, we need to support save/restore the DDR PHY and controller registers during suspend/resume. Also, need CL (http://crosreview.com/397399) to check disabling center logic. Change-Id: I288defd8e9caa3846d9fa663a33e4d51df1aaa5d Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-10-27rockchip: add support save/restore configuration for DDR during enter S3Caesar Wang
This patch intend to support save the registers of the DDR controller and PHY before suspend, and restore them after resume. Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-10-27rockchip: Change dmc register accesses to ATF style for rk3399Caesar Wang
This changes the style of dmc register accesses to be a read/write on a base address plus a register offset instead of reinterpretting a base address as a struct and accessing members within that struct. Change-Id: Iead097cd6afdb830d8bc193608cd39d01ce5a6bc Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-10-27rockchip: Break out common dram code for rk3399Caesar Wang
This renames dram.c and dram.h to dfs.c and dfs.h respectively. This is to make room for common functionality between frequency scaling and suspend code for the DRAM in a pair of common files named dram.c and dram.h. It also removes a duplicate enum definition from dram_spec_timing.h Change-Id: Ibfa1041f8781401f9d27901fe8c61862bcb05562 Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-10-27rockchip: move pmu registers into another header for rk3399Caesar Wang
This moves the PMU register definitions into another file for use in later patches. Change-Id: I8b5f1e7938b63ada6a743cf9661c3e474e96e4e4 Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-10-26Merge pull request #724 from rockchip-linux/support-rk3399-sdramdavidcunado-arm
rockchip: optimize the link mechanism for SRAM code
2016-10-26Merge pull request #739 from rockchip-linux/fixes-latencydavidcunado-arm
rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5
2016-10-25rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5Caesar Wang
The default value of L2CTLR_DATA_RAM_LATENCY is 2, depends to the test result on rk3399, the A72 will need lower voltage for high frequency if it's set to be 5, and almost no effect on performance. Change-Id: I99a6a43edcc0c58f7775c10f4b85669dc3eff66d Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-10-25rockchip: clear the power mode status via M0Caesar Wang
Due to the PMU design, the PMU may not clear the WAKEUP bit after wakeup, therefore, the state machine at the power mode may enter the infinite loop during WFI. There is a solution that we can use the M0 to monitor the WAKEUP bit and clear it during power mode, then the state machine will be recovered immediately. Then, the DUT can exit the WFI normally. Change-Id: I303628553b728c214bf2d436bd3122032b5e669c Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-10-25rockchip: add M0 source code and build system for RK3399Caesar Wang
This CL supports add M0 source code to built into the bl31.bin, the goal is that we can load the M0 code binary into SRAM and execute it. We need the M0 help us to clean the power_mode_en bit during the AP PMU enter the state machine with interrupt, and avoid to the AP can not exit the loop forever. Change-Id: I844582c54a1f0d44ca41290d44618df58679f341 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-10-25rockchip: optimize the link mechanism for SRAM codeCaesar Wang
Add the common extra.ld.S and customized rk3399.ld.S to extend to more features for different platforms. For example, we can add SRAM section and specific address to load there if we need it, and the common bl31.ld.S not need to be modified. Therefore, we can remove the unused codes which copying explicitly from the function pmusram_prepare(). It looks like more clear. Change-Id: Ibffa2da5e8e3d1d2fca80085ebb296ceb967fce8 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-10-21rockchip: fixes the wrong CLKSEL_CON count for CRUCaesar Wang
The CRU_CLKSEL_COUNT value is 108, not 0x108. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Change-Id: Ib9db066b8b3ecafcee7f645dd5633b55a808e3d7
2016-09-29rockchip: fixes the clock select and divide register for rk3399Caesar Wang
As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON register. As the CRU_CLKSEL_CON96～107 high 16-bit isn't write mask and the CRU_CLKSEL_CON offset is 0x100,not 0x80. Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529
2016-09-14Merge pull request #700 from rockchip-linux/fixes-typo-and-warningsdavidcunado-arm
rockchip: Fixes typo and warnings
2016-09-13rockchip: fixes the gic panic for rk3399 resumeCaesar Wang
We make sure the resuming of gic need to be enabled. Otherwise, The resume will hit the below panic. ... [ 24.230541] CPU0: update max cpu_capacity 451 [ 24.236029] CPU5: update max cpu_capacity 1024 [ 24.236046] CPU4: shutdown [ 24.243205] psci: CPU4 killed. [ 24.258730] CPU5: shutdown [ 24.261472] psci: CPU5 killed. [ 24.270417] GIC: unable to set SRE (disabled at EL2), panic ahead [ 24.270417] cat[7801]: undefined instruction: pc=ffffffc0004e65d0 [ 24.270417] Code: b0003940 91274400 97f871af d2801e00 (d5184600) [ 24.270417] Internal error: Oops - undefined instruction: 0 [#1] PREEMPT Change-Id: Ie9542c8d5768ba0accfa073453da8bfe06d4f921
2016-09-10rockchip: fixes some typoCaesar Wang
As the checkpatch reports the warning or error. plat/rockchip/common/plat_pm.c:96: ERROR: do not set execute permissions for source files plat/rockchip/rk3399/drivers/pmu/pmu.c:294: ERROR: do not set execute permissions for source files plat/rockchip/common/plat_pm.c:286: WARNING: line over 80 characters plat/rockchip/common/plat_pm.c:287: WARNING: line over 80 characters Change-Id: Ib347da21c56551c31df3f90f03777b13c75d5c26
2016-09-10rockchip: SIP call use 32 bit return value for rk3399Caesar Wang
for compatible 32bit and 64bit, we use 0x82xxxxxx as function ID, we modify SIP call function return value to 32 bit. Change-Id: Ib99b03a9ea423853aaa296dcc634ee82c622a552
2016-09-10rockchip: set gpio2 ~ gpio4 to input and pull none modeCaesar Wang
For save power cosumption, if gpio power supply shut down, we need to set gpio2 ~ gpio4 to input and HiZ status when suspend, and recovery they status when rusume. we do it base on apio pass from loader. Change-Id: I59fd2395e5e37e63425472a39f519822c9197e4c
2016-09-10rockchip: support disable/enable specific gpio when suspend/resumeCaesar Wang
some specific board need to disable/enable specific gpio when suspend/resume, so we add this function, bootloader can pass the specific gpio, and we can handle these gpios in bl31 suspend/resuem function. Change-Id: I373b03ef9202ee4a05a2b9caacdfa01b47ee2177
2016-09-10rockchip/rk3399: improve gpio driver and support get pull mode functionCaesar Wang
We may need gpio pull mode later, so add this function. Besides fix a set pull mode bug, and save gpio clock gate, when operate the gpio, we will enable gpio clock, when finish gpio operate, restore gpio clock gate status. Change-Id: Ia1d602804f571a17f5ddc499908663b968b02974
2016-09-08rockchip: fix the scu idle for rk3399Tony Xie
As rk3399 reported the d8/octane scores drop 10% with cpu idle. The root cause is thc cpu cluster enter the slow mode. We don't need switch the clock to 24MHz if cpu cluster enter the retention mode. In order to improve performance, it just needs for cluster enter powering off mode. Also, we shouldn't do anything for hlvl if the system is off. Change-Id: I2a02962a01343abd0cba47ed63192c1cdf88b119
2016-08-26Merge pull request #691 from rockchip-linux/fixes-suspend/resume-bugsdavidcunado-arm
Fixes suspend/resume bugs
2016-08-25Merge pull request #684 from rockchip-linux/add-sdram-for-rk3399davidcunado-arm
rockchip: add dram driver for rk3399
2016-08-25rockchip: handle some interrupt before enter power mode for rk3399Caesar Wang
For the PMU design, we don't expect to get the interrupts before enter the power mode. Since that will cause the confusion for the state machine in the power mode. Change-Id: Id8dee79ae617a66271b5caf92caf35f520f45099
2016-08-25rockchip: remove the unused code for rk3399Caesar Wang
Change-Id: I986d64df9dc62354d50ccea0468b90f090a44160 Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2016-08-25rockchip: on rk3399 enable Schmitt trigger on 32 kHz clockCaesar Wang
If we don't enable the Schmitt trigger on the 32 kHz clock then systems won't always resume from suspend properly. Presumably anything else in the system that relies on the 32 kHz clock also will have problems without the Schmitt trigger enabled. Enable it always since having the 32 kHz clock on GPIO0_A0 isn't exactly an optional feature, so all boards using rk3399 will need this. Change-Id: Idc18c6cd1adc5be5f60efd9cb805d83d5cd40129
2016-08-25rockchip: enable or disable auto power down base on frequencyCaesar Wang
add auto_pd_dis_freq parameter, we can pass a frequency from kernel to disable or enable ddr auto power down function. Change-Id: Ie30914701336c59047c380381c6b75dd76a89562
2016-08-25rockchip: rk3399: add dram driverCaesar Wang
add dram driver, and kernel can through sip function talk to bl31 to do ddr frequency scaling. and ddr auto powerdown. Change-Id: I0d0f2869aed95e336c6e23ba96a9310985c84840
2016-08-25rockchip: on rk3399 init the PMU counts at boot; set 24M/32k properlyCaesar Wang
In a previous change we mistakenly thought that PMU_24M_EN_CFG directly controlled whether the PMU counts ran off the 32k vs. 24M clock. Apparently that's not true. Real logic is now documented in code. Also in the previous change we mistaknely though that PMU_24M_EN_CFG was normally supposed to be 1 and we should "restore" it at resume time. This is a terrible idea and made the system totally unreliable after resume. Apparently PMU_24M_EN_CFG should always be 0 with all the current code and settings. Let's fix the above two problems. While we're changing all of this, let's also: 1. Init at boot time. Many of these counts are used when the system is running normally. We want the behavior at boot to match the behavior after suspend/resume. 2. Init CPU counts to be 1 us. Although old code was trying to set this to 1 ms (1000x slower) at suspend/resume time, we've been testing the kernel with 1 us for a long time now. That's because the kernel (at boot time) set these values to 24. Let's keep at 24 until we know that's wrong. 3. Init GPU counts to be 1 us. Old code wasn't touching the GPU, but as documented in comments it makes sense to init here. Do it. 4. Document the crap out of this code, since the SoC's behavior is confusing and poorly documented in the TRM. 5. Increase some stabilization times to 30 ms (from 3 ms). It's unclear that a full 30 ms is needed, but let's be safe for now. This also inits the counts for the GPU. (Thanks to Doug's patch that come from https://crosreview.com/372381) Change-Id: Id1bc159a5a99916aeab043895e5c4585c4adab22
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