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2018-03-07Merge pull request #1239 from arve-android/trusty-fixesdavidcunado-arm
Trusty fixes
2018-02-21tegra/trusty: Setup tegra specific trusty args in platform codeArve Hjønnevåg
Fixes tegra build with SPD=trusty. Not tested. Change-Id: I851a2b00b8b1cc65112b6088980a811d8eda1a99
2018-02-17tegra: Fix mmap_region_t struct mismatchAndreas Färber
Commit fdb1964c34968921379d3592e7ac6e9a685dbab1 ("xlat: Introduce MAP_REGION2() macro") added a granularity field to mmap_region_t. Tegra platforms were using the v2 xlat_tables implementation in common/tegra_common.mk, but v1 xlat_tables.h headers in soc/*/plat_setup.c where arrays are being defined. This caused the next physical address to be read as granularity, causing EINVAL error and triggering an assert. Consistently use xlat_tables_v2.h header to avoid this. Fixes ARM-software/tf-issues#548. Signed-off-by: Andreas Färber <afaerber@suse.de>
2017-11-30Do not enable SVE on pre-v8.2 platformsDavid Cunado
Pre-v8.2 platforms such as the Juno platform does not have the Scalable Vector Extensions implemented and so the build option ENABLE_SVE is set to zero. This has a minor performance improvement with no functional impact. Change-Id: Ib072735db7a0247406f8b60e325b7e28b1e04ad1 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-09-21Fix type of `unsigned long` constantsAntonio Nino Diaz
The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in AArch64. This is inconsistent and that's why we avoid using it as per the Coding Guidelines. This patch changes all `UL` occurrences to `U` or `ULL` depending on the context so that the size of the constant is clear. This problem affected the macro `BIT(nr)`. As long as this macro is used to fill fields of registers, that's not a problem, since all registers are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the macro is used to fill the fields of a 64-bit integer, it won't be able to set the upper 32 bits in AArch32. By changing the type of this macro to `unsigned long long` the behaviour is always the same regardless of the architecture, as this type is 64-bit wide in both cases. Some Tegra platform files have been modified by this patch. Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-08-29Tegra: Rename CORTEX_A57_ACTLR_EL1 to *CPUACTLR*Eleanor Bonnici
CORTEX_A57_ACTLR_EL1 macro refers to the CPUACTLR_EL1 register. Since ACTLR_EL1 is a different register (not implemented in Cortex-A57) this patch renames this macro for clarity. Change-Id: I94d7d564cd2423ae032bbdd59a99d2dc535cdff6 Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
2017-08-15Add new alignment parameter to func assembler macroJulius Werner
Assembler programmers are used to being able to define functions with a specific aligment with a pattern like this: .align X myfunction: However, this pattern is subtly broken when instead of a direct label like 'myfunction:', you use the 'func myfunction' macro that's standard in Trusted Firmware. Since the func macro declares a new section for the function, the .align directive written above it actually applies to the *previous* section in the assembly file, and the function it was supposed to apply to is linked with default alignment. An extreme case can be seen in Rockchip's plat_helpers.S which contains this code: [...] endfunc plat_crash_console_putc .align 16 func platform_cpu_warmboot [...] This assembles into the following plat_helpers.o: Sections: Idx Name Size [...] Algn 9 .text.plat_crash_console_putc 00010000 [...] 2**16 10 .text.platform_cpu_warmboot 00000080 [...] 2**3 As can be seen, the *previous* function actually got the alignment constraint, and it is also 64KB big even though it contains only two instructions, because the .align directive at the end of its section forces the assembler to insert a giant sled of NOPs. The function we actually wanted to align has the default constraint. This code only works at all because the linker just happens to put the two functions right behind each other when linking the final image, and since the end of plat_crash_console_putc is aligned the start of platform_cpu_warmboot will also be. But it still wastes almost 64KB of image space unnecessarily, and it will break under certain circumstances (e.g. if the plat_crash_console_putc function becomes unused and its section gets garbage-collected out). There's no real way to fix this with the existing func macro. Code like func myfunc .align X happens to do the right thing, but is still not really correct code (because the function label is inserted before the .align directive, so the assembler is technically allowed to insert padding at the beginning of the function which would then get executed as instructions if the function was called). Therefore, this patch adds a new parameter with a default value to the func macro that allows overriding its alignment. Also fix up all existing instances of this dangerous antipattern. Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10 Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-07-31Tegra: implement the early suspend handlerVarun Wadekar
This patch implements the early suspend handler for Tegra SoCs. This handler is empty for now and the actual support for a particular platform would be added later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-07-14Fix order of remaining platform #includesIsla Mitchell
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-06-23Fix Tegra CFLAGS usageDouglas Raillard
Use TF_CFLAGS instead of CFLAGS, to allow CFLAGS to be overriden from the make command line. Change-Id: I3e5726c04bcd0176f232581b8be2c94413374ac7 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-14Tegra186: mce: fix MISRA defectsAnthony Zhou
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] * Added parentheses [Rule 12.1] * Voided non C-library functions whose return types are not used [Rule 17.7] Change-Id: I91404edec2e2194b1ce2672d2a3fc6a1f5bf41f1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: delay_timer: fix MISRA defectsAnthony Zhou
Main fixes: * Include header file for function declarations [Rule 8.4] * Move global object into function [Rule 8.9] Change-Id: I1bc9f3f0ebd4ffc0b8444ac856cd97b0cb56bda4 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2017-06-14Tegra: gic: fix MISRA defectsVarun Wadekar
Main fixes: * Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Fixed assert/if statements conditions to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Convert macros form headers to unsigned ints Change-Id: I8051cc16499cece2039c9751bd347645f40f0901 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: fiq_glue: fix MISRA defectsAnthony Zhou
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Convert object type to match the type of function parameters [Rule 10.3] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses[Rule 20.7] Change-Id: I5cf83caafcc1650b545ca731bf3eb8f0bfeb362b Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2017-06-14Tegra: pmc: fix defects flagged during MISRA analysisAnthony Zhou
Main fixes: * Fixed if/while statement conditional to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if/for/while statements in order to make them compound [Rule 15.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Change-Id: Ic72b248aeede6cf18bf85051188ea7b8fd8ae829 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2017-06-14Tegra: memctrl: check GPU reset state from common placeVarun Wadekar
This patch moves the GPU reset state check, during VideoMem resize, to the common SiP handler, to reduce code duplication. Change-Id: I3818c5f104b809da83dc2a61d6a8149606f81c13 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: memctrl_v2: fix software logic to check "flush complete"Varun Wadekar
This patch fixes the logic to check if the command written to the MC_CLIENT_HOTRESET_CTRLx registers, was accepted by the hardware module. Change-Id: If94fff9424555cb4688042eda17b4b20f4eb399a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: add explicit casts for integer macrosVarun Wadekar
This patch adds explicit casts (U(x)) to integers in the tegra_def.h headers, to make them compatible with whatever operation they're used in [MISRA-C Rule 10.1] Change-Id: Ic5fc611aad986a2c6e6e6f625e0753ab9b69eb02 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Unique names for defines in the CPU librariesVarun Wadekar
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: enable 'signed-comparison' compilation warning/errorsVarun Wadekar
This patch enables the 'sign-compare' flag, to enable warning/errors for comparisons between signed/unsigned variables. The warning has been enabled for all the Tegra platforms, to start with. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-08tegra: Fix build errorsSoren Brinkmann
The 'impl' variable is guarded by the symbol DEBUG, but used in an INFO level print statement. INFO is defined based on LOG_LEVEL. Hence, builds would fail when - DEBUG=0 && LOG_LEVEL>=LOG_LEVEL_INFO with a variable used but not defined - DEBUG=1 && LOG_LEVEL<LOG_LEVEL_INFO with a variable defined but not used Fixing this by guarding impl with the same condition that guards INFO. Fixes ARM-software/tf-issues#490 Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2017-05-12Tegra: Break circular dependency in platform header filesSandrine Bailleux
For SoCs T132 and T210, the header file 'platform_def.h' used to include 'tegra_def.h' and vice versa. This patch breaks this circular dependency by making 'tegra_def.h' independent. Change-Id: I45a00a84e6ab8b93d5e9242a9ff65f03e9102a96 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-01Tegra210: implement 'get_target_pwr_state' handlerVarun Wadekar
This patch implements the handler to calculate the cluster and system power states for the Tegra210 SoC. The power states returned by this handler are used by the PSCI library to decide cache maintenance operations - cluster v cpu. Change-Id: I93e4139d4cd8a086b51f328e9a76e91428ebcdab Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra: fix the NS DRAM address calculation logicVarun Wadekar
This patch fixes the logic used to calculate the end of NS memory aperture. The functions allows zero sized NS apertures as that is a valid requirement for some use cases. e.g. VPR resize. Change-Id: Ie966e0ea2f9c6888d21c38e734003704094b3720 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra: memctrl_v2: zero out NS Video memory carveout regionVarun Wadekar
The video memory carveout has to be re-sized depending on the Video content. This requires the NS world to send us new base/size values. Before setting up the new region, we must zero out the previous memory region, so that the video frames are not leaked to the outside world. This patch adds the logic to zero out the previous memory carveout region. Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra186: calculate proper power state for cluster/system power downVarun Wadekar
Earlier, we were setting "System Suspend" as the power state for all system states. This caused incorrect system state during a cluster power down. This patch fixes this anomaly and sets the correct power state during a cluster/system power down. Change-Id: Ibd002930e0ae103e381e0a19670c3c4d057e7cb7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra186: mce: max retries for ARI requestsSteven Kao
This patch adds max retries for all ARI requests and asserts if the ARI request is still busy. Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra: memmap Tegra micro-seconds timer controllerSteven Kao
This patch adds the Tegra micro-seconds controller to the memory map. This allows us to use the delay_timer functionality. Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra: early init the delay timerSteven Kao
This patch moves the platform delay timer init to early BL31 platform setup, so that platforms can use the udelay/mdelay routines in the early init code. Change-Id: I6fe20b76176ea22589539c180c5b6f9d09eda8de Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-26Tegra: Control inclusion of helper code used for assertsAntonio Nino Diaz
One assert depends on code that is conditionally compiled based on the DEBUG define. This patch modifies the conditional inclusion of such code so that it is based on the ENABLE_ASSERTIONS build option. Change-Id: Ic5659a3db8632593b9d2e83dac6d30afd87c131d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-26Tegra: smmu: enable asserts by defaultVarun Wadekar
This patch enables the assert in the context save routine by default, for all flavours of the build. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-26Tegra: enable 'ENABLE_ASSERTIONS' for all buildsVarun Wadekar
This patch changes the platform Makefile to set `ENABLE_ASSERTIONS` to 1 instead of the deprecated option `ASM_ASSERTION`. This also pulls in C assertions in release mode. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-26Tegra: group platform settings togetherVarun Wadekar
This patch groups all the platform configuration macros into the common platform.mk makefile. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-21Merge pull request #912 from vwadekar/tegra-smmu-ctx-save-robustdavidcunado-arm
Tegra: smmu: make the context save sequence robust
2017-04-21Merge pull request #902 from vwadekar/tegra186-sip-mce-callsdavidcunado-arm
Tegra186: Support AARCH32/64 encoding for MCE calls
2017-04-20Tegra: smmu: make the context save sequence robustVarun Wadekar
This patch sanity checks the SMMU context created by the platform code. The first entry contains the size of the array; which the driver now verifies before moving on with the save. This patch also fixes an error in the calculation of the size of the context that gets copied to TZDRAM. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-19Tegra: smmu: fix the size used to save contextVarun Wadekar
This patch fixes the size used to save the context, when the device enters System Suspend. Reported by: David Cunado Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-17Tegra186: Support AARCH32/64 encoding for MCE callsVarun Wadekar
On Tegra systems, there are multiple software components that require to interact with MCE. The components can either be 32-bit or 64-bit payloads. This patch supports MCE SMC functions ID for AARCH32 and AARCH64 architectures to support such clients. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-16Merge pull request #899 from vwadekar/tegra186-platform-support-v6davidcunado-arm
Tegra186 platform support v6
2017-04-14Merge pull request #897 from vwadekar/memctrl-v1-xlat-table-v2davidcunado-arm
Tegra: memctrl_v1: enable 'xlat_table_v2' library
2017-04-13Tegra: fix trivial misra issuesAnthony Zhou
Not having U or ULL as a suffix for these enums causes a lot of unnecessary MISRA issues. This patch adds U or ULL suffix to these common enums to reduce number of MISRA issues. Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra: no need to re-init the same consoleVarun Wadekar
This patch stops initialising the same UART console, as a "crash" console. The normal and the crash consoles use the same UART port and hence the crash console init function now only checks if the console is ready to be used. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra: Add support for fake system suspendVignesh Radhakrishnan
This patch adds support for fake system suspend (SC7). This is a debug mode, to ensure that a different code path is executed for cases like pre-silicon development, where a full-fledged SC7 is not possible in early stages. This particular patch ensures that, if fake system suspend is enabled (denoted by tegra_fake_system_suspend variable having a non-zero value), instead of calling WFI, a request for a warm reset is made for starting the SC7 exit procedure. This ensures that the code path of kernel->ATF and back to kernel is executed without depending on other components involved in SC7 code path. Additionally, this patch also adds support for SMC call from kernel, enabling fake system suspend mode. Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra: memctrl_v2: restore MC_TXN_OVERRIDE settingsVarun Wadekar
This patch restores the MC_TXN_OVERRIDE settings when we exit from System Suspend. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra: memctrl_v1: disable AHB redirection after cold bootVarun Wadekar
During boot, USB3 and flash media (SDMMC/SATA) devices need access to IRAM. Because these clients connect to the MC and do not have a direct path to the IRAM, the MC implements AHB redirection during boot to allow path to IRAM. In this mode, accesses to a programmed memory address aperture are directed to the AHB bus, allowing access to the IRAM. The AHB aperture is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are initialized to disable this aperture. Once bootup is complete, we must program IRAM base/top, thus disabling access to IRAM. This patch provides functionality to disable this access. The tegra port calls this new function before jumping to the non-secure world during cold boot. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra: platform: support Tegra186 chip idVarun Wadekar
This patch adds support to read the chip id and identify if the current platform is Tegra186. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra: memctrl_v2: MC transaction overrides for newer chipsPritesh Raithatha
This patch programs MC transaction overrides settings using mc_txn_override_cfgs array for all Tegra chips beyond Tegra186 rev. A01 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra186: mce: Avoid implementation-defined bitfield typesStephen Warren
GCC version 4.8 (and presumably earlier) warn when non-standard types are used for bitfield definitions when -pedantic is enabled. This prevents TF from being built with such toolchains, since -Werror -pedantic options are used. gcc-4.9 removed this warning; -pedantic is intended to cause gcc to emit a warning in all cases required by the standard, but the standard does not require a warning in this case. See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57773 Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-04-13Tegra: smmu: support for multiple devicesPritesh Raithatha
This patch adds flexibility to the code to initialise multiple SMMU devices. The base address macro name has been changed to make it explicit that we support multiple SMMUs. Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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