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2017-06-14Tegra186: mce: fix MISRA defectsAnthony Zhou
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] * Added parentheses [Rule 12.1] * Voided non C-library functions whose return types are not used [Rule 17.7] Change-Id: I91404edec2e2194b1ce2672d2a3fc6a1f5bf41f1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Unique names for defines in the CPU librariesVarun Wadekar
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: enable 'signed-comparison' compilation warning/errorsVarun Wadekar
This patch enables the 'sign-compare' flag, to enable warning/errors for comparisons between signed/unsigned variables. The warning has been enabled for all the Tegra platforms, to start with. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-01Tegra210: implement 'get_target_pwr_state' handlerVarun Wadekar
This patch implements the handler to calculate the cluster and system power states for the Tegra210 SoC. The power states returned by this handler are used by the PSCI library to decide cache maintenance operations - cluster v cpu. Change-Id: I93e4139d4cd8a086b51f328e9a76e91428ebcdab Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra186: calculate proper power state for cluster/system power downVarun Wadekar
Earlier, we were setting "System Suspend" as the power state for all system states. This caused incorrect system state during a cluster power down. This patch fixes this anomaly and sets the correct power state during a cluster/system power down. Change-Id: Ibd002930e0ae103e381e0a19670c3c4d057e7cb7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra186: mce: max retries for ARI requestsSteven Kao
This patch adds max retries for all ARI requests and asserts if the ARI request is still busy. Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra: memmap Tegra micro-seconds timer controllerSteven Kao
This patch adds the Tegra micro-seconds controller to the memory map. This allows us to use the delay_timer functionality. Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-26Tegra: Control inclusion of helper code used for assertsAntonio Nino Diaz
One assert depends on code that is conditionally compiled based on the DEBUG define. This patch modifies the conditional inclusion of such code so that it is based on the ENABLE_ASSERTIONS build option. Change-Id: Ic5659a3db8632593b9d2e83dac6d30afd87c131d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-21Merge pull request #912 from vwadekar/tegra-smmu-ctx-save-robustdavidcunado-arm
Tegra: smmu: make the context save sequence robust
2017-04-20Tegra: smmu: make the context save sequence robustVarun Wadekar
This patch sanity checks the SMMU context created by the platform code. The first entry contains the size of the array; which the driver now verifies before moving on with the save. This patch also fixes an error in the calculation of the size of the context that gets copied to TZDRAM. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-17Tegra186: Support AARCH32/64 encoding for MCE callsVarun Wadekar
On Tegra systems, there are multiple software components that require to interact with MCE. The components can either be 32-bit or 64-bit payloads. This patch supports MCE SMC functions ID for AARCH32 and AARCH64 architectures to support such clients. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra: fix trivial misra issuesAnthony Zhou
Not having U or ULL as a suffix for these enums causes a lot of unnecessary MISRA issues. This patch adds U or ULL suffix to these common enums to reduce number of MISRA issues. Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra186: mce: Avoid implementation-defined bitfield typesStephen Warren
GCC version 4.8 (and presumably earlier) warn when non-standard types are used for bitfield definitions when -pedantic is enabled. This prevents TF from being built with such toolchains, since -Werror -pedantic options are used. gcc-4.9 removed this warning; -pedantic is intended to cause gcc to emit a warning in all cases required by the standard, but the standard does not require a warning in this case. See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57773 Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-04-13Tegra: smmu: support for multiple devicesPritesh Raithatha
This patch adds flexibility to the code to initialise multiple SMMU devices. The base address macro name has been changed to make it explicit that we support multiple SMMUs. Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13Tegra: smmu: platform handler for SMMU settingsPritesh Raithatha
This patch empowers the platforms to provide an array with the registers that must be saved/restored across System Suspend. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra: allow platforms to override plat_core_pos_by_mpidr()Varun Wadekar
This patch makes the default implementation of plat_core_pos_by_mpidr() as weakly linked, so that platforms can override it with their own. Tegra186, for one, does not have CPU IDs 2 and 3, so it has its own implementation of plat_core_pos_by_mpidr(). Change-Id: I7a5319869c01ede3775386cb95af1431792f74b3 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra: memctrl_v2: platform handler for MC settingsPritesh Raithatha
This patch empowers the platforms to provide the settings (e.g. stream ID, security setting, transaction overrides) required by the Memory Controller driver. This allows the platforms to program the Memory Controller as per their needs and makes the driver scalable. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: mce: support for TEGRA_ARI_MISC_CCPLEX_EDBGREQRich Wiley
This ARI call enables the EDBGREQ feature in the CCPLEX, which will cause the CPUs to enter debug state instead of vectoring to sw (ie MCA handler) upon receiving an async abort signal. Change-Id: Ifcb0e11446b6ac55179e3350d8f02b60ba32c94d Signed-off-by: Rich Wiley <rwiley@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: update t18x_ari.h to v3.1Varun Wadekar
This patch updates the ARI header file to v3.1. Change-Id: I3e58cf50d27fb6e72062bb9d9782b75296b32025 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: PSCI: support for 64-bit TZDRAM baseSteven Kao
This patch fixes the variable width to store the TZDRAM base address used to resume from System Suspend. Change-Id: Ib67eda64b09f26fb2f427f0d624f057081473132 Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra: memctrl_v2: config to enable SMMU deviceVarun Wadekar
This patch adds a config to the memory controller driver to enable SMMU device init during boot. Tegra186 platforms keeps it enabled by default, but future platforms might not support it. Change-Id: Iebe1c60a25fc1cfb4c97a507e121d6685a49cb83 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: read activity monitor's clock counter valuesVarun Wadekar
This patch adds a new SMC function ID to read the refclk and coreclk clock counter values from the Activity Monitor. The non-secure world requires this information to calculate the CPU's frequency. Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq" The following CPU registers have to be set by the non-secure driver before issuing the SMC: X1 = MPIDR of the target core X2 = MIDR of the target core Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra: memctrl_v2: make AFI device settings configurableVarun Wadekar
This patch adds a new config to enable MC settings for the AFIW and AFIR devices. Platforms must enable this config on their own. Change-Id: I53b450117e4764ea76d9347ee2928f9be178b107 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: move smmu driver to tegra/commonVarun Wadekar
This patch moves the smmu driver introduced by the Tegra186 port to tegra/common so that future chips can (re)use it. Change-Id: Ia44c7f2a62fb2d8869db3a44742a8c6b13c49036 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-07Tegra186: split MCE driver into public/private interfacesVarun Wadekar
This patch splits the MCE driver into public and private interfaces to allow usage of common functionality across multiple SoCs. Change-Id: Ib58080e730d72f11ff79507d8e0acffb2ad5c606 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: move platform specific MCE defines to tegra_def.hVarun Wadekar
This patch moves the MCE's configurable parameters to tegra_def.h for the Tegra186 SoC, to allow forward compatiblity. Change-Id: If8660c1c09908a4064dbb67d5ca4fb78389cab13 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: use MSB of wake_timeKrishna Sitaraman
This patch updates wake time of the cpu to use the MSBs and zero out the LSB's. Only 24 out of 32 bits are currently passed through the PSCI interface. Previously all the LSB's were used. Change-Id: Ie2d9d1bf6e3003dd47526a124f64e6ad555d2371 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: Update API for reset vector ARIKrishna Sitaraman
The TEGRA_ARI_COPY_MISCREG_AA64_RST ARI should be called with request_lo/hi set to zero. MTS automatically takes the reset vector from MISCREG_AA64_RST register and does not need it to be passed as parameters. This patch updates the API and the caller function accordingly. Change-Id: Ie3e3402d93951102239d988ca9f0cdf94f290d2f Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: clean CPU wake times from L2 cacheMustafa Yigit Bilgen
When entering C7, ATF disables caches and flushes the L1 cache. However, wake_time[cpu] can still remain in the L2 cache, causing later reads to it to fetch from DRAM. This will read stale values. Fix this by aligning wake_time[cpu] to cache lines, and explicitly cleaning it before disabling caches. Change-Id: Id73d095b479677595a6b3dd0abb240a1fef5f311 Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: update t18x_ari.h to v3.0Krishna Sitaraman
This patch updates the ARI header to version 3.0 Change-Id: I7cfe0c61c80a6b78625232135dd63393602d32fe Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: trampoline: update "System Suspend" exit criteriaVarun Wadekar
The TZRAM memory loses its state during "System Suspend". This patch check if TZRAM base address contains valid data, to decide if the system is exiting from "System Suspend". To enable TZDRAM encryption, the Memory Controller's TZDRAM base/size registers would be populated by the BPMP when the system "wakes up". Change-Id: I5fc8ba1ae3bce12f0ece493f6f9f5f4d92a46344 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: Add smc handler for coresight clock gatingKrishna Sitaraman
This change adds function to invoke for MISC_CCPLEX ARI calls and the corresponding smc handler. This can be used to enable/disable Coresight clock gating. Change-Id: I4bc17aa478a46c29bfe17fd74f839a383ee2b644 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: mce: fix return value for enum features ariKrishna Sitaraman
This patch fixes the incorrect return value that was being passed back for the ENUM_FEATURES ARI call. Change-Id: I3842c6ce27ea24698608830cf4c12cfa7ff64421 Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-05Tegra186: mce: clear reserved fields for ARI callsKrishna Sitaraman
This patch clears the unused or reserved ARI input registers before issuing the actual ARI command. Change-Id: I454b86566bfe088049a5c63527c1323d7b25248a Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: mce: read MCE's firmware version on "real" platformsVarun Wadekar
This patch runs the MCE firmware's version check only if the underlying platform has the capability to the run the firmware. MCE firmware is not running on simulation platforms, identified by v0.3 or v0.6, read from the Tegra Chip ID value. Change-Id: I3b1788b1ee2a0d4464017bb879ac5792cb7022b8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: use helper functions to get major/minor versionVarun Wadekar
This patch uses helper functions to read the chips's major and minor version values. Change-Id: I5b2530a31af5ab3778a8aa63380def4e9f9ee6ec Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: memmap all UART controllersVarun Wadekar
This patch adds all the UART controllers to the memory map. Change-Id: I035e55ca7bff0a96115102f2295981f9e3a5da6b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: implement plat_get_syscnt_freq2()Varun Wadekar
Commit f3d3b316f82faa88e42f3d09c97cd9e52ac92599 replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all the upstream platforms. This patch modifies the Tegra186 code which is not present usptream, yet. Change-Id: Ieda6168050a7769680a3a94513637fed03463a2d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra: smmu: disable TCU prefetch for all the 64 contextsVarun Wadekar
This patch disables TCU prefetch for all the contexts in order to improve SMMU performance. Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101d8459 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: handlers to get BL31 arguments from previous bootloaderVarun Wadekar
This patch overrides the default handlers to get BL31 arguments from the previous bootloader. The previous bootloader stores the pointer to the arguments in PMC secure scratch register #53. BL31 is the first component running on the CPU, as there isn't a previous bootloader. We set the RESET_TO_BL31 flag to enable the path which assumes that there are no input parameters passed by the previous bootloader. Change-Id: Idacc1df292a70c9c1cb4d5c3a774bd796175d5e8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: delete 'Video Memory Carveout' handlingVarun Wadekar
This patch removes duplicate code from the platform's SiP handler routine for processing Video Memory Carveout region requests and uses the common SiP handler instead. Change-Id: Ib307de017fd88d5ed3c816288327cae750a67806 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: modify the return type for `plat_get_syscnt_freq()`Varun Wadekar
Commit c073fda1c692d7c74415d26fb483d6336330fcc0 upstream changed the return type for `plat_get_syscnt_freq()` from uint64_t to unsigned long long. This patch modifies the return type for the Tegra186 platform. Change-Id: Ic9e5c364b90972265576e271582a4347e5eaa6eb Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: Enable ECC and Parity Protection for A02p SKUsVarun Wadekar
This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot, for Tegra186 A02p SKUs. Change-Id: I8522a6cb61f5e4fa9e0471f558a0c3ee8078370e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: mce: Uncore Perfmon ARI ProgrammingVarun Wadekar
Uncore perfmon appears to the CPU as a set of uncore perfmon registers which can be read and written using the ARI interface. The MCE code sequence handles reads and writes to these registers by manipulating the underlying T186 uncore hardware. To access an uncore perfmon register, CPU software writes the ARI request registers to specify * whether the operation is a read or a write, * which uncore perfmon register to access, * the uncore perfmon unit, group, and counter number (if necessary), * the data to write (if the operation is a write). It then initiates an ARI request to run the uncore perfmon sequence in the MCE and reads the resulting value of the uncore perfmon register and any status information from the ARI response registers. The NS world's MCE driver issues MCE_CMD_UNCORE_PERFMON_REQ command for the EL3 layer to start the entire sequence. Once the request completes, the NS world would receive the command status in the X0 register and the command data in the X1 register. Change-Id: I20bf2eca2385f7c8baa81e9445617ae711ecceea Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: implement `get_target_pwr_state` handlerVarun Wadekar
This patch implements the `get_target_pwr_state` handler for Tegra186 SoCs. The SoC port uses this handler to find out the cluster/system state during CPU_SUSPEND, CPU_OFF and SYSTEM_SUSPEND calls. The MCE firmware controls the power state of the CPU/CLuster/System, so we query it to get the state and act accordingly. Change-Id: I86633d8d79aec7dcb405d2301ac69910f93110fe Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-30Tegra186: mce: add the mce_update_cstate_info() helper functionVarun Wadekar
This patch adds a helper function to the MCE driver to allow its clients to issue UPDATE_CSTATE_INFO requests, without having to setup the CPU context struct. We introduced a struct to encapsulate the request parameters, that clients can pass on to the MCE driver. The MCE driver gets the parameters from the struct and programs the hardware accordingly. Change-Id: I02bce57506c4ccd90da82127805d6b564375cbf1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-27Tegra186: reset CPU power state info while onliningVarun Wadekar
This patch resets the CPU power state info when we online any CPU. The NS world software would re-init the CPU power state after the CPU gets online anyways. This allows us to maintain proper CPU/cluster power states in the MCE firmware at all times. Change-Id: Ib24054f53df720a4f88d67b2cb5a2e036e475e14 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-27Tegra186: fix recursion in included headers (tegra_def.h/platform_def.h)Varun Wadekar
This patch fixes the "Recursion in included headers" error flagged by Coverity. Fixes coverity errors "31858: Recursion in included headers" and "31857: Recursion in included headers" Change-Id: Icf8838434b1808b396e743e47f59adc452546364 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-03-23Tegra186: reset power state info during CPU_ONVarun Wadekar
This patch resets the power state info for CPUs when onlining, as we set deepest power when offlining a core but that may not be requested by non-secure sw which controls idle states. It will re-init this info from non-secure software when the core come online. Original change by Prashant Gaikwad <pgaikwad@nvidia.com> Change-Id: Id6c2fa2b821c7705aafbb561a62348c36fd3abd8 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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