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2019-10-03delay: timeout detection supportLionel Debieve
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT. timeout_init_us(some_timeout_us); returns a reference to detect timeout for the provided microsecond delay value from current time. timeout_elapsed(reference) return true/false whether the reference timeout is elapsed. Cherry picked from OP-TEE implementation [1]. [1] commit 33d30a74502b ("core: timeout detection support") Minor: - Remove stm32mp platform duplicated implementation. - Add new include in marvell ble.mk Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c
2019-08-01Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__Julius Werner
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-26Merge changes from topic "advk-serror" into integrationSoby Mathew
* changes: marvell/a3700: Prevent SError accessing PCIe link while it is down marvell: Switch to xlat_tables_v2
2019-07-16marvell/a3700: Prevent SError accessing PCIe link while it is downRemi Pommarel
When the link goes down (e.g. during a retrain), accessing the device configuration space can trigger an ARM64 SError interrupt. Such conditions cannot be predicted, so to avoid a crash the SError is ignored. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Change-Id: I2b1fd3296cc1c88b9ca1fe21c0924cb324eed58d
2019-07-16marvell: Switch to xlat_tables_v2Remi Pommarel
Use v2 xlat tables library instead of v1 for marvell platforms. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Change-Id: I838a6a878a8353e84eea9529721761b478943f0a
2019-07-11Update marvell platform to not rely on undefined overflow behaviourJustin Chadwell
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-06-28Remove MULTI_CONSOLE_API flag and references to itAmbroise Vincent
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-05plat: marvell: do not rely on argument passed via smcGrzegorz Jaszczyk
There is no need to rely on x1 argument. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Change-Id: Ie7766e801e724801b42b66331ba252ede5744a2c
2019-04-05plat: marvell: sip: make sure that comphy init will use correct addressGrzegorz Jaszczyk
The argument passed via x1 is used as a base address for comphy related routines. Nevertheless validation of this address wasn't good enough and allowed some non comphy related addresses to slip over. To overcome this issue make sure that the address passed via SMC points to valid CP range and allow to proceed comphy initializations only with correct comphy offset. This could be fixed in a different way e.g. by passing CP id from the caller, but since this API is already used with various Linux, U-Boot and UEFI versions it can't be changed. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Change-Id: Ia74dbc36efcfbefc4a102d31191e6af5808c4a82
2019-02-01Remove unneeded include paths in PLAT_INCLUDESAntonio Nino Diaz
Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-01Remove duplicated definitions of linker symbolsAntonio Nino Diaz
Many parts of the code were duplicating symbols that are defined in include/common/bl_common.h. It is better to only use the definitions in this header. As all the symbols refer to virtual addresses, they have to be uintptr_t, not unsigned long. This has also been fixed in bl_common.h. Change-Id: I204081af78326ced03fb05f69846f229d324c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-31Merge pull request #1745 from svenauhagen/bugfix/a8kAntonio Niño Díaz
Armada8k GPIO Register macro fix
2019-01-15Move BL1 and BL2 private defines to bl_common.hAntonio Nino Diaz
The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for platforms that may need to access them. Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-09Armada8k GPIO Register macro fixSven Auhagen
The macro has n > 32. It has to be n > 31 since GPIO 0-31 are on Register 0 and 32-63 on Register 1. Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-12-10Merge pull request #1700 from jwerner-chromium/JW_crashfixSoby Mathew
MULTI_CONSOLE_API fixes and cleanups
2018-12-06drivers/console: Link console framework code by defaultJulius Werner
This patch makes the build system link the console framework code by default, like it already does with other common libraries (e.g. cache helpers). This should not make a difference in practice since TF is linked with --gc-sections, so the linker will garbage collect all functions and data that are not referenced by any other code. Thus, if a platform doesn't want to include console code for size reasons and doesn't make any references to console functions, the code will not be included in the final binary. To avoid compatibility issues with older platform ports, only make this change for the MULTI_CONSOLE_API. Change-Id: I153a9dbe680d57aadb860d1c829759ba701130d3 Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-12-04plat/marvell: update platform LSP version to 18.12.0Konstantin Porotchkin
Sync the platform code version with current Marvell LSP. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-12-04a8k: pm: extend MSS_TRIGGER_TIMEOUTIgal Liberman
Very rarely, during cpuidle operations the following error is seen: "PM MSG Trigger Timeout". This is caused by slow handling of message interrutps in the PM FW running on CM3 (under heavy PM operation load). This is not a real issue, so we extend the timeout to avoid the error prints. Change-Id: I92fd6f2ff1ddf208b216c123880ded28a00b6e0e Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59670 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-12-04plat/marvell: comphy: Add support for SFI on Lane 4Konstantin Porotchkin
Add static configuration for SFI+ 10Gbps interface on SERDES Lane 4. This is just a copy of Lane 2 static values, not optimized. Board-to-board iperf test shows up to 6Gbps transfer speed. Change-Id: I024d2ac132f7fa6c342a64367f3dca2123a27e97 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-12-04fix: a3900: pm: fix number of CPU power switches.Christine Gharzuzi
- Number of open power switches for CPUs should be three and now two. - This patch updates the value of open power switches from 0xfd (two power-switches) to 0xfc (three power-switches). Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-12-04svc: Update the EEPROM AVS values processingKonstantin Porotchkin
Add support for SVC test builds for tuning AVS values. Update the SVC procedure and add EEPROM access. Add support for AP807 AVS values (10 bits wide). Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-12-04ble: ap807: Switch to PLL mode and update CPU frequencyChristine Gharzuzi
- Update CPU frequency on AP807 to 2GHz for SAR 0x0. - Increase AVS to 0.88V for 2GHz clock Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-12-04mvebu: cp110: avoid pcie power on/off sequence when called from LinuxIgal Liberman
In Armada 8K DB boards, PCIe initialization can be executed only once because PCIe reset performed during chip power on and it cannot be executed via GPIO later. This means that power on can be executed only once, when it's called from the bootloader. Power on: Read bit 21 of the mode, it marks if the caller is the bootloader or the Linux Kernel. Power off: Check if the comphy was already configured to PCIe, if yes, check if the caller is bootloader, if both conditions are true (PCIe mode and called by Linux) - skip the power-off. In addition, fix incorrect documentation describing mode fields - PCIe width is 3 bits, not 2. NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work with it). Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-12-04plat: marvell: a3700: do not power off cpu due to errata ref #13Grzegorz Jaszczyk
Do not power off the CPU1 since there is no way to wake it up (wake-up is causing CPU0 reset as well duo to HW bug). Quote from errata Ref #13 [In power saving mode, both cores must be powered off]: "When Core 0 is on and Core 1 is in power-off state, a Core 1 wake-up resets Core 0 as well and puts Core 0 back to ROM". To overcome described HW bug instead of powering the CPU off, let it reach WFI instruction, which is invoked by generic psci_do_cpu_off function after platform handler finishes. This will put the core in low power state and give a chance to wake it up. Before this change, after running secondary kernel via kexec, only one core was up, now both cores are up. Change-Id: I87f144867550728055d9b8a2edb84a14539acab7 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-11-15plat/marvell: Migrate to multi-console APIKonstantin Porotchkin
Migrate Marvell platforms from legacy console API to multi-console API. Change-Id: I647f5f49148b463a257a747af05b5f0c967f267c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-11-15fix: plat/marvell: a3700: Remove encryption passwordKonstantin Porotchkin
According to "openssl" manual: -K key The actual key to use: this must be represented as a string comprised only of hex digits. If only the key is specified, the IV must additionally specified using the -iv option. When both a key and a password are specified, the key given with the -K option will be used and the IV generated from the password will be taken. It does not make much sense to specify both key and password. This patch removes "-k 0" parameter from the encryption command since we are already using "-K" and "-iv" for the key and IV. Change-Id: Ia333cedaa3207e643c95d2ec7c229f50eeab96db Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60745 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Sharon Habet <sharonh@marvell.com>
2018-11-08Standardise header guards across codebaseAntonio Nino Diaz
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-01Merge pull request #1623 from MISL-EBU-System-SW/a3700-supportAntonio Niño Díaz
Add support for Armada 3700 and COMPHY porting layer
2018-10-31plat: marvell: Add support for Armada-37xx SoC platformKonstantin Porotchkin
Add supprot for Marvell platforms based on Armada-37xx SoC. This includes support for the official Armada-3720 modular development board and EspressoBin community board. The Armada-37xx SoC contains dual Cortex-A53 Application CPU, single secure CPU (Cortex-M3) and the following interfaces: - SATA 3.0 - USB 3.0 and USB 2.0 - PCIe - SDIO (supports boot from eMMC) - SPI - UART - I2c - Gigabit Ethernet Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-10-25Add plat_crash_console_flush to platforms without itAntonio Nino Diaz
Even though at this point plat_crash_console_flush is optional, it will stop being optional in a following patch. The console driver of warp7 doesn't support flush, so the implementation is a placeholder. TI had ``plat_crash_console_init`` and ``plat_crash_console_putc``, but they weren't global so they weren't actually used. Also, they were calling the wrong functions. imx8_helpers.S only has placeholders for all of the functions. Change-Id: I8d17bbf37c7dad74e134c61ceb92acb9af497718 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-10-22tools: Move doimage to marvell folder for future add-onsKonstantin Porotchkin
Move doimage utility from toos/doimage to tools/marvell/doimage. This is done for supporting mode Marvell tools in the future. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-10-18mvebu: cp110: introduce COMPHY porting layerGrzegorz Jaszczyk
Some of COMPHY parameters depends on the hw connection between the SoC and the PHY, which can vary on different boards e.g. due to different wires length. Define the "porting layer" with some defaults parameters. It ease updating static values which needs to be updated due to board differences, which are now grouped in one place. Example porting layer for a8k-db is under: plat/marvell/a8k/a80x0/board/phy-porting-layer.h If for some boards parameters are not defined (missing phy-porting-layer.h), the default values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the following compilation warning is show: "Using default comphy params - you may need to suit them to your board". The common COMPHY driver code is extracted in order to be shared with future COMPHY driver for A3700 SoC platforms Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-10-11Merge pull request #1621 from jts-arm/typosSoby Mathew
Various corrections of typos
2018-10-10Replace S-EL3 references by EL3John Tsichritzis
The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix has been removed from wherever it was used as "S-EL3". Change-Id: Icdeac9506d763f9f83d7297c7113aec7b85e9dbe Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-10-07plat: marvell: invoke platform specific scp_bl2 image handlerGrzegorz Jaszczyk
Before switching to new API the scp_bl2 handler was invoked from bl2/bl2_image_load.c which was removed. Invoke the platform specific scp_bl2 handler in analogy to ARM and HiSilicon. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2018-10-03marvell: Move BLE from external repo to the platform folderKonstantin Porotchkin
The BLE is the pre-TF-A boot stage required by Marvell Armada BootROM for bringing up DRAM and allow the boot image copy to it. Since this is not a standard boot level and only uses the TF-A as a build environment, it was introduced out of source tree. However it turns out that such remote location introduces additional complexity to the upstream TF-A build process. In order to simplify the build environment the BLE source folder is relocated from the external repository to A8K platform directory. The build documentation is updated accordingly. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-10-02marvell: Continue migration to new APIsKonstantin Porotchkin
- Fix build issue - Add initial memory parameters descriptors for BL2 - Migrate to image load V2 Basic build and run test passed on MacchiatoBin board. Need to fix the service CPU (CM3) image load procesure and test OPTEE functionality, which probably will require additional work. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-09-28marvell: Migrate to new interfacesAntonio Nino Diaz
- Migrate to bl2_early_platform_setup2(). - Remove references to removed build options. - Use private definition of bl31_params_t. This is an incomplete migration, the platform doesn't currently compile. Change-Id: I1ae477b1f2489f49b651528050fdf06e4a55e425 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-19drivers: i2c: mentor: move platform code into header filesAndre Przywara
At the moment we have two I2C stub drivers (for the Allwinner and the Marvell platform), which #include the actual .c driver file. Change this into the more usual design, by renaming and moving the stub drivers into platform specific header files and including these from the actual driver file. The platform specific include directories make sure the driver picks up the right header automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-09-05drivers: mentor: extract MI2CV driver from Marvell driverIcenowy Zheng
The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which is also used by Allwinner. As Mentor Graphics allows a lot of customization, the MI2CV in the two SoC families are not compatible, and driver modifications are needed. Extract the common code to a MI2CV driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-09-03plat: marvell: Update Marvell base code version to 18.09.1Konstantin Porotchkin
Change-Id: I908844364bf8080612aaa6d750d7d2441ecc2eb8 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-09-03plat: svc: ap807: add SVC configuration for AP807Christine Gharzuzi
- add svc configuration according to values burnt to the chip efuse Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03fix: marvell: Check the required libraries before building doimageKonstantin Porotchkin
Some customers are missing host libraries required for doimage builds. This patch requests for the library installation check for every doimage build and suggest the required installation steps in case of missing headers. Change-Id: Icde18c3d4d6045f65e50d2dc9e6514971f40033e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-09-03plat: a8k: enable PMU overflow interrupt handlerMarcin Wojtas
This patch enables handling PMU overflow IRQ by GIC SPI's directly in EL3. Also implement additional SMC routine, which can disable the solution on demand in runtime. Since it is possible to configure PMU interrupt trigger type in the MADT ACPI table, it is enough to set it only once in EL3 during initialization. Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-02marvell: pm: do not panic by default in cpu_standbyMarcin Wojtas
Current default behavior of cpu_standby callback is problematic during the SBSA test, which is unable to run due to EL3 panic. Make it dependent on the PM firmware running. Change-Id: I7a53de8c880bd23b157dd65ce14bb48b5a5c76c8 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-02plat: marvell: a80x0: reconfigure CP0 PCIE0 windowsMarcin Wojtas
In order to allow the use of PCIe cards such as graphics cards, whose demands for BAR space are typically much higher than those of network or SATA/USB cards, reconfigure the I/O windows so we can declare two MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64 one at 0x8_0000_0000. In addition, this will leave ample room for an ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB) For compatibility with older kernels or firmware, leave the original 16 MB window in place as well. Change-Id: Ia8177194e542078772f90941eced81b231c16887 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-02plat: marvell: a70x0: reconfigure CP0 PCIE2 windowsMarcin Wojtas
In order to allow the use of PCIe cards such as graphics cards, whose demands for BAR space are typically much higher than those of network or SATA/USB cards, reconfigure the I/O windows so we can declare two MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64 one at 0x8_0000_0000. In addition, this will leave ample room for an ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB) For compatibility with older kernels or firmware, leave the original 16 MB window in place as well. Change-Id: I80b00691ae8d0a3f3f7285b8e0bfc21c0a095e94 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-02a8k: use the memory controller feature to protect the RT service regionGrzegorz Jaszczyk
Define the RT service space as secure with use of memory controller trustzone feature. Thanks to this protection, any NS-Bootloader nor NS-OS, won't be able to access RT services (e.g. accidentally overwrite it, which will at best result in RT services unavailability). Change-Id: Ie5b6cbe9a1b77879d6d8f8eac5d4e41e468496ce Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-02plat: marvell: rename common include fileKonstantin Porotchkin
Rename a8k_common.h to armada_common.h to keep the same header name across all other Marvell Armada platforms. This is especially useful since various Marvell platforms may use common platform files and share the driver modules. Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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