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2019-09-12Invalidate dcache build option for bl2 entry at EL3Hadi Asyrafi
Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06
2019-09-12intel: agilex: Fix psci power domain offHadi Asyrafi
Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673
2019-09-05Merge "intel: stratix10: Fix reliance on hard coded clock information" into ↵Sandrine Bailleux
integration
2019-08-28Merge "intel: agilex: Clear PLL lostlock bypass mode" into integrationPaul Beesley
2019-08-19intel: agilex: HMC driver calculate DDR sizeHadi Asyrafi
Driver will calculate DDR size instead of using hardcoded value Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde
2019-08-19intel: agilex: Clear PLL lostlock bypass modeHadi Asyrafi
To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
2019-08-15Merge "intel: agilex: Fix memory controller driver" into integrationPaul Beesley
2019-08-15intel: agilex: Fix memory controller driverHadi Asyrafi
Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b
2019-08-14intel: agilex: Fix reliance on hard coded clock informationHadi Asyrafi
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
2019-08-13intel: stratix10: Fix reliance on hard coded clock informationHadi Asyrafi
Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
2019-08-07Merge changes from topic "intel-plat-refactor" into integrationSandrine Bailleux
* changes: intel: Platform common code refactor intel: Platform common code refactor
2019-08-07intel: Platform common code refactorHadi Asyrafi
Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
2019-08-02Merge "intel: stratix10: Fix BL31 memory mapping" into integrationAlexei Fedorov
2019-08-02intel: stratix10: Fix BL31 memory mappingHadi Asyrafi
Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ia857facd0bd0790056df94ed1e016bcf619a161e
2019-08-01intel: Platform common code refactorHadi Asyrafi
Pull out common code from agilex and stratix10 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
2019-07-30intel: agilex: Fix BL31 memory mappingHadi Asyrafi
Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic97aa381d3ceb96395595ec192132859d626b8d1
2019-07-24intel: agilex: Fix build errorAmbroise Vincent
"result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eba8ca ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-07-19Merge "intel: Adds support for Agilex platform" into integrationSoby Mathew
2019-07-17intel: Adds support for Agilex platformHadi Asyrafi
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
2019-07-16Merge changes from topic "jc/shift-overflow" into integrationSoby Mathew
* changes: Enable -Wshift-overflow=2 to check for undefined shift behavior Update base code to not rely on undefined overflow behaviour Update hisilicon drivers to not rely on undefined overflow behaviour Update synopsys drivers to not rely on undefined overflow behaviour Update imx platform to not rely on undefined overflow behaviour Update mediatek platform to not rely on undefined overflow behaviour Update layerscape platform to not rely on undefined overflow behaviour Update intel platform to not rely on undefined overflow behaviour Update rockchip platform to not rely on undefined overflow behaviour Update renesas platform to not rely on undefined overflow behaviour Update meson platform to not rely on undefined overflow behaviour Update marvell platform to not rely on undefined overflow behaviour
2019-07-11Update intel platform to not rely on undefined overflow behaviourJustin Chadwell
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-10plat/intel: Fix SMPLSEL for MMCTien Hock, Loh
MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a
2019-06-28Merge changes from topic "av/console-port" into integrationPaul Beesley
* changes: qemu: use new console interface in aarch32 warp7: remove old console from makefile Remove MULTI_CONSOLE_API flag and references to it Console: removed legacy console API
2019-06-28Remove MULTI_CONSOLE_API flag and references to itAmbroise Vincent
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-06-26intel: Add ncore ccu driverHadi Asyrafi
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0544315986ee28b23157fdfec3fe5aebae6b860f
2019-06-26intel: Fix watchdog driver structureHadi Asyrafi
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0ffccca7ea83bff35c9f149d7054cd610a59ec01
2019-06-26intel: Fix qspi driver write configHadi Asyrafi
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5241ed97697b0280b590b47b9173d102d23f305a
2019-06-26intel: Pull out common drivers into platform commonHadi Asyrafi
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib79e2c6fe6e66dec5004701133ad6a5f4c78f2fa
2019-03-21intel: Enable watchdog timer on Intel S10 platformMuhammad Hadi Asyrafi Abdul Halim
Watchdog driver support & enablement during platform setup Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
2019-03-13Merge pull request #1874 from hadi-asyrafi/qspi_bootSoby Mathew
intel: QSPI boot enablement
2019-03-13intel: QSPI boot enablementMuhammad Hadi Asyrafi Abdul Halim
Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
2019-03-13intel: Add driver for QSPIMuhammad Hadi Asyrafi Abdul Halim
To support the enablement of QSPI booting Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
2019-03-08Merge pull request #1863 from thloh85-intel/mmc_fixesDimitris Papastamos
drivers: mmc: Fix some issues with MMC stack
2019-03-08plat: intel: Add MMC OCR voltage information for initializationTien Hock, Loh
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
2019-03-07Merge pull request #1864 from hadi-asyrafi/mailbox_fixDimitris Papastamos
intel: Mailbox service un-accessible
2019-03-07intel: Mailbox service un-accessibleMuhammad Hadi Asyrafi Abdul Halim
Change map region for device 2 from non-secure to secure Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
2019-03-07plat: intel: Improve ECC scrubbing performanceTien Hock, Loh
We should be using zeromem to scrub memory instead of memset. This would improve the performance by 200x Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
2019-02-26plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platformTien Hock, Loh
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
2019-02-13plat: intel: Fix faulty DDR calibration valueLoh Tien Hock
A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
2019-02-04plat: intel: Add BL2 support for Stratix 10 SoCLoh Tien Hock
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
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