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path: root/plat/intel/soc/agilex
AgeCommit message (Expand)Author
2019-09-12Invalidate dcache build option for bl2 entry at EL3Hadi Asyrafi
2019-09-12intel: agilex: Fix psci power domain offHadi Asyrafi
2019-08-28Merge "intel: agilex: Clear PLL lostlock bypass mode" into integrationPaul Beesley
2019-08-19intel: agilex: HMC driver calculate DDR sizeHadi Asyrafi
2019-08-19intel: agilex: Clear PLL lostlock bypass modeHadi Asyrafi
2019-08-15Merge "intel: agilex: Fix memory controller driver" into integrationPaul Beesley
2019-08-15intel: agilex: Fix memory controller driverHadi Asyrafi
2019-08-14intel: agilex: Fix reliance on hard coded clock informationHadi Asyrafi
2019-08-07Merge changes from topic "intel-plat-refactor" into integrationSandrine Bailleux
2019-08-07intel: Platform common code refactorHadi Asyrafi
2019-08-01intel: Platform common code refactorHadi Asyrafi
2019-07-30intel: agilex: Fix BL31 memory mappingHadi Asyrafi
2019-07-24intel: agilex: Fix build errorAmbroise Vincent
2019-07-17intel: Adds support for Agilex platformHadi Asyrafi
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