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2018-11-01imx8q: [trusty] Kick CAAM powerJi Luo
JR0 and JR1 of CAAM are owned by SECO, only kick the power of JR2 and JR3 here and assign the resources to be accessed by secure world. Signed-off-by: Ji Luo <ji.luo@nxp.com>
2018-10-29MA-13239 imx8qm: Touch correct pad for UART0Haoran.Wang
Due imx8qm_mek's UART0_RTS_B and UART0_CTS_0 pad reuse to be the UART2 for base bard which operated by M4_1, so don't touch these two pads in ATF. Signed-off-by: Haoran.Wang <elven.wang@nxp.com> Acked-by: Pete Zhang <pete.zhang@nxp.com>
2018-10-25iMX8Q: Don't copy tee after fit is enabledLuo Ji
Tee(Trusty Os) will be stored in fit for Android and Android Auto so we don't need to copy it anymore, this will save some boot time. Signed-off-by: Luo Ji <ji.luo@nxp.com>
2018-10-12imx8qm: keep A53 cluster power on for cache coherency issueAnson Huang
A53 cluster cannot be power gated unless the entire multi-cluster (A53 + A72 + CCI) is gated off. Root cause still TBD, this patch adds temporary workaround to ONLY allow A53 power off when system suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-28imx8qm/imx8qxp: enable output debug message to SC consoleAnson Huang
Add support for enabling output debug message to SC console, SC_CONSOLE is used to enable/disable it. Example log output on SC console as below: *** Debug Monitor *** >$ NOTICE: smc_fid is c2000003 imx_pwr_domain_on cluster_id 0, cpu_id 1 cluster:0 core:1 is on imx_pwr_domain_on cluster_id 0, cpu_id 2 cluster:0 core:2 is on imx_pwr_domain_on cluster_id 0, cpu_id 3 cluster:0 core:3 is on imx_pwr_domain_on cluster_id 1, cpu_id 0 cluster:1 core:0 is on imx_pwr_domain_on cluster_id 1, cpu_id 1 cluster:1 core:1 is on Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-26imx8qm/imx8qxp: add misc set temp SIP supportAnson Huang
Add FSL_SIP_MISC_SET_TEMP support for setting thermal alarm function. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-12MA-11015 Support Trusty OS on imx8qm/qxpHaoran.Wang
The Trusty OS binary will be installed into container.img and loaded into 0x84000000. Due Trusty OS addresss is in 0xfe000000 which ROM cannot reach, so use ATF to copy it into the target address. Mapped the BL32 code into MMU due the Trusty SPD need to check the code status and decide the CPU executing mode. To reserve and protect the memory for secure world, modify the partition code to keep BL32 spaces in secure_part. Signed-off-by: Haoran.Wang <elven.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2018-09-08imx8qm/imx8qxp: support random CPU resume when system suspendAnson Huang
Using sc_pm_set_cpu_resume API instead of sc_pm_set_cpu_resume_addr to support random CPU resume for system suspend, as Linux kernel now supports non CPU0 suspend, we have to specify the CPU ID for SCFW to wake up when system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-27imx8qm: put IRQ_STEER/DRC/DBLOGIC into OFF when suspendAnson Huang
To support KS1, need to put all resources into OFF mode instead of STBY when Linux kernel suspend. Here, DRC, IRQ_STEER and DBLOGIC can be OFF for KS1 mode. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-26imx8: postpone moving resources to non-secure partitionPeng Fan
With flash_uboot_cm4ddr in imx-mkimage, the m4 code will access ddr. However after m4 core moved to non-secure partition, the ddr memory is still in secure partition. Then m4 core will fault. So postpone moving resources including m4 core, until other resources, such as memory/pin moved to non-secure partition. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1c8ce0ad5f583ec41026d4ab5bef622f1b45aecd)
2018-07-05imx8qm/imx8qxp: switch to MULTI_CONSOLE_API for debug uart supportAnson Huang
Switch to MULTI_CONSOLE_API to make debug UART work. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-03MLK-18732-2: Add OTP SIP service for QM/QXTeo Hall
Add SIP service for OTP reading/writing for use in u-boot Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-06-21imx: enable necessary erratas for A53 r0p4Anson Huang
This patch enables necessary erratas for A53 r0p4 according to docs/cpu-specific-build-macros.rst. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-20imx8qm: support MU power off during suspendAnson Huang
Add MU power off support for suspend, it needs to be re-initialized after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11imx8qm: move M4 to OS part at lastPeng Fan
With default configuration, M4 and A35 in one partition, M4 is loaded by ROM. "err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);" M4 core will first be moved to non-secure OS part, then the resource used by M4 will be moved to non-secure OS part later. But before the resource be moved to non-secure OS part, M4 core is still running, so a non-secure M4 core access a secure resource will trigger error in M4 side. First mark M4 core as non-movable, after all other resoures moved to OS part, move M4 to OS part. No need to check whether M4 is created a new partition by SCFW, if a partition already created, the call to mark M4 as non-removable will fail, because it M4 is in its own partition. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-06-11plat: imx: Fix the IRQSTR power modes for iMX8QM/QXPNitin Garg
make sure to put IRQSTEER SCU into correct power modes. Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2018-06-11plat: freescale: update the license identifier with SPDX short identifierBai Ping
clean up the license identifier with short SPDX short identifier. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8qm: Use MU0 for SCU communicationAnson Huang
Use MU0 to comply with boot image usage of MU, Also power on and pass MU1 for OS/Hypervisor. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11plat: imx: add gic save/restore for imx8qm/qxpBai Ping
In order to save power when AP side is suspend, the DBLOG need to be put into low power mode. GIC need to be power off to save power. before GIC power off, we need to save the GIC setting, then after resume, we need to restore the gic setting. irqsteer need to be used to wakeup the AP side when wakeup interrupt is pending for AP side. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx: add scu2 irqstr to sec rsrcBai Ping
The irqstr for scu2 is used for AP wakeup if gic is power off, so this resource need to be added to the sec rsrc. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11imx8qm: Enable erratum 859971Peng Fan
`ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 859971: Speculative instruction prefetch to Execute-never (XN) memory could cause deadlock or data integrity issue On i.MX8QM, we are using r0p2, so enable this errata. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-06-11imx8qm: correct cluster/cpu power down sequenceAnson Huang
cluster needs to be power down only after cpus inside it are all powered down, so move all of them into kill function; Enable USE_COHERENT_MEM feature to make sure no cache coherence issue and avoid cache operations in many places; Add return value for cpu kill function. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2018-06-11imx8qm/imx8qxp: enlarge MAX_XLAT_TABLES to make debug version workAnson Huang
In worse case, MAX_XLAT_TABLES needs to be equal to MAX_MMAP_REGIONS, enlarge MAX_XLAT_TABLES to make debug version ATF can boot up, otherwise, it may fail at below: ASSERT: lib/xlat_tables/xlat_tables_common.c <362> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11Add low power state requests:Ranjani Vaidyanathan
1. Request to DRC switch to STBY in low power. 2. Set GIC to LP mode once GIC interface has been disabled in low power flow. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2018-06-11plat: freescale: imx8qm/qxp: add poweroffRobin Gong
Add power off interface for Linux. Currently poweroff the whole board,may change to poweroff partition if necessary. sync with the below scfw commit: commit 0e1f8aa5d6c6a6d9b8c05d5a84bbd613b301d367 Author: Chuck Cannon <chuck.cannon@freescale.com> Date: Tue Nov 28 13:56:29 2017 -0600 Use SC_R_BOARD_R1 to control the base board reset. Signed-off-by: Chuck Cannon <chuck.cannon@freescale.com> Signed-off-by: Robin Gong <yibin.gong@nxp.com>
2018-06-11Request the appropriate modes for runtime and low power for DDR, MU,Ranjani Vaidyanathan
system interconnect etc. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
2018-06-11imx8qm: add cluster power on/off for cpu hot-plug and suspendAnson Huang
When doing cpu hot-plug, if all CPUs in same cluster are off, then this cluster's power and CCI port can be also turned off to save power. Also add cluster and CCI low power mode request to SCFW. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11imx8qm: add suspend/resume supportAnson Huang
Add suspend/resume support with all CPUs power down. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11i.mx8qm/i.mx8qxp: psci: add power off supportAnson Huang
Add system_off pcsi callback to avoid below kernel message when doing power off: [11613.953711] reboot: Power down [11613.958318] systemd-shutdow: 8 output lines suppressed due to ratelimiting [11613.965285] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00 [11613.965285] [11613.974441] CPU: 0 PID: 1 Comm: systemd-shutdow Not tainted 4.9.11-03354-g0e1 [11613.982369] Hardware name: Freescale i.MX8QXP LPDDR4 ARM2 (DT) [11613.988216] Call trace: [11613.990681] [<ffff0000080882bc>] dump_backtrace+0x0/0x1a8 [11613.996092] [<ffff000008088478>] show_stack+0x14/0x1c [11614.001154] [<ffff0000083aaf98>] dump_stack+0x8c/0xac [11614.006213] [<ffff000008162aac>] panic+0x124/0x28c [11614.011016] [<ffff0000080c0b20>] complete_and_exit+0x0/0x20 [11614.016600] [<ffff0000080dc6d8>] SyS_reboot+0x168/0x244 [11614.021829] [<ffff000008082ef0>] el0_svc_naked+0x24/0x28 [11614.027153] Kernel Offset: disabled [11614.030646] Memory Limit: none [11614.040755] ---[ end Kernel panic - not syncing: Attempted to kill init! exi0 [11614.040755] As there is no system power off SCFW API available now, so just simply do wfi and never return when system_off is called. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11freescale: add srtc SIP supportAnson Huang
Add SRTC SIP support for i.MX8QM/i.MX8QXP. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11imx8qm: add board reboot supportAnson Huang
Add i.MX8QM board reboot support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11i.mx8qm/i.mx8qxp: add SIP cpu-freq supportAnson Huang
Linux kernel will issue cpu-freq scale via SIP, ATF calls SCFW API to finish the CPU frequency scale. Move SIP service code from i.mx8mq to common place for all i.mx SoCs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11imx8qm/qxp: Reserve memory region for ATFYe Li
Reserve the memory region that is only can access by ATF. ATF is running in this memory region, while masters in other partitions can't access it. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-06-11imx8qm/qxp: Modify the memory regions allocation to NS partitionYe Li
Change to search the ATF owned memory regions and assign them to non-secure OS partition. Not allocate new memory region for each one. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-06-08imx8qm/imx8qxp: no need to disable console in plat runtime setupAnson Huang
As we already have control for debug console in platform_def.h, so no need to un-initialize console in plat runtime setup, just overwrite the common implementation with blank function. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-08iMX8QM/QXP: Allocate memory regions to NS partitionYe Li
Not only the resources, but also the memory regions need to assign to non-secure partition. Otherwise, when the boot partition is secured, the OS non-secure partition can't access any memory. This patch currently assign all memory to NS partition, since it is not isolated, the current secure partition also can access them. In future, may need to change the regions for reserving some memory in secure partition for ATF and BL32. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-06-08iMX8QM: Do not terminate barrier transcations in CCINitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2018-06-08Fix the UART PAD ctrl in last commitNitin Garg
missed bit 31 and 30 which are needed Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2018-06-08Fix the pinmux to use correct resource ID for iMX8QM/QXNitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2018-06-08i.MX8QM: disable debug console by defaultNitin Garg
Disable ATF console output for iMX8QM Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2018-06-08Add support for A72 CPU0 as primary cpuAnson Huang
Need to add support for booting up A72 cluster only, so on need to check the cluster ID for primary CPU, that means if CPU ID is 0, then it can be as primary CPU. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-08Fix A72 L2 DATA latency and support booting CA72 as primaryNitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2018-06-08Fix MMU mapping for MU in useTeo Hall
change MMU mapping to use the address of the MU currently being used for ATF Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-06-08update secure partition and add NS accessTeo Hall
add more resources to secure partition for protection. Also add in functionality to allow for register access of some secure-owned peripherals. These peripherals will still be protected from power or clk changes. Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-06-08add RM scu svc and partition secure MUTeo Hall
add rm svc api and set aside separate MU for secure api calls into SCU Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-06-08Correct debug uart baudrate for i.MX8QMAnson Huang
UART baudrate is 115200 on i.MX8QM ARM2 board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-08Add i.MX8QM suport.Anson Huang
Add i.MX8QM platform support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
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