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2018-11-13MMIOT-152 + MMIOT-157 : move specific RDC configuration from driver to board ↵Olivier Masse
setup Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2018-11-13MMIOT-152 Rebase on imx_1.5.y + imx8mm : DRM RDC config addedOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2018-11-02plat: imx8mq: remove unused files on imx8mqBai Ping
remove unused files on i.MX8MQ. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-02plat: imx8mq: refact the dram low power codeBai Ping
refact the dram low power related code to make it more friendly for different dram config or different board. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-17plat: imx8mq: add 100us delay after USB OTG SRC bit 0 clearBai Ping
After the SRC bit clear, we must wait for a while to make sure the operation is finished. for USB OTG, the limitations are: 1. before system clock configuration. ipg clock runs at 12.5MHz. delay time should longer than 82us. 2. after system clock configuration. ipg clock runs at 66.5MHz. delay time should longer than 15.3us. so add udelay 100 to safely clear the SRC bit 0. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-13imx8mq: fix soc_id issueAnson Huang
The chip revision should ONLY overwrite the lower 16 bits of soc_id, otherwise, the cpu_is_imx8mq() API in Linux kernel will be incorrect. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-06MLK-19465 imx8mq: Fix cpu rev issue on B0.1 chipYe Li
On B0.1 chip, the value is 0x1020 not 0x20, due to minor version updated. So if reading the word and comparing with 0x20, the result is wrong. Fix the issue by only reading low major version byte for ROM version Signed-off-by: Ye Li <ye.li@nxp.com>
2018-09-03imx8mq: update chip revision method for B1Anson Huang
i.MX8MQ B1's chip revision is identified by reading OCOTP offset 0x40, the magic number 0xff0055aa is for B1. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-31plat: imx8mq: update the ddr controller perf QoS settingBai Ping
update the ddr controller perf QoS setting on i.MX8MQ. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-22imx8mq:plat: add noc priority configuration entryZhang Bo
Add NOC configuration entry for all the module. Kernel can configure the noc priority through this entry. Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
2018-07-05imx8mq/imx8mm: make sure no overlap during memory mapAnson Huang
The debug version of TF-A has below assert, fix it by making sure no memory map overlap. ASSERT: lib/xlat_tables/xlat_tables_common.c:129 Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-05imx8mq/imx8mm: switch to MULTI_CONSOLE_API for debug uart supportAnson Huang
Switch to MULTI_CONSOLE_API to make debug UART work. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-21imx: enable necessary erratas for A53 r0p4Anson Huang
This patch enables necessary erratas for A53 r0p4 according to docs/cpu-specific-build-macros.rst. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11MLK-18343-2: plat: imx8mm: add support for RDC and CSUSilvano di Ninno
move CSU and RDC driver to common/i.mx8m folder and enable the driver for i.mx8mm Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
2018-06-11plat: imx8m: move hab file to common dir of imx8mBai Ping
As the i.MX8MM and i.MX8MQ share the same hab file, move it to common/imx8m, make it reusable for all i.MX8M SOCs. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mq: rename files for imx8mqBai Ping
For the i.MX8 media processor, we have i.MX8MQ and i.MX8MM etc. so rename the file name of imx8m_bl31_setup.c and imx8m_psci.c to imx8mq_xxx to make it more clear that these file is specific to i.MX8MQ. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: freescale: update the license identifier with SPDX short identifierBai Ping
clean up the license identifier with short SPDX short identifier. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11MLK-17591-2: CSU/RDC Add testing capabilitySilvano di Ninno
this patch adds some configuration to test CSU and RDC feature by default this is disable. to enable it add $(eval $(call add_define,CSU_RDC_TEST)) to the platform.mk file under plat/freescale/imx8mq/include this patch configure - CSU for GPIO5 to be secure only - RDC for Cortex A to be Domain ID 0 - GPIO4 to be rw by domain ID 2 to test, stops boot at uboot and run following command: u-boot=> md 0x3024000 03024000:"Synchronous Abort" handler, esr 0x96000210 ELR: 40257504 LR: 402574c0 x0 : 0000000000000009 x1 : 00000000308600b4 x2 : 00000000fdf28804 x3 : 0000000000000000 x4 : 0000000003024000 x5 : 00000000fdf73ad0 x6 : 0000000000000004 x7 : 000000000000000f x8 : 00000000fc8ff7e0 x9 : 0000000000000000 x10: 00000000fc8ff049 x11: 0000000000000021 x12: 0000000000000008 x13: 00000000ffffffff x14: 00000000fc8ffb1c x15: 00000000fc8ffc40 x16: 0000000000000000 x17: 0000000000000000 x18: 00000000fc907da0 x19: 0000000000000040 x20: 0000000000000004 x21: 0000000003024000 x22: 0000000003024000 x23: 00000000fdf7348d x24: 0000000000000008 x25: 0000000000000009 x26: 0000000000000004 x27: 0000000000000004 x28: 00000000fc8ff928 x29: 00000000fc8ff8a0 Resetting CPU ... resetting ... CPU tried to acces GPIO 5 registers and crashes u-boot=> md 0x30230000 30230000:"Synchronous Abort" handler, esr 0x96000210 ELR: 40257504 LR: 402574c0 x0 : 0000000000000009 x1 : 00000000308600b4 x2 : 00000000fdf28804 x3 : 0000000000000000 x4 : 0000000030230000 x5 : 00000000fdf73ad0 x6 : 0000000000000004 x7 : 000000000000000f x8 : 00000000fc8ff7e0 x9 : 0000000000000000 x10: 00000000fc8ff049 x11: 0000000000000021 x12: 0000000000000008 x13: 00000000ffffffff x14: 00000000fc8ffb1c x15: 00000000fc8ffc40 x16: 0000000000000000 x17: 0000000000000000 x18: 00000000fc907da0 x19: 0000000000000040 x20: 0000000000000004 x21: 0000000030230000 x22: 0000000030230000 x23: 00000000fdf7348d x24: 0000000000000008 x25: 0000000000000009 x26: 0000000000000004 x27: 0000000000000004 x28: 00000000fc8ff928 x29: 00000000fc8ff8a0 Resetting CPU ... resetting ... CPU tried to acces GPIO 4 registers and crashes Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-06-11MLK-17591-1: CSU Fix Slave configurationSilvano di Ninno
there is a bug in the CSL assignment. the CSL(n) and CSL(n+1) configuration were reversed. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-06-11plat: imx8mq: correct the reg offset of ddr type registerBai Ping
correct the ddr type register's offset. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mq: fix boot hang on ddr4/ddr3l boardBai Ping
Currently, DDR3L/DDR4 board don't support DDR DVFS, So skip ddr switch 3200 mts if the DDR is not LPDDR4. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mq: update the lpddr4 dvfs and retention flowBai Ping
Update the ddr retenton flow and dvfs flow used on imx8mq lpddr4 board. 1. DVFS flow is changed from hwffc to swffc. 2. frequency setpoint is change from 100mts to 667mts. 3. ddr retention flow is updated to compatible with the new lpddr4 training fw. 4. fix the retention failure issue caused by incorrect reset flow in retention exit. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11MLK-17253: Initialize caam sm at bootFranck LENORMAND
At boot, we reset the Secure Memory configuration for imx8mq to a default state giving all the job rings to linux and allowing all accesses from all SDIDs. NOTE: Checkpatch OK. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
2018-06-11plat: imx8mq: Improve the DDR DVFS flow on imx8mqBai Ping
Flush the L1 and L2 cache before DDR frequency change to make sure that no DDR memory access caused by cache activity. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11imx8mq: move stack to ocram_sPeng Fan
Add an ocram_s mmap entry Merge mmap entry to use 2MB aligned base and size to shrink the final mmu table size. Move stack to ocram_s Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-06-11MLK-17111: crypto: caam: Configure job rings master IDAymen Sghaier
For i.MX8MQ B0 revision the default configuration of JRaMID is not valid to allow Kernel use CAAM job ring. This patch set the Master ID of Cortex A in the JRaMID registers. Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
2018-06-11imx8mq: add SIP for NOC settingsAnson Huang
On i.MX8MQ, NOC may need different settings for different use cases, so add SIP for NOC settings. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11plat: imx: Update the DDR performance settingBai Ping
Update the DDR performance setting when out of retention. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11imx8mq: Add HAB supportYe Li
Since the HAB only works in secure mode. The BL33 runs at EL2 non-secure can't intialize the HAB successfully. So add the SIP call for these HAB interfaces, BL33 will trap to ATF to run the HAB. The HAB codes locates in ROM, and need to access OCRAM, CAAM RAM and DDR to authenticate image. Add these relevant memory region to MMU. Also extend the stack size of each core to avoid stack overflow by HAB. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-06-11imx8mq: disable default rdc and csu configurations to fix boot blockAymen Sghaier
Enabling the default csu configuration lead to block boot on testing boards. Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
2018-06-11imx8mq: Add rdc supportAymen Sghaier
Enable the RDC driver for i.MX8MQ platform with a default settings as an example. Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
2018-06-11imx8mq: Add csu supportAymen Sghaier
Enable the CSU driver for i.MX8MQ platform with a default settings as an example. Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
2018-06-11plat: imx8mq: fix the stack overflow issue on imx8mqBai Ping
the previous stack size is small, the stack will very easy to overflow, then lead to ATF not work. So increase the stack size to fix this issue. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mq: fix the system wakeup by non-wakeup IRQ.Bai Ping
When system enter suspend, it should be only wakeup by specific wakeup source, so non-wakeup source should be masked before enter suspend. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mq: enable cpuidle support on iMX8MQBai Ping
Refact the PSCI related code. Enable cpuidle support on i.MX8MQ for CPU idle support. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11imx: imx8mq: add SOC info SIP support for i.MX8MQAnson Huang
i.MX8MQ does NOT update revision info in ANATOP_DIGPROG register, so the revision info needs to read from ROM, for security reason, this needs to be done in ATF, so add this SIP support for kernel. The A0 chip's ROM version is located at 0x800, and B0 chip is located at 0x83c. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11imx8mq: add src sip to handle m4Peng Fan
Add src sip to handle M4 boot and status check Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-06-11plat: imx8mq: update the ddrc and phy configBai Ping
update the ddrc and phy config info, add more register config for other frequency point. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mq add ddr frequency support on imx8mqBai Ping
When changing the DDR frequency, the DDRC will block AXI access, so the code for changing the frequency need to be run on OCRAM not make sure no DDR access at this stage. the DDR frequency change request is from EL1 linux kernel side, we use the SiP service call to trap the DDR frequency change operation from linux kernel to ATF. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11imx8mq: pass TEE address and size to BL33Peng Fan
Pass TEE address space to BL33 to avoid uboot relocation touch this space. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-06-11plat: imx8mq add ddr retention support for imx8mqBai Ping
Enable the DDR retention support on imx8mq. when DDR retention is enabled, the non-fast wakeup mode can be enabled at the same time. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mq: add mmmap for aips1 spaceBai Ping
map the whole AIPS1 space, so we don't need to create map for individual peripheral region. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11imx8mq: add TEE supportPeng Fan
TEE entry is defined as 0xFE000000. When there is SPD passed to makefile , TEE_IMX8 will be defined. Compiling OP-TEE support using "make PLAT=imx8mq bl31 SPD=opteed" Note: Since TEE image is located at DRAM 0xFE000000, so need to reserve this space in UBoot and Kernel, by using gd->dram_size = PHYS_SDRAM_SIZE - SZ_32M or else. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-06-11imx8mq: change the BL31 load address to ocramBai Ping
Change the BL31 load address to ocram so we can put DDR into low power mode as needed. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11relocate the xlat_table section into ocram_sBai Ping
On i.MX8MQ, we may need to run ATF in ocram space, but the ocram space is limited, can NOT put all the sections into it, so move the xlat_table section into OCRAM_S. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11imx: replace all GPL with BSD identifier.Anson Huang
Replace all GPL with BSD identifier. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11imx8mq: gpc: correct ARM power down request register offsetAnson Huang
The GPC_CPU_PGC_SW_PDN_REQ offset should be 0xfc, previous offset is incorrect, so actually ARM core is NOT powered down and the power leakage is very high. With this fix, each ARM core's leakage is about 25mA@0.9V. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11fix sw pup/pdn issue on imx8mqBai Ping
The bits[3:0] of CPU_PGC_PUP/PDN_TRG use core's SW power up/down. prevous bits assignment is wrong, so fix it. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11i.mx8qm/i.mx8qxp: add SIP cpu-freq supportAnson Huang
Linux kernel will issue cpu-freq scale via SIP, ATF calls SCFW API to finish the CPU frequency scale. Move SIP service code from i.mx8mq to common place for all i.mx SoCs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11imx8mq: enable PU power domainAnson Huang
- USB PHY reset bit in SRC needs to be clear before doing USB PHY power gating in GPC, only needs to do once; - Need to handle GPC_PU_PWRHSK during power up/down; - Enable GPC pu power gate support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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