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32bit. So we use [32:1] as the configuration value
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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setup
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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ERR050044: GPU/VPU power domain on/off stress test leads
to unexpected GPU interrupts and hang.
his is caused by no dedicated HW resets for GPU2D/3D.
There is one reset for whole GPUmix and GPU2D/3D has their
own SW reset signals. The SW reset cannot be asserted while
GPU2D/3D is in power off status. So if only GPU2D or GPU3D
has to be powered off and on, unknown status leads to the problem.
VPU has similiar issue. So we need to assert the SW reset before
power up the power domain.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add DDR4 DVFS support for i.MX8M. Currently, only tested on i.MX8MM.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add ddr4 retention flow for imx8m.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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For i.MX8MM low power audio playback, when Linux suspend,
M4 still needs to be active for audio playback, so system
can NOT enter DSM mode but only force A core platform into
STOP mode, PLLs/NoC/DRAM need to be active as well and MU
interrupt wakeup needs to be enabled for waking up Linux
by MU message sent by M4.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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the GPU/VPU mix power off is skip in previous code,
so correct to make sure GPU/VPU mix is actually power
off.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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csu_rdc test in ATF makes use of GPIO 4 and 5. Unfortunatly GPIO5 is
being used by u-boot. This is why u-boot crashes.
Changing the peripherals to protect, instead of gpio4 and 5, use csu
and rdc registers instead.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
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If NOC is power down in DSM mode, the tz380 register config
will be lost, so we must re-init the tz380 after system resume.
the tz380 initialization must be done after DRAM has been out
of retention.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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enable NOC power down in DSM mode.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Enable the power domain support on imx8mm.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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add LPDDR4 DVFS support on imx8mm.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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All the DRAM timing related config is saved by SPL in OCRAM_S,
so no need to do save for these configs in ATF anymore.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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On i.MX8MM, the OCRAM's last 128K is dedicated for ATF, so move
bl31 to this memory region.
BuildInfo:
- IMX-MKIMAGE: ee5ad91b
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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The debug version of TF-A has below assert, fix
it by making sure no memory map overlap.
ASSERT: lib/xlat_tables/xlat_tables_common.c:129
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Switch to MULTI_CONSOLE_API to make debug UART work.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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This patch enables necessary erratas for A53 r0p4
according to docs/cpu-specific-build-macros.rst.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Only enable the wakeup irq when system enter DSM mode.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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use ARRAY_SIZE to get the array size.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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enable DSM mode on i.MX8MM.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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re-design the dram power management code to make it more
common for all i.MX8M SOCs. code need to refact and optimize
to make more better. Using this common code on i.MX8MM first,
for i.MX8MQ, will move to this later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Switch the CKIL clock source to 32K OSC. On i.MX8MM,
after SOC PoR, the default clock source for CKIL is from
divided 24MHz OSC, as 24MHz OSC will be power down when
system enters DSM mdoe. So it is better to use 32K OSC
as the default clock source after system bootup.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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VPU, GPU and PCIE's clock need to be on before power on
these power domains.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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When system enter deepest cpuilde(WAIT mode), the L2 cache memory
can be on for retention to increase the system performance. So
the WAIT mode with cluster power down should be defined as
rentention power state in PSCI. changing the WAIT_OFF_STATE to
WAIT_RET_STATE to make sure the l2 cache memory is not
clean & invalidate.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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A53 WAIT mode is specific for OS cpuilde. The MASTER1 & MASTER2
mapping in A53 domain should be clear, otherwise the 'noc2supermix'
and 'supermix2noc' ADB400 async port will be power down when A53
enters WAIT mode.If the ADB400 is power down in WAIT mode, all the bus
request from supermix to noc wrapper will be blocked.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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- configure Secure memory partition
- allocate all CAAM JR to Linux
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
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move CSU and RDC driver to common/i.mx8m folder
and enable the driver for i.mx8mm
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
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fix entry point for the OP-TEE
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
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Enable the WAIT mode support in cpuilde to save power.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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cleanup XLAT and STACK defines
the OCRAM size for ATF is big enough for i.MX 8mm
there is no need to move code to OCRAM_S
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Acked-by: Jacky Bai <ping.bai@nxp.com>
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Similar to imx8mq, the U-boot calls SIP call for HAB interfaces, and trap to ATF
to run the HAB.
Since HAB codes locates in ROM, and need to access OCRAM, CAAM RAM and DDR to
authenticate image. Add these relevant memory region to MMU. Also extend the
stack size of each core to avoid stack overflow, and extend the BL31 limit
to OCRAM end 0x940000.
Signed-off-by: Ye Li <ye.li@nxp.com>
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i.MX8MM is a new soc of the i.MX8M family, this patch
add the basic support for i.MX8MM. further code optimization
needed. WAIT mode support is currently disabled, will be enabled
later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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