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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Add DDR4 DVFS support for i.MX8M. Currently, only tested on i.MX8MM.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add ddr4 retention flow for imx8m.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Enable the power domain support on imx8mm.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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add LPDDR4 DVFS support on imx8mm.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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All the DRAM timing related config is saved by SPL in OCRAM_S,
so no need to do save for these configs in ATF anymore.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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This patch enables necessary erratas for A53 r0p4
according to docs/cpu-specific-build-macros.rst.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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re-design the dram power management code to make it more
common for all i.MX8M SOCs. code need to refact and optimize
to make more better. Using this common code on i.MX8MM first,
for i.MX8MQ, will move to this later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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move CSU and RDC driver to common/i.mx8m folder
and enable the driver for i.mx8mm
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
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cleanup XLAT and STACK defines
the OCRAM size for ATF is big enough for i.MX 8mm
there is no need to move code to OCRAM_S
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Acked-by: Jacky Bai <ping.bai@nxp.com>
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i.MX8MM is a new soc of the i.MX8M family, this patch
add the basic support for i.MX8MM. further code optimization
needed. WAIT mode support is currently disabled, will be enabled
later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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