Age | Commit message (Collapse) | Author |
|
re-enable csu and rdc test for use of the test team
only enable if CSU_RDC_TEST is defined.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
(cherry picked from commit 2eb979f144f1c008f64d4550035ece0ad69a2365)
|
|
DRAM MMU settings miss the MT_NS on iMX8MM/MN/MP, this breaks the
HAB function since we load image by u-boot in NS mode and authenticate
it in ATF. Without MT_NS, ATF access secure memory which is different
cacheline with non-secure memory.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
|
|
On i.MX8MP, the SRC GPR9(0x94) is used by memory repair, so choose
SRC GPR10(0x98) as the LPA status sync register. Add use '==' instead
of '&' for LPA active statue check.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
|
|
Support stop M7 with SIP call.
Per IC team, to rekick M7 need follow steps.
If M7 already in WFI, perform below steps.
a) Set [0x303A_002C].0=0 [ request SLEEPHOLDREQn ]
b) Wait [0x303A_00EC].1 = 0 [ wait SLEEPHOLDACKn ]
c) Set GPR.CPUWAIT=1
d) Set [0x303A_002C].0=1 [ de-assert SLEEPHOLDREQn ]
e) Set SRC_M7_RCR[3:0] = 0xE0 [ reset M7 core/plat ]
f) Wait SRC_M7_RCR[3:0] = 0x8
g) Init TCM or DDR
h) Set GPR.INITVTOR
i) Set GPR.CPUWAIT=0, M7 starting running
Add a timeout check, if timeout, still perform force reset, in this
way no need to rely on M7 team's image wfi support ready.
Return a1,a2 to caller to check timeout or reset fail.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
|
On i.MX8MN & i.MX8MP, the M core enabled check should
relay on the IOMUX GPR CPU_WAIT bit, when this bit is
cleared, it means M core is active & running, so refine
the m4 enabled check method.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
move the gpc reg offset, bit define & macro to a separate header
file for code reuse.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Align code style between 8mq, 8mm and 8mn files.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
|
|
Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
|
|
Add trusty support for imx8mn, default load address and
size of trusty are 0xbe000000 and 0x2000000.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from commit 1566947ab431388906d71a1fb48e802fc9a1eec9)
|
|
spd trusty requires memory dynamic mapping feature to be
enabled, so we have to use xlat table library v2 instead
of v1.
Test: builds.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
|
|
Replace the magic number index with enum type to make RDC/CSU config
more clear for user.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the M core low power audio support on i.MX8M.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Enable the NOC wrapper power down support for SoC that
have switchable NOC power domain.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the SRC SiP handler for M4/M7 boot support on i.MX8M SoC.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the HAB secure boot support for the i.MX8M SoC family.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the CSU init on i.MX8MN & config the ocram
secure access range. CSU config for specific
system design can be added in the 'csu_cfg' array.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
No need to keep all PU domains on as the full power domain driver
support has been added.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the PU power domain support for imx8mm/mn.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add the DDR frequency change support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I84f0ef51b04b84da8ba2cbeca86a07338a4903de
|
|
Enable dram retention support on i.MX8MN.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|
|
Add imx8mn basic support
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
|